[bsp/old stm32 bsp]remove old stm32 bsp

.travis.yml

@@ -29,16 +29,16 @@ env:
 #  - RTT_BSP='avr32uc3b0' RTT_TOOL_CHAIN='atmel-avr32'
 #  - RTT_BSP='bf533' # no scons
   - RTT_BSP='efm32' RTT_TOOL_CHAIN='sourcery-arm' 
-#  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm' 
+#  - RTT_BSP='gd32450z-eval' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='gkipc' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='lm3s8962' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lm3s9b9x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lm4f232' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='tm4c129x' RTT_TOOL_CHAIN='sourcery-arm'
-  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='lpc176x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc178x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc2148' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='lpc2478' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc43xx/M4' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='lpc408x' RTT_TOOL_CHAIN='sourcery-arm'
@@ -46,14 +46,14 @@ env:
 #  - RTT_BSP='lpc54608-LPCXpresso' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='ls1bdev' RTT_TOOL_CHAIN='sourcery-mips'
   - RTT_BSP='ls1cdev' RTT_TOOL_CHAIN='sourcery-mips'
-  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='imx6sx/cortex-a9' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='m16c62p' # m32c
-  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='mb9bf500r' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='mb9bf506r' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='mb9bf618s' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='mb9bf568r' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='microblaze' # no scons
-  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='mini2440' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='mini4020' # no scons
 #  - RTT_BSP='nios_ii' # no scons
   - RTT_BSP='nuvoton_nuc472' RTT_TOOL_CHAIN='sourcery-arm'
@@ -63,25 +63,21 @@ env:
   - RTT_BSP='qemu-vexpress-gemini' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='sam7x' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='simulator' # x86
-  - RTT_BSP='stm32f0x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l072' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f107' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f40x' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm' 
-  - RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm' 
+  - RTT_BSP='stm32f10x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f10x-HAL' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f4xx-HAL' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f429-apollo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32f429-disco' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f091-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f103-atk-warshipv3' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-dofly-lyc8' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f103-hw100k-ibox' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f107-uc-eval' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32f405-smdz-breadfruit' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f407-st-discovery' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32f411-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
@@ -98,6 +94,7 @@ env:
   - RTT_BSP='stm32/stm32l432-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32l475-atk-pandora' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='stm32/stm32l476-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
+  - RTT_BSP='stm32/stm32l496-ali-developer' RTT_TOOL_CHAIN='sourcery-arm'
   - RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
 #  - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
 #  - RTT_BSP='upd70f3454' # iar

bsp/stm32f0x/Libraries/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd

@@ -1,274 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- 
-  @date: 29.07.2011
-  @note    Copyright (C) 2011 ARM Limited. All rights reserved.
-  @par
-   ARM Limited (ARM) is supplying this software for use with Cortex-M
-   processor based microcontroller, but can be equally used for other
-   suitable  processor architectures. This file can be freely distributed.
-   Modifications to this file shall be clearly marked.
-
-  @par
-   THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-   OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-   ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-   CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- -->
-
-<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
-  
-  <xs:simpleType name="registerNameType">
-    <xs:restriction base="xs:string">
-      <xs:pattern value="([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="dimIndexType">
-    <xs:restriction base="xs:string">
-      <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="scaledNonNegativeInteger">
-    <xs:restriction base="xs:string">
-      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="enumeratedValueDataType">
-    <xs:restriction base="xs:string">
-      <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="accessType">
-    <xs:restriction base="xs:token">
-      <xs:enumeration value="read-only"/>
-      <xs:enumeration value="write-only"/>
-      <xs:enumeration value="read-write"/>
-      <xs:enumeration value="writeOnce"/>
-      <xs:enumeration value="read-writeOnce"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="modifiedWriteValuesType">
-    <xs:restriction base="xs:token">
-      <xs:enumeration value="oneToClear"/>
-      <xs:enumeration value="oneToSet"/>
-      <xs:enumeration value="oneToToggle"/>
-      <xs:enumeration value="zeroToClear"/>
-      <xs:enumeration value="zeroToSet"/>
-      <xs:enumeration value="zeroToToggle"/>
-      <xs:enumeration value="clear"/>
-      <xs:enumeration value="set"/>
-      <xs:enumeration value="modify"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="readActionType">
-    <xs:restriction base="xs:token">
-      <xs:enumeration value="clear"/>
-      <xs:enumeration value="set"/>
-      <xs:enumeration value="modify"/>
-      <xs:enumeration value="modifyExternal"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="enumUsageType">
-    <xs:restriction base="xs:token">
-      <xs:enumeration value="read"/>
-      <xs:enumeration value="write"/>
-      <xs:enumeration value="read-write"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:simpleType name="bitRangeType">
-    <xs:restriction base="xs:token">
-      <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
-    </xs:restriction>
-  </xs:simpleType>
-
-  <xs:complexType name="writeConstraintType">
-    <xs:choice>
-      <xs:element name="writeAsRead" type="xs:boolean"/>
-      <xs:element name="useEnumeratedValues" type="xs:boolean"/>
-      <xs:element name="range">
-        <xs:complexType>
-          <xs:sequence>
-            <xs:element name="minimum" type="scaledNonNegativeInteger"/>
-            <xs:element name="maximum" type="scaledNonNegativeInteger"/>
-          </xs:sequence>
-        </xs:complexType>
-      </xs:element>
-    </xs:choice>
-  </xs:complexType>
-
-  <xs:complexType name="addressBlockType">
-    <xs:sequence>
-      <xs:element name="offset" type="scaledNonNegativeInteger"/>
-      <xs:element name="size" type="scaledNonNegativeInteger"/>
-      <xs:element name="usage">
-        <xs:simpleType>
-          <xs:restriction base="xs:token">
-            <xs:enumeration value="registers"/>
-            <xs:enumeration value="buffer"/>
-            <xs:enumeration value="reserved"/>
-          </xs:restriction>
-        </xs:simpleType>
-      </xs:element>
-    </xs:sequence>
-  </xs:complexType>
-
-  <xs:complexType name="interruptType">
-    <xs:sequence>
-      <xs:element name="name" type="xs:string"/>
-      <xs:element name="value" type="xs:integer"/>
-    </xs:sequence>
-  </xs:complexType>
-
-  <xs:group name="registerPropertiesGroup">
-    <xs:sequence>
-      <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
-      <xs:element name="access" type="accessType" minOccurs="0"/>
-      <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
-      <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
-    </xs:sequence>
-  </xs:group>
-
-  <xs:group name="bitRangeLsbMsbStyle">
-    <xs:sequence>
-      <xs:element name="lsb"  type="scaledNonNegativeInteger"/>
-      <xs:element name="msb"  type="scaledNonNegativeInteger"/>
-    </xs:sequence>
-  </xs:group>
-
-  <xs:group name="bitRangeOffsetWidthStyle">
-    <xs:sequence>
-      <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
-      <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>   
-    </xs:sequence> 
-  </xs:group>
-
-  <xs:group name="dimElementGroup">
-    <xs:sequence>
-      <xs:element name="dim" type="scaledNonNegativeInteger"/>
-      <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
-      <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
-    </xs:sequence>
-  </xs:group>
-
-  <xs:element name="device" nillable="true">
-    <xs:complexType>
-      <xs:sequence>
-        <xs:element name="name" type="xs:string"/>
-        <xs:element name="version" type="xs:string"/>
-        <xs:element name="description" type="xs:string"/>
-        <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
-        <xs:element name="width" type="scaledNonNegativeInteger"/>
-        <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
-        <xs:element name="peripherals">
-          <xs:complexType>
-            <xs:sequence>
-              <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
-                <xs:complexType>
-                  <xs:sequence>
-                    <xs:element name="name" type="xs:Name"/>
-                    <xs:element name="version" type="xs:string" minOccurs="0"/>
-                    <xs:element name="description" type="xs:string" minOccurs="0"/>
-                    <xs:element name="groupName" type="xs:string" minOccurs="0"/>
-                    <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
-                    <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
-                    <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
-                    <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
-                    <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
-                    <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
-                    <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
-                    <xs:element name="registers" minOccurs="0" maxOccurs="1">
-                      <xs:complexType>
-                        <xs:sequence>
-                          <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
-                            <xs:complexType>
-                              <xs:sequence>
-                                <xs:group ref="dimElementGroup" minOccurs="0"/>
-                                <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
-                                <xs:element name="displayName" type="xs:string" minOccurs="0"/>
-                                <xs:element name="description" type="xs:string" minOccurs="0"/>
-                                <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
-                                <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
-                                <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
-                                <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
-                                <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
-                                <xs:element name="readAction" type="readActionType" minOccurs="0"/>
-                                <xs:element name="fields" minOccurs="0" maxOccurs="1">
-                                  <xs:complexType>
-                                    <xs:sequence>
-                                      <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
-                                      <xs:complexType>
-                                        <xs:sequence>
-                                          <xs:element name="name" type="xs:string"/>
-                                          <xs:element name="description" type="xs:string" minOccurs="0"/>
-                                          <xs:choice>
-                                            <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
-                                            <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
-                                            <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
-                                          </xs:choice>
-                                          <xs:element name="access" type="accessType" minOccurs="0"/>
-                                          <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
-                                          <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
-                                          <xs:element name="readAction" type="readActionType" minOccurs="0"/>
-                                          <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
-                                            <xs:complexType>
-                                              <xs:sequence>
-                                                <xs:element name="name" type="xs:Name" minOccurs="0"/>
-                                                <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
-                                                <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
-                                                  <xs:complexType>
-                                                    <xs:sequence>
-                                                      <xs:element name="name" type="xs:string"/>
-                                                      <xs:element name="description" type="xs:string" minOccurs="0"/>
-                                                      <xs:choice>
-                                                        <xs:element name="value" type="enumeratedValueDataType"/>
-                                                        <xs:element name="isDefault" type="xs:boolean"/>
-                                                      </xs:choice>
-                                                    </xs:sequence>
-                                                  </xs:complexType>
-                                                </xs:element>
-                                              </xs:sequence>
-                                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
-                                            </xs:complexType>
-                                          </xs:element>
-                                        </xs:sequence>
-                                        <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
-                                      </xs:complexType>
-                                    </xs:element>
-                                    </xs:sequence>
-                                  </xs:complexType>
-                                </xs:element>
-                              </xs:sequence>
-                              <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
-                            </xs:complexType>
-                          </xs:element>
-                        </xs:sequence>
-                      </xs:complexType>
-                    </xs:element>
-                  </xs:sequence>
-                  <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
-                </xs:complexType>
-              </xs:element>
-            </xs:sequence>
-          </xs:complexType>
-        </xs:element>
-        <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
-          <xs:complexType>
-            <xs:sequence>
-              <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
-              </xs:any>
-            </xs:sequence>
-          </xs:complexType>
-        </xs:element>
-      </xs:sequence>
-      <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
-    </xs:complexType>
-  </xs:element>
-</xs:schema>

bsp/stm32f0x/Libraries/CMSIS/Documentation/CMSIS_CM4_SIMD.htm

@@ -1,3809 +0,0 @@
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-    -->
-</style>
-</head>
-
-<body>
-
-<h1>CMSIS Support for Cortex-M4 SIMD Instructions</h1>
-
-<p align="center">This file describes the Cortex-M4 SIMD instructions supported by CMSIS.</p>
-<p align="center">Version: 1.00 - 25. November 2010</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<h2>Revision History</h2>
-<ul>
-	<li>Revision 0.01 - January 2010: Initial version</li>
-	<li>Revision 0.02 - June 2010: added __QADD, __QSUB</li>
-	<li>Revision 1.00 - November 2010: </li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#About">About</a></li>
-  <li class="LI2"><a href="#CM4-SIMD-Instructions">Cortex-M4 SIMD instruction support</a></li>
-  <li class="LI2"><a href="#Examples">Examples</a></li>
-</ol>
-
-
-
-<p>&nbsp;</p>
-<h2><a name="About"></a>About</h2>
-<p>
-  CMSIS provides for the Cortex-M4 a set of functions supporting Cortex-M4 SIMD instructions.
-</p>
-
-<p>&nbsp;</p>
-<h2><a name="CM4-SIMD-Instructions"></a>Cortex-M4 SIMD instruction support</h2>
-<p>CMSIS supports the following functions for Cortex-M4 instructions:
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Name</th>
-      <th class="kt">Mnemonic</th>
-      <th class="kt">Description</th>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SADD8">__SADD8</a></b></td>
-      <td class="kt">SADD8</td>
-      <td class="kt">GE setting quad 8-bit signed addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QADD8">__QADD8</a></b></td>
-      <td class="kt">QADD8</td>
-      <td class="kt">Q setting quad 8-bit saturating addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHADD8">__SHADD8</a></b></td>
-      <td class="kt">SHADD8</td>
-      <td class="kt">Quad 8-bit signed addition with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UADD8">__UADD8</a></b></td>
-      <td class="kt">UADD8</td>
-      <td class="kt">GE setting quad 8-bit unsigned addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQADD8">__UQADD8</a></b></td>
-      <td class="kt">UQADD8</td>
-      <td class="kt">Quad 8-bit unsigned saturating addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHADD8">__UHADD8</a></b></td>
-      <td class="kt">UHADD8</td>
-      <td class="kt">Quad 8-bit unsigned addition with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SSUB8">__SSUB8</a></b></td>
-      <td class="kt">SSUB8</td>
-      <td class="kt">GE setting quad 8-bit signed subtraction</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QSUB8">__QSUB8</a></b></td>
-      <td class="kt">QSUB8</td>
-      <td class="kt">Q setting quad 8-bit saturating subtract</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHSUB8">__SHSUB8</a></b></td>
-      <td class="kt">SHSUB8</td>
-      <td class="kt">Quad 8-bit signed subtraction with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USUB8">__USUB8</a></b></td>
-      <td class="kt">USUB8</td>
-      <td class="kt">GE setting quad 8-bit unsigned subtract</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQSUB8">__UQSUB8</a></b></td>
-      <td class="kt">UQSUB8</td>
-      <td class="kt">Quad 8-bit unsigned saturating subtraction</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHSUB8">__UHSUB8</a></b></td>
-      <td class="kt">UHSUB8</td>
-      <td class="kt">Quad 8-bit unsigned subtraction with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SADD16">__SADD16</a></b></td>
-      <td class="kt">SADD16</td>
-      <td class="kt">GE setting dual 16-bit signed addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QADD16">__QADD16</a></b></td>
-      <td class="kt">QADD16</td>
-      <td class="kt">Q setting dual 16-bit saturating addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHADD16">__SHADD16</a></b></td>
-      <td class="kt">SHADD16</td>
-      <td class="kt">Dual 16-bit signed addition with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UADD16">__UADD16</a></b></td>
-      <td class="kt">UADD16</td>
-      <td class="kt">GE setting dual 16-bit unsigned addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQADD16">__UQADD16</a></b></td>
-      <td class="kt">UQADD16</td>
-      <td class="kt">Dual 16-bit unsigned saturating addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHADD16">__UHADD16</a></b></td>
-      <td class="kt">UHADD16</td>
-      <td class="kt">Dual 16-bit unsigned addition with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SSUB16">__SSUB16</a></b></td>
-      <td class="kt">SSUB16</td>
-      <td class="kt">GE setting dual 16-bit signed subtraction</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QSUB16">__QSUB16</a></b></td>
-      <td class="kt">QSUB16</td>
-      <td class="kt">Q setting dual 16-bit saturating subtract</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHSUB16">__SHSUB16</a></b></td>
-      <td class="kt">SHSUB16</td>
-      <td class="kt">Dual 16-bit signed subtraction with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USUB16">__USUB16</a></b></td>
-      <td class="kt">USUB16</td>
-      <td class="kt">GE setting dual 16-bit unsigned subtract</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQSUB16">__UQSUB16</a></b></td>
-      <td class="kt">UQSUB16</td>
-      <td class="kt">Dual 16-bit unsigned saturating subtraction</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHSUB16">__UHSUB16</a></b></td>
-      <td class="kt">UHSUB16</td>
-      <td class="kt">Dual 16-bit unsigned subtraction with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SASX">__SASX</a></b></td>
-      <td class="kt">SASX</td>
-      <td class="kt">GE setting dual 16-bit addition and subtraction with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QASX">__QASX</a></b></td>
-      <td class="kt">QASX</td>
-      <td class="kt">Q setting dual 16-bit add and subtract with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHASX">__SHASX</a></b></td>
-      <td class="kt">SHASX</td>
-      <td class="kt">Dual 16-bit signed addition and subtraction with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UASX">__UASX</a></b></td>
-      <td class="kt">UASX</td>
-      <td class="kt">GE setting dual 16-bit unsigned addition and subtraction with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQASX">__UQASX</a></b></td>
-      <td class="kt">UQASX</td>
-      <td class="kt">Dual 16-bit unsigned saturating addition and subtraction with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHASX">__UHASX</a></b></td>
-      <td class="kt">UHASX</td>
-      <td class="kt">Dual 16-bit unsigned addition and subtraction with halved results and exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SSAX">__SSAX</a></b></td>
-      <td class="kt">SSAX</td>
-      <td class="kt">GE setting dual 16-bit signed subtraction and addition with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QSAX">__QSAX</a></b></td>
-      <td class="kt">QSAX</td>
-      <td class="kt">Q setting dual 16-bit subtract and add with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SHSAX">__SHSAX</a></b></td>
-      <td class="kt">SHSAX</td>
-      <td class="kt">Dual 16-bit signed subtraction and addition with halved results</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USAX">__USAX</a></b></td>
-      <td class="kt">USAX</td>
-      <td class="kt">GE setting dual 16-bit unsigned subtract and add with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UQSAX">__UQSAX</a></b></td>
-      <td class="kt">UQSAX</td>
-      <td class="kt">Dual 16-bit unsigned saturating subtraction and addition with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UHSAX">__UHSAX</a></b></td>
-      <td class="kt">UHSAX</td>
-      <td class="kt">Dual 16-bit unsigned subtraction and addition with halved results and exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USAD8">__USAD8</a></b></td>
-      <td class="kt">USAD8</td>
-      <td class="kt">Unsigned sum of quad 8-bit unsigned absolute difference</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USADA8">__USADA8</a></b></td>
-      <td class="kt">USADA8</td>
-      <td class="kt">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SSAT16">__SSAT16</a></b></td>
-      <td class="kt">SSAT16</td>
-      <td class="kt">Q setting dual 16-bit saturate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__USAT16">__USAT16</a></b></td>
-      <td class="kt">USAT16</td>
-      <td class="kt">Q setting dual 16-bit unsigned saturate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UXTB16">__UXTB16</a></b></td>
-      <td class="kt">UXTB16</td>
-      <td class="kt">Dual extract 8-bits and zero-extend to 16-bits</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__UXTAB16">__UXTAB16</a></b></td>
-      <td class="kt">UXTAB16</td>
-      <td class="kt">Extracted 16-bit to 32-bit unsigned addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SXTB16">__SXTB16</a></b></td>
-      <td class="kt">SXTB16</td>
-      <td class="kt">Dual extract 8-bits and sign extend each to 16-bits</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SXTAB16">__SXTAB16</a></b></td>
-      <td class="kt">SXTAB16</td>
-      <td class="kt">Dual extracted 8-bit to 16-bit signed addition</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMUAD">__SMUAD</a></b></td>
-      <td class="kt">SMUAD</td>
-      <td class="kt">Q setting sum of dual 16-bit signed multiply</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMUADX">__SMUADX</a></b></td>
-      <td class="kt">SMUADX</td>
-      <td class="kt">Q setting sum of dual 16-bit signed multiply with exchange</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLAD">__SMLAD</a></b></td>
-      <td class="kt">SMLAD</td>
-      <td class="kt">Q setting dual 16-bit signed multiply with single 32-bit accumulator</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLADX">__SMLADX</a></b></td>
-      <td class="kt">SMLADX</td>
-      <td class="kt">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLALD">__SMLALD</a></b></td>
-      <td class="kt">SMLALD</td>
-      <td class="kt">Dual 16-bit signed multiply with single 64-bit accumulator</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLALDX">__SMLALDX</a></b></td>
-      <td class="kt">SMLALDX</td>
-      <td class="kt">Dual 16-bit signed multiply with exchange with single 64-bit accumulator</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMUSD">__SMUSD</a></b></td>
-      <td class="kt">SMUSD</td>
-      <td class="kt">Dual 16-bit signed multiply returning difference</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMUSDX">__SMUSDX</a></b></td>
-      <td class="kt">SMUSDX</td>
-      <td class="kt">Dual 16-bit signed multiply with exchange returning difference</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLSD">__SMLSD</a></b></td>
-      <td class="kt">SMLSD</td>
-      <td class="kt">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLSDX">__SMLSDX</a></b></td>
-      <td class="kt">SMLSDX</td>
-      <td class="kt">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLSLD">__SMLSLD</a></b></td>
-      <td class="kt">SMLSLD</td>
-      <td class="kt">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SMLSLDX">__SMLSLDX</a></b></td>
-      <td class="kt">SMLSLDX</td>
-      <td class="kt">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__SEL">__SEL</a></b></td>
-      <td class="kt">SEL</td>
-      <td class="kt">Select bytes based on GE bits</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QADD">__QADD</a></b></td>
-      <td class="kt">QADD</td>
-      <td class="kt">Q setting saturating add</td>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#__QSUB">__QSUB</a></b></td>
-      <td class="kt">QSUB/td>
-      <td class="kt">Q setting saturating subtract</td>
-    </tr>
-
-    </tbody>
-</table>
-
-<!-- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------     -->
-<!-- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------     -->
-
-<h3><a name="__SADD8"></a>Function __SADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four 8-bit signed integer additions.<br>
-          The GE bits in the APSR are set according to the results of the additions.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands.</li>
-          <li><b>val2</b>: second four 8-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the first bytes from each operand, in the first byte of the return value.</li>
-            <li>the addition of the second bytes of each operand, in the second byte of the return value.</li>
-            <li>the addition of the third bytes of each operand, in the third byte of the return value.</li>
-            <li>the addition of the fourth bytes of each operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[7:0] &ge; 0 then APSR.GE[0] = 1 else 0</li>
-            <li>if res[15:8] &ge; 0 then APSR.GE[1] = 1 else 0</li>
-            <li>if res[23:16] &ge; 0 then APSR.GE[2] = 1 else 0</li>
-            <li>if res[31:24] &ge; 0 then APSR.GE[3] = 1 else 0</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   + val2[7:0]
-res[15:8]  = val1[15:8]  + val2[15:8]
-res[23:16] = val1[23:16] + val2[23:16]
-res[31:24] = val1[31:24] + val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QADD8"></a>Function __QADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four 8-bit integer additions, saturating the results to 
-          the 8-bit signed integer range -2<sup>7</sup> &le; x &le; 2<sup>7</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands.</li>
-          <li><b>val2</b>: second four 8-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the saturated addition of the first byte of each operand in the first byte of the return value.</li>
-            <li>the saturated addition of the second byte of each operand in the second byte of the return value.</li>
-            <li>the saturated addition of the third byte of each operand in the third byte of the return value.</li>
-            <li>the saturated addition of the fourth byte of each operand in the fourth byte of the return value.</li>
-          </ul>
-          <p>The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> &le; x &le; 2<sup>7</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   + val2[7:0]
-res[15:8]  = val1[15:8]  + val2[15:8]
-res[23:16] = val1[23:16] + val2[23:16]
-res[31:24] = val1[31:24] + val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHADD8"></a>Function __SHADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four signed 8-bit integer additions, halving the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands.</li>
-          <li><b>val2</b>: second four 8-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the first bytes from each operand, in the first byte of the return value.</li>
-            <li>the halved addition of the second bytes from each operand, in the second byte of the return value.</li>
-            <li>the halved addition fo the third bytes from each operand, in the third byte of the return value.</li>
-            <li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = (val1[7:0]   + val2[7:0])   &gt;&gt; 1
-res[15:8]  = (val1[15:8]  + val2[15:8])  &gt;&gt; 1
-res[23:16] = (val1[23:16] + val2[23:16]) &gt;&gt; 1
-res[31:24] = (val1[31:24] + val2[31:24]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UADD8"></a>Function __UADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit integer additions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands for each addition.</li>
-          <li><b>val2</b>: second four 8-bit summands for each addition.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the first bytes in each operand, in the first byte of the return value.</li>
-            <li>the addition of the second bytes in each operand, in the second byte of the return value.</li>
-            <li>the addition of the third bytes in each operand, in the third byte of the return value.</li>
-            <li>the addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[7:0] &ge; 0x100 then APSR.GE[0] = 1 else 0</li>
-            <li>if res[15:8] &ge; 0x100 then APSR.GE[1] = 1 else 0</li>
-            <li>if res[23:16] &ge; 0x100 then APSR.GE[2] = 1 else 0</li>
-            <li>if res[31:24] &ge; 0x100 then APSR.GE[3] = 1 else 0</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   + val2[7:0]
-res[15:8]  = val1[15:8]  + val2[15:8]
-res[23:16] = val1[23:16] + val2[23:16]
-res[31:24] = val1[31:24] + val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQADD8"></a>Function __UQADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit integer additions, saturating the 
-          results to the 8-bit unsigned integer range 0 &le; x &le; 2<sup>8</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands.</li>
-          <li><b>val2</b>: second four 8-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the first bytes in each operand, in the first byte of the return value.</li>
-            <li>the addition of the second bytes in each operand, in the second byte of the return value.</li>
-            <li>the addition of the third bytes in each operand, in the third byte of the return value.</li>
-            <li>the addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 8-bit unsigned integer range 0 &le; x &le; 2<sup>8</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   + val2[7:0]
-res[15:8]  = val1[15:8]  + val2[15:8]
-res[23:16] = val1[23:16] + val2[23:16]
-res[31:24] = val1[31:24] + val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHADD8"></a>Function __UHADD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit integer additions, halving the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit summands.</li>
-          <li><b>val2</b>: second four 8-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the first bytes in each operand, in the first byte of the return value.</li>
-            <li>the halved addition of the second bytes in each operand, in the second byte of the return value.</li>
-            <li>the halved addition of the third bytes in each operand, in the third byte of the return value.</li>
-            <li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = (val1[7:0]   + val2[7:0])   &gt;&gt; 1
-res[15:8]  = (val1[15:8]  + val2[15:8])  &gt;&gt; 1
-res[23:16] = (val1[23:16] + val2[23:16]) &gt;&gt; 1
-res[31:24] = (val1[31:24] + val2[31:24]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SSUB8"></a>Function __SSUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SSUB8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four 8-bit signed integer subtractions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands of each subtraction.</li>
-          <li><b>val2</b>: second four 8-bit operands of each subtraction.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand, in the first bytes of the return value.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand, in the second byte of the return value.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand, in the third byte of the return value.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation. If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[8:0] &ge; 0 then APSR.GE[0] = 1 else 0</li>
-            <li>if res[15:8] &ge; 0 then APSR.GE[1] = 1 else 0</li>
-            <li>if res[23:16] &ge; 0 then APSR.GE[2] = 1 else 0</li>
-            <li>if res[31:24] &ge; 0 then APSR.GE[3] = 1 else 0</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   - val2[7:0]
-res[15:8]  = val1[15:8]  - val2[15:8]
-res[23:16] = val1[23:16] - val2[23:16]
-res[31:24] = val1[31:24] - val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QSUB8"></a>Function __QSUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QADD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four 8-bit integer subtractions, saturating the results 
-          to the 8-bit signed integer range -2<sup>7</sup> &le; x &le; 2<sup>7</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands.</li>
-          <li><b>val2</b>: second four 8-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand, in the first byte of the return value.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand, in the second byte of the return value.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand, in the third byte of the return value.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> &le; x &le; 2<sup>7</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   - val2[7:0]
-res[15:8]  = val1[15:8]  - val2[15:8]
-res[23:16] = val1[23:16] - val2[23:16]
-res[31:24] = val1[31:24] - val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHSUB8"></a>Function __SHSUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHSUB8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four signed 8-bit integer subtractions, halving the 
-          results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands.</li>
-          <li><b>val2</b>: second four 8-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the first byte in the second operand from the first byte 
-                in the first operand, in the first byte of the return value.</li>
-            <li>the halved subtraction of the second byte in the second operand from the second 
-                byte in the first operand, in the second byte of the return value.</li>
-            <li>the halved subtraction of the third byte in the second operand from the third byte 
-                in the first operand, in the third byte of the return value.</li>
-            <li>the halved subtraction of the fourth byte in the second operand from the fourth 
-                byte in the first operand, in the fourth byte of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = (val1[7:0]   - val2[7:0])  &gt;&gt; 1
-res[15:8]  = (val1[15:8]  - val2[15:8]) &gt;&gt; 1
-res[23:16] = (val1[23:16] - val2[23:16] &gt;&gt; 1
-res[31:24] = (val1[31:24] - val2[31:24] &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USUB8"></a>Function __USUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USUB8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function It enables you to perform four 8-bit unsigned integer subtractions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands.</li>
-          <li><b>val2</b>: second four 8-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand, in the first byte of the return value.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand, in the second byte of the return value.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand, in the third byte of the return value.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[7:0] &ge; 0 then APSR.GE[0] = 1 else 0</li>
-            <li>if res[15:8] &ge; 0 then APSR.GE[1] = 1 else 0</li>
-            <li>if res[23:16] &ge; 0 then APSR.GE[2] = 1 else 0</li>
-            <li>if res[31:24] &ge; 0 then APSR.GE[3] = 1 else 0</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   - val2[7:0]
-res[15:8]  = val1[15:8]  - val2[15:8]
-res[23:16] = val1[23:16] - val2[23:16]
-res[31:24] = val1[31:24] - val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQSUB8"></a>Function __UQSUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQSUB8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit integer subtractions, saturating 
-          the results to the 8-bit unsigned integer range 0 &le; x &le; 2<sup>8</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands.</li>
-          <li><b>val2</b>: second four 8-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand, in the first byte of the return value.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand, in the second byte of the return value.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand, in the third byte of the return value.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand, in the fourth byte of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 8-bit unsigned integer range 0 &le; x &le; 2<sup>8</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = val1[7:0]   - val2[7:0]
-res[15:8]  = val1[15:8]  - val2[15:8]
-res[23:16] = val1[23:16] - val2[23:16]
-res[31:24] = val1[31:24] - val2[31:24]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHSUB8"></a>Function __UHSUB8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHSUB8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit integer subtractions, halving the 
-          results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands.</li>
-          <li><b>val2</b>: second four 8-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the first byte in the second operand from the first byte 
-                in the first operand, in the first byte of the return value.</li>
-            <li>the halved subtraction of the second byte in the second operand from the second 
-                byte in the first operand, in the second byte of the return value.</li>
-            <li>the halved subtraction of the third byte in the second operand from the third byte 
-                in the first operand, in the third byte of the return value.</li>
-            <li>the halved subtraction of the fourth byte in the second operand from the fourth 
-                byte in the first operand, in the fourth byte of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[7:0]   = (val1[7:0]   - val2[7:0])   &gt;&gt; 1
-res[15:8]  = (val1[15:8]  - val2[15:8])  &gt;&gt; 1
-res[23:16] = (val1[23:16] - val2[23:16]) &gt;&gt; 1
-res[31:24] = (val1[31:24] - val2[31:24]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SADD16"></a>Function __SADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed integer additions.<br>
-          The GE bits in the APSR are set according to the results of the additions.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands.</li>
-          <li><b>val2</b>: second two 16-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfwords in the low halfword of the return value.</li>
-            <li>the addition of the high halfwords in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[15:0]
-res[31:16] = val1[31:16] + val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QADD16"></a>Function __QADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit integer arithmetic additions in parallel, 
-          saturating the results to the 16-bit signed integer range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands.</li>
-          <li><b>val2</b>: second two 16-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the saturated addition of the low halfwords in the low halfword of the return value.</li>
-            <li>the saturated addition of the high halfwords in the high halfword of the return value.</li>
-          </ul>
-          <p>The returned results are saturated to the 16-bit signed integer 
-             range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[15:0]
-res[16:31] = val1[31:16] + val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHADD16"></a>Function __SHADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two signed 16-bit integer additions, halving the 
-          results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands.</li>
-          <li><b>val2</b>: second two 16-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the low halfwords from each operand, in the low halfword 
-                of the return value.</li>
-            <li>the halved addition of the high halfwords from each operand, in the high halfword 
-                of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  + val2[15:0])  &gt;&gt; 1
-res[31:16] = (val1[31:16] + val2[31:16]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UADD16"></a>Function __UADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit unsigned integer additions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands for each addition.</li>
-          <li><b>val2</b>: second two 16-bit summands for each addition.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfwords in each operand, in the low halfword of the 
-                return value.</li>
-            <li>the addition of the high halfwords in each operand, in the high halfword of the 
-                return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0x10000 then APSR.GE[0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0x10000 then APSR.GE[1] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[15:0]
-res[31:16] = val1[31:16] + val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQADD16"></a>Function __UQADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two unsigned 16-bit integer additions, saturating the 
-          results to the 16-bit unsigned integer range 0 &le; x &le; 2<sup>16</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands.</li>
-          <li><b>val2</b>: second two 16-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfword in the first operand and the low halfword in the 
-                second operand, in the low halfword of the return value.</li>
-            <li>the addition of the high halfword in the first operand and the high halfword in the 
-                second operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 16-bit unsigned integer 
-             range 0 &le; x &le; 2<sup>16</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[15:0]
-res[31:16] = val1[31:16] + val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHADD16"></a>Function __UHADD16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHADD16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two unsigned 16-bit integer additions, halving the 
-          results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit summands.</li>
-          <li><b>val2</b>: second two 16-bit summands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the low halfwords in each operand, in the low halfword of 
-                the return value.</li>
-            <li>the halved addition of the high halfwords in each operand, in the high halfword 
-                of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  + val2[15:0])  &gt;&gt; 1
-res[31:16] = (val1[31:16] + val2[31:16]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SSUB16"></a>Function __SSUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SSUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed integer subtractions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands of each subtraction.</li>
-          <li><b>val2</b>: second two 16-bit operands of each subtraction.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the low halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the high halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[15:0]
-res[31:16] = val1[31:16] - val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QSUB16"></a>Function __QSUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QSUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit integer subtractions, saturating the 
-          results to the 16-bit signed integer range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands.</li>
-          <li><b>val2</b>: second two 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the saturated subtraction of the low halfword in the second operand from the low 
-                halfword in the first operand, in the low halfword of the returned result.</li>
-            <li>the saturated subtraction of the high halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the returned result.</li>
-          </ul>
-          <p>The returned results are saturated to the 16-bit signed integer 
-             range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[15:0]
-res[31:16] = val1[31:16] - val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHSUB16"></a>Function __SHSUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHSUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two signed 16-bit integer subtractions, halving the 
-          results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands.</li>
-          <li><b>val2</b>: second two 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the low halfword in the second operand from the low 
-                halfword in the first operand, in the low halfword of the return value.</li>
-            <li>the halved subtraction of the high halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  - val2[15:0])  &gt;&gt; 1
-res[31:16] = (val1[31:16] - val2[31:16]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USUB16"></a>Function __USUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit unsigned integer subtractions.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands.</li>
-          <li><b>val2</b>: second two 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the low halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the high halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[15:0]
-res[31:16] = val1[31:16] - val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQSUB16"></a>Function __UQSUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQSUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two unsigned 16-bit integer subtractions, saturating 
-          the results to the 16-bit unsigned integer range 0 &le; x &le; 2<sup>16</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands for each subtraction.</li>
-          <li><b>val2</b>: second two 16-bit operands for each subtraction.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the low halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the high halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 16-bit unsigned integer range 0 &le; x &le; 2<sup>16</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[15:0]
-res[31:16] = val1[31:16] - val2[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHSUB16"></a>Function __UHSUB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHSUB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two unsigned 16-bit integer subtractions, halving 
-          the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands.</li>
-          <li><b>val2</b>: second two 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the low halfword in the second operand from the low 
-                halfword in the first operand, in the low halfword of the return value.</li>
-            <li>the halved subtraction of the high halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  - val2[15:0])  &gt;&gt; 1
-res[31:16] = (val1[31:16] - val2[31:16]) &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SASX"></a>Function __SASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function inserts an SASX instruction into the instruction stream generated by the 
-          compiler. It enables you to exchange the halfwords of the second operand, add the high 
-          halfwords and subtract the low halfwords.<br>
-          The GE bits in the APRS are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
-              first operand for the addition in the high halfword.</li>
-          <li><b>val2</b>: second operand for the subtraction in the high halfword, and the 
-              second operand for the addition in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the high halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the addition of the high halfword in the first operand and the low halfword in the 
-                second operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0] - val2[31:16]
-res[31:16] = val1[31:16] + val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QASX"></a>Function __QASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the one operand, then add the high
-          halfwords and subtract the low halfwords, saturating the results to the 16-bit signed 
-          integer range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the subtraction in the low halfword, and the 
-                       first operand for the addition in the high halfword.</li>
-          <li><b>val2</b>: second operand for the subtraction in the high halfword, and the
-                       second operand for the addition in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the saturated subtraction of the high halfword in the second operand from the low 
-                halfword in the first operand, in the low halfword of the return value.</li>
-            <li>the saturated addition of the high halfword in the first operand and the low 
-                halfword in the second operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The returned results are saturated to the 16-bit signed integer 
-             range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[31:16]
-res[31:16] = val1[31:16] + val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHASX"></a>Function __SHASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the two halfwords of one operand, perform one 
-          signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands.</li>
-          <li><b>val2</b>: second 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the high halfword in the second operand from the low 
-                halfword in the first operand, in the low halfword of the return value.</li>
-            <li>the halved subtraction of the low halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  - val2[31:16]) &gt;&gt; 1
-res[31:16] = (val1[31:16] - val2[15:0])  &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UASX"></a>Function __UASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the two halfwords of the second operand, add the 
-          high halfwords and subtract the low halfwords.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
-              first operand for the addition in the high halfword.</li>
-          <li><b>val2</b>: second operand for the subtraction in the high halfword and the
-              second operand for the addition in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the high halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the addition of the high halfword in the first operand and the low halfword in the 
-                second operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0x10000 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[31:16]
-res[31:16] = val1[31:16] + val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQASX"></a>Function __UQASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand and perform 
-          one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the 
-          results to the 16-bit unsigned integer range 0 &le; x &le; 2<sup>16</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first two 16-bit operands.</li>
-          <li><b>val2</b>: second two 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the high halfword in the second operand from the low halfword 
-                in the first operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the low halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 16-bit unsigned integer  
-             range 0 &le; x &le; 2<sup>16</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  - val2[31:16]
-res[31:16] = val1[31:16] + val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHASX"></a>Function __UHASX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHASX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand, add the high 
-          halfwords and subtract the low halfwords, halving the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
-           first operand for the addition in the high halfword.</li>
-          <li><b>val2</b>: second operand for the subtraction in the high halfword, and the 
-           second operand for the addition in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved subtraction of the high halfword in the second operand from the low 
-                halfword in the first operand.</li>
-            <li>the halved addition of the high halfword in the first operand and the low halfword 
-                in the second operand.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  - val2[31:16]) &gt;&gt; 1
-res[31:16] = (val1[31:16] + val2[15:0])  &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SSAX"></a>Function __SSAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SSAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the two halfwords of one operand and perform one 
-          16-bit integer subtraction and one 16-bit addition.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the addition in the low halfword, and the first 
-              operand for the subtraction in the high halfword.</li>
-          <li><b>val2</b>: second operand for the addition in the high halfword, and the
-              second operand for the subtraction in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfword in the first operand and the high halfword in the 
-                second operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the low halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[31:16]
-res[31:16] = val1[31:16] - val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__QSAX"></a>Function __QSAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QSAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of one operand, then subtract the 
-          high halfwords and add the low halfwords, saturating the results to the 16-bit signed 
-          integer range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the addition in the low halfword, and the first
-           operand for the subtraction in the high halfword.</li>
-          <li><b>val2</b>: second operand for the addition in the high halfword, and the 
-           second operand for the subtraction in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the saturated addition of the low halfword of the first operand and the high 
-                halfword of the second operand, in the low halfword of the return value.</li>
-            <li>the saturated subtraction of the low halfword of the second operand from the high 
-                halfword of the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The returned results are saturated to the 16-bit signed integer 
-             range -2<sup>15</sup> &le; x &le; 2<sup>15</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[31:16]
-res[31:16] = val1[31:16] - val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SHSAX"></a>Function __SHSAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SHSAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the two halfwords of one operand, perform one 
-          signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands.</li>
-          <li><b>val2</b>: second 16-bit operands.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the low halfword in the first operand and the high halfword 
-                in the second operand, in the low halfword of the return value.</li>
-            <li>the halved subtraction of the low halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  + val2[31:16]) &gt;&gt; 1
-res[31:16] = (val1[31:16] - val2[15:0])  &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USAX"></a>Function __USAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand, subtract the 
-          high halfwords and add the low halfwords.<br>
-          The GE bits in the APSR are set according to the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the addition in the low halfword, and the first
-              operand for the subtraction in the high halfword.</li>
-          <li><b>val2</b>: second operand for the addition in the high halfword, and the
-              second operand for the subtraction in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfword in the first operand and the high halfword in the 
-                second operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the low halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on 
-             the results of the operation.<br>
-             If <i>res</i> is the return value, then:
-          </p>
-          <ul style="margin-top:0px">
-            <li>if res[15:0] &ge; 0x10000 then APSR.GE[1:0] = 11 else 00</li>
-            <li>if res[31:16] &ge; 0 then APSR.GE[3:2] = 11 else 00</li>
-         </ul>      
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[31:16]
-res[31:16] = val1[31:16] - val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UQSAX"></a>Function __UQSAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UQSAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand and perform 
-          one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the 
-          results to the 16-bit unsigned integer range 0 &le; x &le; 2<sup>16</sup> - 1.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operand for the addition in the low halfword, and the
-              first 16-bit operand for the subtraction in the high halfword.</li>
-          <li><b>val2</b>: second 16-bit halfword for the addition in the high halfword,
-              and the second 16-bit halfword for the subtraction in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the addition of the low halfword in the first operand and the high halfword in the 
-                second operand, in the low halfword of the return value.</li>
-            <li>the subtraction of the low halfword in the second operand from the high halfword 
-                in the first operand, in the high halfword of the return value.</li>
-          </ul>
-          <p>The results are saturated to the 16-bit unsigned integer 
-             range 0 &le; x &le; 2<sup>16</sup> - 1.
-          </p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + val2[31:16]
-res[31:16] = val1[31:16] - val2[15:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UHSAX"></a>Function __UHSAX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UHSAX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand, subtract the 
-          high halfwords and add the low halfwords, halving the results.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first operand for the addition in the low halfword, and the first
-              operand for the subtraction in the high halfword.</li>
-          <li><b>val2</b>: second operand for the addition in the high halfword, and the
-              second operand for the subtraction in the low halfword.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the halved addition of the high halfword in the second operand and the low 
-                halfword in the first operand, in the low halfword of the return value.</li>
-            <li>the halved subtraction of the low halfword in the second operand from the high 
-                halfword in the first operand, in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = (val1[15:0]  + val2[31:16]) &gt;&gt; 1
-res[31:16] = (val1[31:16] - val2[15:0])  &gt;&gt; 1</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USAD8"></a>Function __USAD8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USAD8(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit subtractions, and add the 
-          absolute values of the differences together, returning the result as a single unsigned 
-          integer.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands for the subtractions.</li>
-          <li><b>val2</b>: second four 8-bit operands for the subtractions.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the sum of the absolute differences of:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand.</li>
-          </ul>
-          <p>The sum is returned as a single unsigned integer.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-absdiff1  = val1[7:0]   - val2[7:0]
-absdiff2  = val1[15:8]  - val2[15:8]
-absdiff3  = val1[23:16] - val2[23:16]
-absdiff4  = val1[31:24] - val2[31:24]
-res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USADA8"></a>Function __USADA8</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform four unsigned 8-bit subtractions, and add the 
-          absolute values of the differences to a 32-bit accumulate operand.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first four 8-bit operands for the subtractions.</li>
-          <li><b>val2</b>: second four 8-bit operands for the subtractions.</li>
-          <li><b>val3</b>: accumulation value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the sum of the absolute differences of the following 
-            bytes, added to the accumulation value:</p>
-         <ul style="margin-top:0px">
-            <li>the subtraction of the first byte in the second operand from the first byte in the 
-                first operand.</li>
-            <li>the subtraction of the second byte in the second operand from the second byte in 
-                the first operand.</li>
-            <li>the subtraction of the third byte in the second operand from the third byte in the 
-                first operand.</li>
-            <li>the subtraction of the fourth byte in the second operand from the fourth byte in 
-                the first operand.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-absdiff1  = val1[7:0]   - val2[7:0]
-absdiff2  = val1[15:8]  - val2[15:8]
-absdiff3  = val1[23:16] - val2[23:16]
-absdiff4  = val1[31:24] - val2[31:24]
-sum       = absdiff1 + absdiff2 + absdiff3 + absdiff4
-res[31:0] = sum[31:0] + val3[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SSAT16"></a>Function __SSAT16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SSAT16(uint32_t val1, const uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to saturate two signed 16-bit values to a selected signed range.<br>
-          The Q bit is set if either operation saturates.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: two signed 16-bit values to be saturated.</li>
-          <li><b>val2</b>: bit position for saturation, an integral constant expression in the
-              range 1 to 16.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns:</p>
-         <ul style="margin-top:0px">
-            <li>the signed saturation of the low halfword in <i>val1</i>, saturated to the bit position 
-                specified in <i>val2</i> and returned in the low halfword of the return value.</li>
-            <li>the signed saturation of the high halfword in <i>val1</i>, saturated to the bit position 
-                specified in <i>val2</i> and returned in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-Saturate halfwords in val1 to the signed range specified by the bit position in val2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__USAT16"></a>Function __USAT16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __USAT16(uint32_t val1, const uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to saturate two signed 16-bit values to a selected unsigned 
-         range.<br>
-         The Q bit is set if either operation saturates.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: two 16-bit values that are to be saturated.</li>
-          <li><b>val2</b>: bit position for saturation, and must be an integral constant 
-           expression in the range 0 to 15.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the saturation of the two signed 16-bit values, as non-negative values.</p>
-         <ul style="margin-top:0px">
-            <li>the saturation of the low halfword in <i>val1</i>, saturated to the bit position 
-                specified in <i>val2</i> and returned in the low halfword of the return value.</li>
-            <li>the saturation of the high halfword in <i>val1</i>, saturated to the bit position 
-                specified in <i>val2</i> and returned in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-Saturate halfwords in val1 to the unsigned range specified by the bit position in val2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UXTB16"></a>Function __UXTB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UXTB16(uint32_t val);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to extract two 8-bit values from an operand and zero-extend 
-          them to 16 bits each.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the 8-bit values zero-extended to 16-bit values.</p>
-         <ul style="margin-top:0px">
-            <li>zero-extended value of val[7:0] in the low halfword of the return value.</li>
-            <li>zero-extended value of val[23:16] in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = ZeroExtended(val[7:0]  )
-res[31:16] = ZeroExtended(val[23:16])</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__UXTAB16"></a>Function __UXTAB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __UXTAB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to extract two 8-bit values from one operand, zero-extend them 
-          to 16 bits each, and add the results to two 16-bit values from another operand.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: value added to the zero-extended to 16-bit values.</li>
-          <li><b>val2</b>: two 8-bit values to be extracted and zero-extended.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the 8-bit values in <i>val2</i>, zero-extended to 16-bit values 
-            and added to <i>val1</i>.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = ZeroExt(val2[7:0]   to 16 bits) + val1[15:0]
-res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SXTB16"></a>Function __SXTB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SXTB16(uint32_t val);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to extract two 8-bit values from an operand and sign-extend 
-          them to 16 bits each.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the 8-bit values sign-extended to 16-bit values.</p>
-         <ul style="margin-top:0px">
-            <li>sign-extended value of val[7:0] in the low halfword of the return value.</li>
-            <li>sign-extended value of val[23:16] in the high halfword of the return value.</li>
-          </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = SignExtended(val[7:0]
-res[31:16] = SignExtended(val[23:16]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SXTAB16"></a>Function __SXTAB16</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SXTAB16(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to extract two 8-bit values from the second operand (at bit 
-          positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the 
-          first operand.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: values added to the zero-extended to 16-bit values.</li>
-          <li><b>val2</b>: two 8-bit values to be extracted and zero-extended.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the addition of <i>val1</i> and <i>val2</i>, where the 8-bit values in 
-            val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[15:0]  = val1[15:0]  + SignExtended(val2[7:0])
-res[31:16] = val1[31:16] + SignExtended(val2[23:16])</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMUAD"></a>Function __SMUAD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMUAD(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function It enables you to perform two 16-bit signed multiplications, adding the 
-          products together.<br>
-          The Q bit is set if the addition overflows.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the sum of the products of the two 16-bit signed multiplications.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-res[31:0] = p1 + p2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMUADX"></a>Function __SMUADX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMUADX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed multiplications with exchanged
-          halfwords of the second operand, adding the products together.<br>
-          The Q bit is set if the addition overflows.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the sum of the products of the two 16-bit signed multiplications with exchanged
-            halfwords of the second operand.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-res[31:0] = p1 + p2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLAD"></a>Function __SMLAD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two signed 16-bit multiplications, adding both 
-          results to a 32-bit accumulate operand.<br>
-          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the product of each multiplication added to the accumulate 
-            value, as a 32-bit integer.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-res[31:0] = p1 + p2 + val3[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLADX"></a>Function __SMLADX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two signed 16-bit multiplications with exchanged
-          halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br>
-          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the product of each multiplication with exchanged
-            halfwords of the second operand added to the accumulate value, as a 32-bit integer.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-res[31:0] = p1 + p2 + val3[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLALD"></a>Function __SMLALD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two signed 16-bit multiplications, adding both 
-          results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit 
-          addition. This overflow is not detected if it occurs. Instead, the result wraps around 
-          modulo2<sup>64</sup>.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the product of each multiplication added to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-sum = p1 + p2 + val3[63:32][31:0]
-res[63:32] = sum[63:32]
-res[31:0]  = sum[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLALDX"></a>Function __SMLALDX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand, and perform 
-          two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. 
-          Overflow is only possible as a result of the 64-bit addition. This overflow is not detected 
-          if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the product of each multiplication added to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-sum = p1 + p2 + val3[63:32][31:0]
-res[63:32] = sum[63:32]
-res[31:0] = sum[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMUSD"></a>Function __SMUSD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMUSD(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed multiplications, taking the 
-          difference of the products by subtracting the high halfword product from the low 
-          halfword product.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the products of the two 16-bit signed multiplications.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-res[31:0] = p1 - p2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMUSDX"></a>Function __SMUSDX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMUSDX(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed multiplications, subtracting one 
-          of the products from the other. The halfwords of the second operand are exchanged 
-          before performing the arithmetic. This produces top * bottom and bottom * top 
-          multiplication.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the products of the two 16-bit signed multiplications.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-res[31:0] = p1 - p2</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLSD"></a>Function __SMLSD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to perform two 16-bit signed multiplications, take the 
-          difference of the products, subtracting the high halfword product from the low halfword 
-          product, and add the difference to a 32-bit accumulate operand.<br>
-          The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the 
-          subtraction.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val3</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the product of each multiplication, added 
-            to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-res[31:0] = p1 - p2 + val3[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLSDX"></a>Function __SMLSDX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords in the second operand, then perform 
-          two 16-bit signed multiplications. The difference of the products is added to a 32-bit 
-          accumulate operand.<br>
-          The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val3</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the product of each multiplication, added 
-            to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-res[31:0] = p1 - p2 + val3[31:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLSLD"></a>Function __SMLSLD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function It enables you to perform two 16-bit signed multiplications, take the 
-          difference of the products, subtracting the high halfword product from the low halfword 
-          product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur 
-          during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit 
-          addition, and this overflow is not detected. Instead, the result wraps round to  
-          modulo2<sup>64</sup>.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val3</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the product of each multiplication, 
-            added to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[15:0]
-p2 = val1[31:16] * val2[31:16]
-res[63:0] = p1 - p2 + val3[63:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="__SMLSLDX"></a>Function __SMLSLDX</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to exchange the halfwords of the second operand, perform two 
-          16-bit multiplications, adding the difference of the products to a 64-bit accumulate 
-          operand. Overflow cannot occur during the multiplications or the subtraction. Overflow 
-          can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, 
-          the result wraps round to modulo2<sup>64</sup>.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
-          <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
-          <li><b>val3</b>: accumulate value.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the difference of the product of each multiplication, 
-            added to the accumulate value.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-p1 = val1[15:0]  * val2[31:16]
-p2 = val1[31:16] * val2[15:0]
-res[63:0] = p1 - p2 + val3[63:0]</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h3><a name="__SEL"></a>Function __SEL</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __SEL(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function inserts a SEL instruction into the instruction stream generated by the 
-          compiler. It enables you to select bytes from the input parameters, whereby the bytes 
-          that are selected depend upon the results of previous SIMD instruction function. The 
-          results of previous SIMD instruction function are represented by the Greater than or 
-          Equal flags in the Application Program Status Register (APSR).
-          The __SEL function works equally well on both halfword and byte operand function 
-          results. This is because halfword operand operations set two (duplicate) GE bits per 
-          value.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: four selectable 8-bit values.</li>
-          <li><b>val2</b>: four selectable 8-bit values.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function selects bytes from the input parameters and returns them in the 
-            return value, res, according to the following criteria:</p>
-         <ul style="margin-top:0px">
-            <li>if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]</li>
-            <li>if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]</li>
-            <li>if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]</li>
-            <li>if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]</li>
-          </ul>
-      </td>
-    </tr>
-
-  </tbody>
-</table>
-
-<h3><a name="__QADD"></a>Function __QADD</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QADD(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to obtain the saturating add of two integers.<br>
-         The Q bit is set if the operation saturates.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: first summand of the saturating add operation.</li>
-          <li><b>val2</b>: second summand of the saturating add operation.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the saturating addition of val1 and val2.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[31:0] = SAT(val1 + SAT(val2 * 2))</pre>
-      </td>
-    </tr>
-
-  </tbody>
-</table>
-
-<h3><a name="__QSUB"></a>Function __QSUB</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Summary</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t __QSUB(uint32_t val1, uint32_t val2);</pre>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Description</b></td>
-      <td>This function enables you to obtain the saturating subtraction of two integers.<br>
-         The Q bit is set if the operation saturates.
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Parameter</b></td>
-      <td>
-        <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
-          <li><b>val1</b>: minuend of the saturating subtraction operation.</li>
-          <li><b>val2</b>: subtrahend of the saturating subtraction operation.</li>
-        </ul>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Return Value</b></td>
-      <td>
-         <p>The function returns the saturating subtraction of val1 and val2.</p>
-      </td>
-    </tr>
-
-    <tr>
-      <td><b>Operation</b></td>
-      <td>
-        <pre style="margin-left:0px">
-res[31:0] = SAT(val1 - SAT(val2 * 2))</pre>
-      </td>
-    </tr>
-
-  </tbody>
-</table>
-
-<!-- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------     -->
-<!-- --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------     -->
-<p>&nbsp;</p>
-<h2><a name="Examples"></a>Examples</h2>
-<p>Following are some coding examples using the SIMD functions:
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Name</th>
-      <th class="kt">Description</th>
-    </tr>
- 
-    <tr>
-      <td class="kt"><b><a href="#Addition">Addition</a></b></td>
-      <td class="kt">Add two values using SIMD function</td>
-      </tr>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#Addition">Subtraction</a></b></td>
-      <td class="kt">Subtract two values using SIMD function</td>
-      </tr>
-    </tr>
-
-    <tr>
-      <td class="kt"><b><a href="#Multiplication">Multiplication</a></b></td>
-      <td class="kt">Performing a multiplication using SIMD function</td>
-      </tr>
-    </tr>
-
-  </tbody>
-</table>
-
-
-<h3><a name="Addition"></a>Addition</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Example</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t add_halfwords(uint32_t val1, uint32_t val2)
-{
-   uint32_t res;
-   res = __SADD16(val1, val2);
-   return res;
-}</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="Subtraction"></a>Subtraction</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Example</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
-{
-  uint32_t res;
-  res = __SSUB16(val1, val2);
-  return res;
-}</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><a name="Multiplication"></a>Multiplication</h3>
-<table border="0" cellpadding="5" cellspacing="5">
-  <tbody>
-    <tr>
-      <td><b>Example</b></td>
-      <td>
-        <pre style="margin-left:0px">
-uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
-{
-  uint32_t res;
-  res = __SMUAD(val1, val2);
-  return res;
-}</pre>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-
-</body>
-</html>

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-<body>
-<h1>Cortex Microcontroller Software Interface Standard</h1>
-
-<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
-<p align="center">Version: 2.10 - July 2011</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
-	<li>Version 1.00: initial release. </li>
-	<li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
-	<li>Version 1.02: added Cortex-M0. </li>
-	<li>Version 1.10: second review. </li>
-	<li>Version 1.20: third review. </li>
-	<li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
-	<li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
-	<li>Version 1.30: updated Device Support Packages.</li>
-	<li>Version 2.00: added Cortex-M4 support.</li>
-	<li>Version 2.01: internal review.</li>
-	<li>Version 2.02: updated Device Specific Defines</li>
-	<li>Version 2.10: reworked core include files</li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#1">About</a></li>
-  <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
-  <li class="LI2"><a href="#3">CMSIS Files</a></li>
-  <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
-  <li class="LI2"><a href="#5">CMSIS Example</a></li>
-  <li class="LI2"><a href="#6">CMSIS MISRA-C:2004 Compliance Exceptions</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
-  The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
-  that are faced when software components are deployed to physical microcontroller devices based on a
-  Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M 
-  processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
-  with various silicon and software vendors and provides a common approach to interface to peripherals, 
-  real-time operating systems, and middleware components.
-</p>
-
-<p>ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:</p>
-<ul>
-  <li><strong>Core Peripheral Access Layer</strong>: contains name definitions, 
-    address definitions and helper functions to
-    access core registers and peripherals. It defines also a device
-    independent interface for RTOS Kernels that includes debug channel
-    definitions.</li>
-</ul>
-
-<p>These software layers are expanded by Silicon partners with:</p>
-<ul>
-  <li><strong>Device Peripheral Access Layer</strong>: provides definitions
-    for all device peripherals</li>
-  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
-    additional helper functions for peripherals</li>
-</ul>
-
-<p>CMSIS defines for a Cortex-M Microcontroller System:</p>
-<ul>
-  <li style="text-align: left;">A common way to access peripheral registers
-    and a common way to define exception vectors.</li>
-  <li style="text-align: left;">The register names of the <strong>Core
-    Peripherals</strong> and<strong> </strong>the names of the <strong>Core
-    Exception Vectors</strong>.</li>
-  <li>An device independent interface for RTOS Kernels including a debug
-    channel.</li>
-</ul>
-
-<p>
-  By using CMSIS compliant software components, the user can easier re-use template code. 
-  CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-</p>
-
-<h2><a name="2"></a>Coding Rules and Conventions</h2>
-
-<p>
-  The following section describes the coding rules and conventions used in the CMSIS 
-  implementation. It contains also information about data types and version number information.
-</p>
-
-<h3>Essentials</h3>
-<ul>
-  <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, 
-      there are disable and enable sequences for PC-LINT inserted.</li>
-  <li>ANSI standard data types defined in the ANSI C header file
-    <strong>&lt;stdint.h&gt;</strong> are used.</li>
-  <li>#define constants that include expressions must be enclosed by
-    parenthesis.</li>
-  <li>Variables and parameters have a complete data type.</li>
-  <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
-    re-entrant.</li>
-  <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
-    (which means that wait/query loops are done at other software layers).</li>
-  <li>For each exception/interrupt there is definition for:
-  <ul>
-    <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
-	(for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
-    <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
-    <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
-  </ul></li>
-</ul>
-
-<h3>Recommendations</h3>
-
-<p>The CMSIS recommends the following conventions for identifiers.</p>
-<ul>
-  <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
-  <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
-  <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
-  <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
-</ul>
-
-<b>Comments</b>
-
-<ul>
-  <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style 
-  (<em>// comment</em>). It is assumed that the programming tools support today 
-	consistently the C++ comment style.</li>
-  <li><strong>Function Comments</strong> provide for each function the following information:
-  <ul>
-    <li>one-line brief function overview.</li>
-    <li>detailed parameter explanation.</li>
-    <li>detailed information about return values.</li>
-    <li>detailed description of the actual function.</li>
-  </ul>
-  <p><b>Doxygen Example:</b></p>
-  <pre>
-/** 
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- * @param  IRQn  interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */</pre>
-  </li>
-</ul>
-
-<h3>Data Types and IO Type Qualifiers</h3>
-
-<p>
-  The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
-  <strong>&lt;stdint.h&gt;</strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
-  to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of 
-  debug information of peripheral registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
-      <th class="kt">#define</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__I</td>
-      <td class="kt">volatile const</td>
-      <td class="kt">Read access only</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__O</td>
-      <td class="kt">volatile</td>
-      <td class="kt">Write access only</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__IO</td>
-      <td class="kt">volatile</td>
-      <td class="kt">Read and write access</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3>CMSIS Version Number</h3>
-<p>
-  File <strong>core_cm4.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM4_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
-#define __CM4_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM4_CMSIS_VERSION_SUB)</pre>
-
-<p>
-  File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
-#define __CM3_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM3_CMSIS_VERSION_SUB)</pre>
-
-<p>
-  File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM0_CMSIS_VERSION_MAIN  (0x02)      /* [31:16] main version       */
-#define __CM0_CMSIS_VERSION_SUB   (0x10)      /* [15:0]  sub version        */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN &lt;&lt; 16) | __CM0_CMSIS_VERSION_SUB)</pre>
-
-
-<h3>CMSIS Cortex Core</h3>
-<p>
-  File <strong>core_cm4.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M                (0x04)</pre>
-
-<p>
-  File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M                (0x03)</pre>
-
-<p>
-  File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M                (0x00)</pre>
-
-
-<h2><a name="3"></a>CMSIS Files</h2>
-<p>
-  This section describes the Files provided in context with the CMSIS to access the Cortex-M
-  hardware and peripherals.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">File</th>
-      <th class="kt">Provider</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap"><i>device.h</i></td>
-      <td class="kt">Device specific (provided by silicon partner)</td>
-      <td class="kt">Defines the peripherals for the actual device. The file may use 
-        several other include files to define the peripherals of the actual device.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm0.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm3.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm4.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the core peripherals for the Cortex-M4 CPU and core peripherals.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cm4_simd.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the Cortex-M4 Core SIMD functions.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cmFunc.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the Cortex-M Core Register access functions.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">core_cmInstr.h</td>
-      <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
-      <td class="kt">Defines the Cortex-M Core instructions.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
-      <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
-      <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">system<i>_device</i></td>
-      <td class="kt">ARM (adapted by silicon partner)</td>
-      <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes 
-        typically the oscillator (PLL) that is part of the microcontroller device</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3><em>device.h</em></h3>
-
-<p>
-  The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the 
-  <u><strong>central include file</strong></u> that the application programmer is using in 
-  the C source code. This file contains:
-</p>
-<ul>
-  <li>
-	<p><strong>Interrupt Number Definition</strong>: provides interrupt numbers 
-	(IRQn) for all core and device specific exceptions and interrupts.</p>
-	</li>
-	<li>
-	<p><strong>Configuration for core_cm0.h / core_cm3.h / core_cm4.h</strong>: reflects the 
-	actual configuration of the Cortex-M processor that is part of the actual 
-	device. As such the file <strong>core_cm0.h / core_cm3.h / core_cm4.h</strong> is included that 
-	implements access to processor registers and core peripherals. </p>
-	</li>
-	<li>
-	<p><strong>Device Peripheral Access Layer</strong>: provides definitions
-    for all device peripherals. It contains all data structures and the address 
-	mapping for the device specific peripherals. </p>
-	</li>
-  <li><strong>Access Functions for Peripherals (optional)</strong>: provides
-    additional helper functions for peripherals that are useful for programming 
-	of these peripherals. Access Functions may be provided as inline functions 
-	or can be extern references to a device specific library provided by the 
-	silicon vendor.</li>
-</ul>
-
-
-<h4>Interrupt Number Definition</h4>
-
-<p>To access the device specific interrupts the device.h file defines IRQn 
-numbers for the complete device using a enum typedef as shown below:</p>
-<pre>
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
-  NonMaskableInt_IRQn             = -14,      /*!&lt; 2 Non Maskable Interrupt                              */
-  HardFault_IRQn                  = -13,      /*!&lt; 3 Cortex-M3 Hard Fault Interrupt                      */
-  MemoryManagement_IRQn           = -12,      /*!&lt; 4 Cortex-M3 Memory Management Interrupt               */
-  BusFault_IRQn                   = -11,      /*!&lt; 5 Cortex-M3 Bus Fault Interrupt                       */
-  UsageFault_IRQn                 = -10,      /*!&lt; 6 Cortex-M3 Usage Fault Interrupt                     */
-  SVCall_IRQn                     = -5,       /*!&lt; 11 Cortex-M3 SV Call Interrupt                        */
-  DebugMonitor_IRQn               = -4,       /*!&lt; 12 Cortex-M3 Debug Monitor Interrupt                  */
-  PendSV_IRQn                     = -2,       /*!&lt; 14 Cortex-M3 Pend SV Interrupt                        */
-  SysTick_IRQn                    = -1,       /*!&lt; 15 Cortex-M3 System Tick Interrupt                    */
-/******  STM32 specific Interrupt Numbers ****************************************************************/
-  WWDG_STM_IRQn                   = 0,        /*!&lt; Window WatchDog Interrupt                             */
-  PVD_STM_IRQn                    = 1,        /*!&lt; PVD through EXTI Line detection Interrupt             */
-  :
-  :
-  } IRQn_Type;</pre>
-
-
-<h4>Device Specific Defines</h4>
-<p>
-  The following device implementation specific defines are set in the device header file and are 
-  used for the Cortex-M core configuration options. Some configuration options are reflected 
-  in the CMSIS layer using the #define settings described below.
-</p>
-<p>
-  Several features in <strong>core_cm#.h</strong> are configured by the following defines 
-  that must be defined before <strong>#include &lt;core_cm#.h&gt;</strong>
-  preprocessor command.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">#define</th>
-      <th class="kt" nowrap="nowrap">Core</th>
-      <th class="kt" nowrap="nowrap">Value</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__CM0_REV</td>
-      <td class="kt" nowrap="nowrap">M0</td>
-      <td class="kt" nowrap="nowrap">0x0000</td>
-      <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__CM3_REV</td>
-      <td class="kt" nowrap="nowrap">M3</td>
-      <td class="kt" nowrap="nowrap">0x0101 | 0x0200</td>
-      <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__CM4_REV</td>
-      <td class="kt" nowrap="nowrap">M4</td>
-      <td class="kt" nowrap="nowrap">0x0000</td>
-      <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">2 .. 8</td>
-      <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">0 | 1</td>
-      <td class="kt">Defines if a MPU is present or not</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__FPU_PRESENT</td>
-      <td class="kt" nowrap="nowrap">M4</td>
-      <td class="kt" nowrap="nowrap">0 | 1</td>
-      <td class="kt">Defines if a FPU is present or not</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">0 | 1</td>
-      <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function 
-		in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em> 
-		file must contain a vendor specific implementation of this function.</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h4>Device Peripheral Access Layer</h4>
-<p>
-  Each peripheral uses a prefix which consists of <strong>&lt;device abbreviation&gt;_</strong> 
-  and <strong>&lt;peripheral name&gt;_</strong> to identify peripheral registers that access this 
-  specific peripheral. The intention of this is to avoid name collisions caused
-  due to short names. If more than one peripheral of the same type exists, 
-  identifiers have a postfix (digit or letter). For example:
-</p>
-<ul>
-	<li>&lt;device abbreviation&gt;_UART_Type: defines the generic register layout for all UART channels in a device.
-      <pre>
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;                     /*!< Offset: 0x000 (R/ )  Receiver Buffer Register    */
-  __O  uint8_t  THR;                     /*!< Offset: 0x000 ( /W)  Transmit Holding Register   */
-  __IO uint8_t  DLL;                     /*!< Offset: 0x000 (R/W)  Divisor Latch LSB           */
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;                     /*!< Offset: 0x004 (R/W)  Divisor Latch MSB           */
-  __IO uint32_t IER;                     /*!< Offset: 0x004 (R/W)  Interrupt Enable Register   */
-  };
-  union {
-  __I  uint32_t IIR;                     /*!< Offset: 0x008 (R/ )  Interrupt ID Register       */
-  __O  uint8_t  FCR;                     /*!< Offset: 0x008 ( /W)  FIFO Control Register       */
-  };
-  __IO uint8_t  LCR;                     /*!< Offset: 0x00C (R/W)  Line Control Register       */
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;                     /*!< Offset: 0x014 (R/ )  Line Status Register        */
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;                     /*!< Offset: 0x01C (R/W)  Scratch Pad Register        */
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;                     /*!< Offset: 0x020 (R/W)  Autobaud Control Register   */
-  __IO uint8_t  ICR;                     /*!< Offset: 0x024 (R/W)  IrDA Control Register       */
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;                     /*!< Offset: 0x028 (R/W)  Fractional Divider Register */
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;                     /*!< Offset: 0x030 (R/W)  Transmit Enable Register    */
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;                 /*!< Offset: 0x058 (R/ )  FIFO Level Register         */
-} LPC_UART_TypeDef;</pre>
-  </li>
-	<li>&lt;device abbreviation&gt;_UART1: is a pointer to a register structure that refers to a specific UART. 
-      For example UART1-&gt;THR is the transmit holding register of UART1.
-      <pre>
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )</pre>
-  </li>
-</ul>
-
-<h5>Minimal Requiements</h5>
-<p>
-  To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong> 
-  and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
-</p>
-<ul>
-  <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
-      Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
-      the peripheral registers. For example:
-      <pre>
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;</pre>
-  </li>
-
-  <li>
-    <strong>Base Address</strong> for each peripheral (in case of multiple peripherals 
-    that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
-    <pre>
-#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */</pre>
-  </li>
-
-  <li>
-    <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use 
-    the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0, 
-    LPC_UART2). For Example:
-    <pre>
-#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */</pre>
-  </li>
-</ul>
-
-<p>
-  These definitions allow to access the peripheral registers from user code with simple assignments like:
-</p>
-<pre>SysTick-&gt;CTRL = 0;</pre>
-
-<h5>Optional Features</h5>
-<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
-<ul>
-	<li>
-    #define constants that simplify access to the peripheral registers. 
-	  These constant define bit-positions or other specific patterns are that required for the 
-    programming of the peripheral registers. The identifiers used start with 
-    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. 
-    It is recommended to use CAPITAL letters for such #define constants.
-  </li>
-	<li>
-    Functions that perform more complex functions with the peripheral (i.e. status query before 
-    a sending register is accessed). Again these function start with 
-    <strong>&lt;device abbreviation&gt;_</strong> and <strong>&lt;peripheral name&gt;_</strong>. 
-  </li>
-</ul>
-
-<h3>core_cm0.h</h3>
-<p>
-  File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does 
-  the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers 
-  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>This file implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
-<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm0.h in generic 
-   library projects that are device independent. Only core relevant types and defines are used.</p>
-
-<h3>core_cm3.h</h3>
-<p>
-  File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does 
-  the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers 
-  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>This file implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
-<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm3.h in generic 
-   library projects that are device independent. Only core relevant types and defines are used.</p>
-
-<h3>core_cm4.h, core_cm4_simd.h</h3>
-<p>
-  File <b>core_cm4.h</b> describes the data structures for the Cortex-M4 core peripherals and does 
-  the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers 
-  and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
-  File <b>core_cm4_simd.h</b> defines Cortex-M4 SIMD instructions.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M4.</p>
-<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm4.h in generic 
-   library projects that are device independent. Only core relevant types and defines are used.</p>
-
-<h3>core_cmFunc.h and core_cmInstr.h</h3>
-<p>
-  File <b>core_cmFunc.h</b> defines the Cortex-M Core Register access functions (defined as <strong>static inline</strong>).
-</p>
-<p>
-  File <b>core_cmInstr.h</b> defines the Cortex-M Core instructions (defined as <strong>static inline</strong>).
-</p>
-<p>These files are part of the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M.</p>
-
-<h3>startup_<em>device</em></h3>
-<p>
-  A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
-  compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific 
-  interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function 
-  to an dummy handler. Therefore the interrupt handler can be directly used in application software 
-  without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
-</p>
-<p>
-  The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-</p>
-<pre>
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler</pre>
-
-<p>
-  The following exception names are fixed and define the start of the vector table for a Cortex-M3:
-</p>
-<pre>
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler</pre>
-
-<p>
-  In the following examples for device specific interrupts are shown:
-</p>
-<pre>
-; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_IRQHandler         ; Tamper</pre>
-
-<p>
-  Device specific interrupts must have a dummy function that can be overwritten in user code. 
-  Below is an example for this dummy function.
-</p>
-<pre>
-Default_Handler PROC
-                EXPORT WWDG_IRQHandler   [WEAK]
-                EXPORT PVD_IRQHandler    [WEAK]
-                EXPORT TAMPER_IRQHandler [WEAK]
-                :
-                :
-                WWDG_IRQHandler
-                PVD_IRQHandler
-                TAMPER_IRQHandler
-                :
-                :
-                B .
-                ENDP</pre>
-                
-<p>
-  The user application may simply define an interrupt handler function by using the handler name
-  as shown below.
-</p>
-<pre>
-void WWDG_IRQHandler(void)
-{
-  :
-  :
-}</pre>
-
-
-<h3><a name="4"></a>system_<em>device</em>.c</h3>
-<p>
-  A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by 
-  the silicon vendor to match their actual device. As a <strong>minimum requirement</strong> 
-  this file must provide a device specific system configuration function and a global variable 
-  that contains the system frequency. It configures the device and initializes typically the 
-  oscillator (PLL) that is part of the microcontroller device.
-</p>
-<p>
-  The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
-  as a minimum requirement the SystemInit function as shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Function Definition</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
-      <td class="kt">Setup the microcontroller system. Typically this function configures the 
-                     oscillator (PLL) that is part of the microcontroller device. For systems 
-                     with variable clock speed it also updates the variable SystemCoreClock.<br>
-                     SystemInit is called from startup<i>_device</i> file.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
-      <td class="kt">Updates the variable SystemCoreClock and must be called whenever the 
-                     core clock is changed during program execution. SystemCoreClockUpdate()
-                     evaluates the clock register settings and calculates the current core clock.
-</td>
-    </tr>
-  </tbody>
-</table>
-
-<p>
-  Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> 
-  is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Variable Definition</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
-      <td class="kt">Contains the system core clock (which is the system clock	frequency supplied 
-                     to the SysTick timer and the processor core clock). This variable can be 
-                     used by the user application to setup the SysTick timer or configure other 
-                     parameters. It may also be used by debugger to query the frequency of the 
-                     debug timer or configure the trace clock speed.<br>
-                     SystemCoreClock is initialized with a correct predefined value.<br><br>
-		                 The compiler must be configured to avoid the removal of this variable in 
-		                 case that the application program is not using it. It is important for 
-		                 debug systems that the variable is physically present in memory so that 
-		                 it can be examined to configure the debugger.</td>
-    </tr>
-  </tbody>
-</table>
-
-<p class="Note">Note</p>
-<ul>
-  <li><p>The above definitions are the minimum requirements for the file <strong>
-	system_</strong><em><strong>device</strong></em><strong>.c</strong>. This 
-	file may export more functions or variables that provide a more flexible 
-	configuration of the microcontroller system.</p>
-  </li>
-</ul>
-
-
-<h2>Core Peripheral Access Layer</h2>
-
-<h3>Cortex-M Core Register Access</h3>
-<p>
-  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
-  and provide access to Cortex-M core registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Function Definition</th>
-      <th class="kt">Core</th>
-      <th class="kt">Core Register</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">PRIMASK = 0</td>
-      <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE	i</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">PRIMASK = 1</td>
-      <td class="kt">Global Interrupt disable (using the instruction <strong>CPSID i</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return CONTROL</td>
-      <td class="kt">Return Control Register Value (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">CONTROL = value</td>
-      <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_IPSR (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return IPSR</td>
-      <td class="kt">Return IPSR Register Value (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_APSR (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return APSR</td>
-      <td class="kt">Return APSR Register Value (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_xPSR (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return xPSR</td>
-      <td class="kt">Return xPSR Register Value (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return PSP</td>
-      <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
-      <td class="kt" nowrap="nowrap">>M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">PSP = TopOfProcStack</td>
-      <td class="kt">Set Process Stack Pointer value (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return MSP</td>
-      <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">MSP = TopOfMainStack</td>
-      <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">return PRIMASK</td>
-      <td class="kt">Return Priority Mask Register (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">PRIMASK = value</td>
-      <td class="kt">Assign value to Priority Mask Register (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">FAULTMASK = 0</td>
-      <td class="kt">Global Fault exception and Interrupt enable (using the instruction <strong>CPSIE f</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">FAULTMASK = 1</td>
-      <td class="kt">Global Fault exception and Interrupt disable (using the instruction <strong>CPSID f</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_BASEPRI (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">return BASEPRI</td>
-      <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">BASEPRI = value</td>
-      <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">return FAULTMASK</td>
-      <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">FAULTMASK = value</td>
-      <td class="kt">Assign value to Fault Mask Register (using the instruction <strong>MSR</strong>)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __get_FPSCR (void)</td>
-      <td class="kt" nowrap="nowrap">M4</td>
-      <td class="kt" nowrap="nowrap">return FPSCR</td>
-      <td class="kt">Return Floating Point Status / Control Register</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __set_FPSCR (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M4</td>
-      <td class="kt" nowrap="nowrap">FPSCR = value</td>
-      <td class="kt">Assign value to Floating Point Status / Control Register</td>
-    </tr>
-  </tbody>
-</table>
-
-<h3>Cortex-M Instruction Access</h3>
-<p>
-  The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
-  generate specific Cortex-M instructions. The functions are implemented in the file 
-  <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt">Name</th>
-      <th class="kt">Core</th>
-      <th class="kt">Generated CPU Instruction</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __NOP (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">NOP</td>
-      <td class="kt">No Operation</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __WFI (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">WFI</td>
-      <td class="kt">Wait for Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __WFE (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">WFE</td>
-      <td class="kt">Wait for Event</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __SEV (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">SEV</td>
-      <td class="kt">Set Event</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __ISB (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">ISB</td>
-      <td class="kt">Instruction Synchronization Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __DSB (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">DSB</td>
-      <td class="kt">Data Synchronization Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void __DMB (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">DMB</td>
-      <td class="kt">Data Memory Barrier</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">REV</td>
-      <td class="kt">Reverse byte order in integer value.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">REV16</td>
-      <td class="kt">Reverse byte order in unsigned short value. </td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">REVSH</td>
-      <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">RBIT</td>
-      <td class="kt">Reverse bit order of value</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">LDREXB</td>
-      <td class="kt">Load exclusive byte</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">LDREXH</td>
-      <td class="kt">Load exclusive half-word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">LDREXW</td>
-      <td class="kt">Load exclusive word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint8_t __STREXB (uint8_t value, uint8_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">STREXB</td>
-      <td class="kt">Store exclusive byte</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint16_t __STREXH (uint16_t value, uint16_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">STREXH</td>
-      <td class="kt">Store exclusive half-word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t __STREXW (uint32_t value, uint32_t *addr)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">STREXW</td>
-      <td class="kt">Store exclusive word</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void  __CLREX (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">CLREX</td>
-      <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void  __SSAT (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">SSAT</td>
-      <td class="kt">saturate a signed value</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void  __USAT (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">USAT</td>
-      <td class="kt">saturate an unsigned value</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h3>NVIC Access Functions</h3>
-<p>
-  The CMSIS provides access to the NVIC via the register interface structure and several helper
-  functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to 
-  identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative 
-  IRQn values are used for processor core exceptions.
-</p>
-<p>
-  For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides 
-  the following enum names.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
-      <th class="kt">Core</th>
-      <th class="kt">IRQn</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">-14</td>
-      <td class="kt">Cortex-M Non Maskable Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">-13</td>
-      <td class="kt">Cortex-M Hard Fault Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">-12</td>
-      <td class="kt">Cortex-M Memory Management Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">-11</td>
-      <td class="kt">Cortex-M Bus Fault Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">-10</td>
-      <td class="kt">Cortex-M Usage Fault Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">-5</td>
-      <td class="kt">Cortex-M SV Call Interrupt </td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">-4</td>
-      <td class="kt">Cortex-M Debug Monitor Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">-2</td>
-      <td class="kt">Cortex-M Pend SV Interrupt</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">-1</td>
-      <td class="kt">Cortex-M System Tick Interrupt</td>
-    </tr>
-  </tbody>
-</table>
-
-<p>The following functions simplify the setup of the NVIC.
-The functions are defined as <strong>static inline</strong>.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Core</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">Priority Grouping Value</td>
-      <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">(void)</td>
-      <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Enable IRQn</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Disable IRQn</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Return 1 if IRQn is pending else 0</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Set IRQn Pending</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Clear IRQn Pending Status</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Return 1 if IRQn is active else 0</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SetPriority (<br>
-	  &nbsp;&nbsp;IRQn_Type IRQn,<br>
-	  &nbsp;&nbsp;uint32_t priority)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number, Priority</td>
-      <td class="kt">Set Priority for IRQn<br>
-                     (not threadsafe for Cortex-M0)</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number</td>
-      <td class="kt">Get Priority for IRQn</td>
-    </tr>
-    <tr>
-<!--      <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
-      <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (<br>
-	  &nbsp;&nbsp;uint32_t PriorityGroup,<br>
-	  &nbsp;&nbsp;uint32_t PreemptPriority,<br>
-	  &nbsp;&nbsp;uint32_t SubPriority)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap">IRQ Number,<br>
-	  Priority Group,<br>
-	  Preemptive Priority,<br>
-	  Sub Priority</td>
-      <td class="kt">Encode priority for given group, preemptive and sub priority</td>
-    </tr>
-<!--      <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
-      <td class="kt" nowrap="nowrap">void NVIC_DecodePriority (<br>
-	  &nbsp;&nbsp;uint32_t Priority,<br> 
-	  &nbsp;&nbsp;uint32_t PriorityGroup,<br> 
-	  &nbsp;&nbsp;uint32_t* pPreemptPriority,<br> 
-	  &nbsp;&nbsp;uint32_t* pSubPriority)</td>
-      <td class="kt" nowrap="nowrap">M3, M4</td>
-      <td class="kt" nowrap="nowrap"><br>
-	  Priority,<br>
-	  Priority Group,<br>
-	  pointer to Preempt. Priority,<br>
-	  pointer to Sub Priority</td>
-      <td class="kt">Decode given priority to group, preemptive and sub priority</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
-      <td class="kt" nowrap="nowrap">M0, M3, M4</td>
-      <td class="kt" nowrap="nowrap">(void)</td>
-      <td class="kt">Resets the System</td>
-    </tr>
-  </tbody>
-</table>
-<p class="Note">Note</p>
-<ul>
-  <li><p>The processor exceptions have negative enum values. Device specific interrupts 
-         have positive enum values and start with 0. The values are defined in
-         <b><em>device.h</em></b> file.
-      </p>
-  </li>
-  <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
-         used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
-         depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
-      </p>
-  </li>
-</ul>
-
-
-<h3>SysTick Configuration Function</h3>
-
-<p>The following function is used to configure the SysTick timer and start the 
-SysTick interrupt.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig (uint32_t ticks)</span></td>
-      <td class="kt">ticks is SysTick counter reload value</td>
-      <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this 
-        call the SysTick timer creates interrupts with the specified time interval.<br><br>
-        Return: 0 when successful, 1 on failure.<br>
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h3>Cortex-M3 / Cortex-M4 ITM Debug Access</h3>
-
-<p>The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that 
-provides together with the Serial Viewer Output trace capabilities for the 
-microcontroller system. The ITM has 32 communication channels; two ITM 
-communication channels are used by CMSIS to output the following information:</p>
-<ul>
-  <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function 
-      which can be used for printf-style output via the debug interface.</li>
-  <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for 
-      kernel awareness debugging.</li>
-</ul>
-<p class="Note">Note</p>
-<ul>
-  <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels 
-      may use the Privileged level for program execution. ITM 
-      channels have 4 groups with 8 channels each, whereby each group can be 
-      configured for access rights in the Unprivileged level. The ITM channel 0 
-      may be therefore enabled for the user task whereas ITM channel 31 may be 
-      accessible only in Privileged level from the RTOS kernel itself.</p>
-  </li>
-</ul>
-
-<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the 
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
-      <td class="kt">character to output</td>
-      <td class="kt">The function outputs a character via the ITM channel 0. The 
-                     function returns when no debugger is connected that has booked the 
-                     output. It is blocking when a debugger is connected, but the 
-                     previous character send is not transmitted.<br><br>
-                     Return: the input character 'chr'.
-      </td>
-    </tr>
-  </tbody>
-</table>
-
-<p>
-  Example for the usage of the ITM Channel 31 for RTOS Kernels:
-</p>
-<pre>
-  // check if debugger connected and ITM channel enabled for tracing
-  if ((CoreDebug-&gt;DEMCR &amp; CoreDebug_DEMCR_TRCENA) &amp;&amp;
-  (ITM-&gt;TCR &amp; ITM_TCR_ITMENA) &amp;&amp;
-  (ITM-&gt;TER &amp; (1UL &lt;&lt; 31))) {
-    // transmit trace data
-    while (ITM-&gt;PORT31_U32 == 0);
-    ITM-&gt;PORT[31].u8 = task_id;      // id of next task
-    while (ITM-&gt;PORT[31].u32 == 0);
-    ITM-&gt;PORT[31].u32 = task_status; // status information
-  }</pre>
-
-
-<h3>Cortex-M3 additional Debug Access</h3>
-
-<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
-Data can be transmitted via a certain global buffer variable towards the target system.</p>
-
-<p>The buffer variable and the prototypes of the additional functions are shown in the 
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
-  <tbody>
-    <tr>
-      <th class="kt" nowrap="nowrap">Name</th>
-      <th class="kt">Parameter</th>
-      <th class="kt">Description</th>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
-      <td class="kt"> </td>
-      <td class="kt">Buffer to transmit data towards debug system. <br><br>
-                     Value 0x5AA55AA5 indicates that buffer is empty.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
-      <td class="kt">none</td>
-      <td class="kt">The nonblocking functions returns the character stored in 
-                     ITM_RxBuffer. <br><br>
-                     Return: -1 indicates that no character was received.</td>
-    </tr>
-    <tr>
-      <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
-      <td class="kt">none</td>
-      <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
-                     Return: 1 indicates that a character is available, 0 indicates that
-                     no character is available.</td>
-    </tr>
-  </tbody>
-</table>
-
-
-<h2><a name="5"></a>CMSIS Example</h2>
-<p>
-  The following section shows a typical example for using the CMSIS layer in user applications.
-  The example is based on a STM32F10x Device.
-</p>
-<pre>
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks;                       /* timeTicks counter */
-
-void SysTick_Handler(void) {
-  msTicks++;                                     /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
-  uint32_t curTicks = msTicks;
-
-  while ((msTicks - curTicks) &lt; dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
-  ;                                              /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
-  ;                                              /* Turn On  LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
-  ;                                              /* Turn Off LED */
-}
-
-int main (void) {
-  if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
-    ;                                            /* Handle Error */
-    while (1);
-  }
-  
-  LED_Config();                                  /* configure the LEDs */                            
- 
-  while(1) {
-    LED_On (0x100);                              /* Turn  on the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-    LED_Off (0x100);                             /* Turn off the LED   */
-    Delay (100);                                 /* delay  100 Msec    */
-  }
-}</pre>
-
-
-<h2><a name="6"></a>CMSIS MISRA-C:2004 Compliance Exceptions</h2>
-<p>
-  CMSIS violates following MISRA-C2004 Rules:
-</p>
-<ul>
-   <li>Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-       Function definitions in header files are used to allow 'inlining'.</li> 
-
-   <li>Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-       Unions are used for effective representation of core registers.</li>
-   
-   <li>Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-       Function-like macros are used to allow more efficient code.</li> 
-</ul>
-
-<p>&nbsp;&nbsp;</p>
-
-</body></html>

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--->
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-
-<body>
-
-<h1>CMSIS Debug Support</h1>
-<p align="center">This file describes the CMSIS Debug support available with CMSIS (starting V1.30).</p>
-<p align="center">Version: 1.02 - 25. July 2011</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
-	<li>Version 1.00: Initial Release. </li>
-	<li>Version 1.01: Internal Review. </li>
-	<li>Version 1.02: Removed product specific information. </li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#About">About</a></li>
-  <li class="LI2"><a href="#ITM_DbgAcc">Cortex-M3 / Cortex-M4 ITM Debug Access</a></li>
-  <li class="LI2"><a href="#DbgIn_DbgOut">Debug IN / OUT functions</a></li>
-  <li class="LI2"><a href="#ITM_DbgSup">ITM Debug Support in Debugger</a></li>
-</ol>
-
-<p>&nbsp;</p>
-<h2><a name="About"></a>About</h2>
-<p>
-  CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
-  This document describes the available CMSIS Debug functions and the used methods.
-</p>
-
-<p>&nbsp;</p>
-<h2><a name="ITM_DbgAcc"></a>Cortex-M3 / Cortex-M4 ITM Debug Access</h2>
-<p>
-  The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with 
-  the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has 
-  32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM 
-  communication channels are used by CMSIS to output the following information:
-</p>
-<ul>
-	<li>ITM Channel 0: used for printf-style output via the debug interface.</li>
-	<li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
-</ul>
-
-<p>&nbsp;</p>
-<h2><a name="DbgIn_DbgOut"></a>Debug IN / OUT functions</h2>
-<p>CMSIS provides following debug functions:</p>
-<ul>
-	<li>ITM_SendChar (uses ITM channel 0)</li>
-	<li>ITM_ReceiveChar (uses global variable)</li>
-	<li>ITM_CheckChar (uses global variable)</li>
-</ul>
-
-<h3>ITM_SendChar</h3>
-<p>
-  <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from 
-  the microcontroller system to the debug system. <br>
-  Only a 8 bit value is transmitted.
-</p>
-<pre>
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  /* check if debugger connected and ITM channel enabled for tracing */
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &amp;&amp;
-      (ITM-&gt;TCR & ITM_TCR_ITMENA)                  &amp;&amp;
-      (ITM-&gt;TER & (1UL &lt;&lt; 0))  ) 
-  {
-    while (ITM-&gt;PORT[0].u32 == 0);
-    ITM-&gt;PORT[0].u8 = (uint8_t)ch;
-  }  
-  return (ch);
-}</pre>
-
-<h3>ITM_ReceiveChar</h3>
-<p>
-  ITM communication channel is only capable for OUT direction. For IN direction
-  a global variable is used. A simple mechanism detects if a character is received.
-  The project to test need to be build with debug information.
-</p>
-
-<p>
-  The global variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
-  to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to 
-	ensure a proper handshake.
-</p>
-<pre>
-extern volatile int32_t ITM_RxBuffer;                    /* variable to receive characters                             */
-</pre>
-<p>
-  A dedicated bit pattern is used to determine if <strong>ITM_RxBuffer</strong> is empty
-  or contains a valid value.
-</p>
-<pre>
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-</pre>
-<p>
-  <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
-  It returns the received character or '-1' if no character was available.
-</p>
-<pre>
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-</pre>
-
-<h3>ITM_CheckChar</h3>
-<p>
-  <strong>ITM_CheckChar</strong> is used to check if a character is received.
-</p>
-<pre>
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}</pre>
-
-
-<p>&nbsp;</p>
-<h2><a name="ITM_DbgSup"></a>ITM Debug Support in a Debugger</h2>
-<p>
-  The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
-</p>
-<p>Direction: Microcontroller -&gt; Debugger:</p>
-<ul>
-  <li>
-    at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
-    stream it receives from the Microcontroller's CoreSight ITM unit
-  </li>
-  <li>
-    data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated <strong>Console Window</strong>
-  </li>
-</ul>
-
-<p>Direction: Debugger -&gt; Microcontroller:</p>
-<ul>
-  <li>
-    at the beginning of a debug session the debugger shall seek for the presence of the global variable named <strong>ITM_RxBuffer</strong> in the debug
-    information of the application being loaded
-  </li>
-  <li>
-    strings entered into the <strong>Console Window</strong> are written by the debugger as a stream of char values via the variable <strong>ITM_RxBuffer</strong>.
-  </li>
-  <li>
-    the debugger writes the next character into the <strong>ITM_RxBuffer</strong> only once the value has been read and the <strong>ITM_RXBUFFER_EMPTY</strong> value being set.
-    (refer to: ITM_ReceiveChar()).
-</ul>
-
-</body>
-
-</html>

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-<html>
-
-<head>
-<title>CMSIS Version History</title>
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-
-<h1>CMSIS Version History</h1>
-<p align="center">This document describes the changes between the different CMSIS versions.</p>
-<p align="center">Version: 2.10 - July 2011</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#Toolchain">Used Toolchains</a></li>
-  <li class="LI2"><a href="#6">Changes to version V2.00</a></li>
-  <li class="LI2"><a href="#5">Changes to version V1.30</a></li>
-  <li class="LI2"><a href="#4">Changes to version V1.20</a></li>
-  <li class="LI2"><a href="#2">Open Points</a></li>
-  <li class="LI2"><a href="#1">Limitations</a></li>
-</ol>
-
-
-<h2><a name="Toolchain"></a>Used Toolchains</h2>
-<p>
-  Following toolchains have been used for test / verification:</i>.
-</p>
-  <ul>
-    <li>ARM: MDK-ARM Version 4.21</li>
-    <li>GNU: Sourcery G++ Lite Edition for ARM 2010.09-51</li>
-    <li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
-  </ul>
-
-
-<h2><a name="6"></a>Changes to version V2.00</h2>
-
-<h3>Added CMSIS DSP Software Library support for Cortex-M0 based MCUs</h3>
-<p>
-  The <strong>CMSIS DSP Software Library</strong> provides now also libraries and examples for Cortex-M0.
-</p>
-<p>
-  For more information refer to <i>CMSIS DSP Library documentation</i>.
-</p>
-
-<h3>Added big endian support for DSP library</h3>
-<p>
-  The <strong>CMSIS DSP Software Library</strong> provides now also pre-build libraries 
-	and projects for big endian devices.
-</p>
-<p>
-  For more information refer to <i>CMSIS DSP Library documentation</i>.
-</p>
-
-
-<h3>Simplified folder structure for CMSIS include files</h3>
-<p>
-  All CMSIS core include files as well as the DSP-Library header files are located in 
-	a single folder <strong>./CMSIS/Include</strong>.
-</p>
-
-<h3>Changed folder structure for Device Support packages</h3>
-<p>
-  Device Support packages are expected to be in folder <strong>./Device</strong> located at the
-  same level as <strong>./CMSIS</strong>.
-</p>
-<p>The new Device folder contains the following subfolders:</p>
-  <ul>
-     <li><b>Device</b></li>
-       <ul>
-         <li>&lt;<b>Vendor</b>&gt; 
-           <ul>
-             <li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;
-               <ul>
-                  <li><b>Include</b><br>
-                      &lt;device&gt;.h<br>
-                      system_&lt;device&gt;.h<br>
-                  </li>
-                  <li><b>Source</b>
-                    <ul>
-                       <li><b>Templates</b><br>
-                           system_&lt;device&gt;.c<br>
-                          <ul>
-                             <li>&lt;<b>Toolchain</b>&gt;<br>
-                                 startup_&lt;device&gt;.s<br>
-                             </li>
-                             <li>&lt;<b>Toolchain</b>&gt;</li>
-                                <li>...</li>
-                          </ul>
-                       </li>
-                    </ul>
-                  </li>
-               </ul>
-             <li>&lt;<b>Device</b>&gt; | &lt;<b>Device Series</b>&gt;</li>
-             <li>...</li>
-           </ul>
-         </li>
-         <li>&lt;<b>Vendor</b>&gt;</li>
-         <li>...</li>
-       </ul>
-     </li>
-  </ul>
-<p>Template files are application specific files and are required to be copied to the project prior to use!</p>
-
-<h3>Removed CMSIS core source files</h3>
-<p>
-  The CMSIS core source files <strong>core_cm0.c, core_cm3.c, core_cm4.c</strong> 
-  containing helper functions for older ARM compiler versions got removed.
-</p>
-<p>
-  For the <b>ARM Compiler Toolchain </b>version <b>V4.0.677</b> or later is 
-	required!</p>
-
-
-<h2><a name="5"></a>Changes to version V1.30</h2>
-
-<h3>Added CMSIS DSP Software Library</h3>
-<p>
-  The <strong>CMSIS DSP Software Library</strong> is a suite of common signal processing functions targeted 
-  to Cortex-M processor based microcontrollers. Even though the code has been specifically 
-  optimized towards using the extended DSP instruction set of the Cortex-M4 processor, 
-  the library can be compiled for any Cortex-M processor.
-</p>
-<p>
-  For more information see <i>CMSIS DSP Library documentation</i>.
-</p>
-
-<h3>Added CMSIS System View Description</h3>
-<p>
-  The <strong>CMSIS System View Description</strong> answers the challenges of accurate, detailed and 
-  timely device aware peripheral debugging support for Cortex Microcontroller based 
-  devices by the software development tools vendor community.
-</p>
-<p>
-  Silicon vendors shall create and maintain a formalized description of the debug view 
-  for all the peripherals contained in their Cortex Microcontroller based devices.
-  Tool vendors use such descriptions to establish device specific debug support in 
-  their debugging tools.
-</p>
-<p>
-  A standardized System View Description shall provide a common approach to 
-  capturing peripheral debug related information in a machine readable files.
-</p>
-<p>
-  For more information see <i>CMSIS System View Description</i>.
-</p>
-
-<h3>Added Cortex-M4 Core Support</h3>
-<p>
-  Additional folder <strong>CM4</strong>, containing the Cortex-M4 core support files, has been added.
-</p>
-  <ul>
-    <li>CM0</li>
-    <li>CM3</li>
-    <li>CM4
-       <ul>
-         <li>CoreSupport</li>
-         <li>DeviceSupport</li>
-       </ul>
-    </li>
-  </ul>
-
-<h3>New naming for Core Support Files</h3>
-<p>
-  The new Core Support Files are:
-</p>
-<ul>
-  <li>core_cm#.h  (# = 0, 3, 4)</li>
-  <li>core_cmFunc.h  (Cortex-M Core Register access functions)</li>
-  <li>core_cmInstr.h  (Cortex-M Core instructions)</li>
-  <li>core_cm4_simd.h (Cortex-M4 SIMD instructions)</li>
-</ul>
-
-<h2><a name="4"></a>Changes to version V1.20</h2>
-
-<h3>Removed CMSIS Middelware packages</h3>
-<p>
-  CMSIS Middleware is removed and no longer focus of CMSIS.
-</p>
-
-<h3>SystemFrequency renamed to SystemCoreClock</h3>
-<p>
-  The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
-  because the variable holds the clock value at which the core is running.
-</p>
-
-<h3>Changed startup concept</h3>
-<p>
-  The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit 
-  from main) has the weakness that it does not work for controllers which need a already 
-  configuerd clock system to configure the external memory controller.
-</p>
-
-<h5>Changed startup concept</h5>
-<ul>
-  <li>
-    SystemInit() is called from startup file before <strong>premain</strong>.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> configures the clock system and also configures
-    an existing external memory controller.
-  </li>
-  <li>
-    <strong>SystemInit()</strong> must not use global variables.
-  </li>
-  <li>
-    <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
-  </li>
-  <li>
-    Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
-   <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
-   and must be called whenever the core clock is changed.<br>
-   <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
-   the current core clock.
-  </li>
-</ul>
-      
-
-<h3>Advanced Debug Functions</h3>
-<p>
-  ITM communication channel is only capable for OUT direction. To allow also communication for
-  IN direction a simple concept is provided.
-</p>
-<ul>
-  <li>
-    Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
-  </li>
-  <li>
-    Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
-  </li>
-  <li>
-    Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
-  </li>
-</ul>
-
-<p>
-  For detailed explanation see file <strong>CMSIS debug support.htm</strong>. 
-</p>
-
-
-<h3>Core Register Bit Definitions</h3>
-<p>
-  Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
-  defines correspond with the Cortex-M Technical Reference Manual.  
-</p>
-<p>
-  e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */</pre>
-
-<h3>DoxyGen Tags</h3>
-<p>
-  DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
-  using DoxyGen.
-</p>
-
-<h3>Folder Structure</h3>
-<p>
-  The folder structure is changed to differentiate the single support packages.
-</p>
-
-  <ul>
-    <li>CM0</li>
-    <li>CM3
-       <ul>
-         <li>CoreSupport</li>
-         <li>DeviceSupport</li>
-           <ul>
-             <li>Vendor 
-               <ul>
-                 <li>Device
-                   <ul>
-                      <li>Startup
-                        <ul>
-                          <li>Toolchain</li>
-                          <li>Toolchain</li>
-                          <li>...</li>
-                        </ul>
-                      </li>
-                   </ul>
-                 </li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Vendor</li>
-             <li>...</li>
-           </ul>
-         </li>
-         <li>Example <i>(optional)</i>
-           <ul>
-             <li>Toolchain 
-               <ul>
-                 <li>Device</li>
-                 <li>Device</li>
-                 <li>...</li>
-               </ul>
-             </li>
-             <li>Toolchain</li>
-             <li>...</li>
-           </ul>
-         </li>
-       </ul>
-    </li>
-     
-    <li>Documentation</li>
-  </ul>
-
-<h2><a name="2"></a>Open Points</h2>
-<p>
-  Following points need to be clarified and solved:
-</p>
-<ul>
-  <li>
-    <p>
-      Equivalent C and Assembler startup files.
-    </p>
-    <p>
-      Is there a need for having C startup files although assembler startup files are
-      very efficient and do not need to be changed?
-    <p/>
-  </li>
-  <li>
-    <p>
-      Placing of HEAP in external RAM.
-    </p>
-    <p>
-      It must be possible to place HEAP in external RAM if the device supports an 
-      external memory controller.
-    </p>
-  </li>
-  <li>
-    <p>
-      Placing of STACK /HEAP.
-    </p>
-    <p>
-      STACK should always be placed at the end of internal RAM.
-    </p>
-    <p>
-      If HEAP is placed in internal RAM than it should be placed after RW ZI section.
-    </p>
-  </li>
-</ul>
-
-
-<h2><a name="1"></a>Limitations</h2>
-<p>
-  The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
-  No <strong>C startup files</strong> are available. 
- </li>
-</ul>
-

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-<body>
-<h1 class="style1">Cortex Microcontroller Software Interface Standard<br>
-System View Description</h1>
-
-<p class="style1">This file describes the Cortex Microcontroller Software 
-Interface Standard - System View Description (CMSIS - SVD) concept and syntax.</p>
-<p class="style1">Version: 1.02 - 27. July 2011</p>
-
-<p class="style1">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
-	<li>Version 0.91: initial proposal.</li>
-	<li>Version 0.92: revised proposal considering forum feedback (e.g. consider 
-	IP-XACT constructs and naming scheme)</li>
-	<li>Version 1.0: new elements: peripheral version, vendor specific 
-	extension section, interrupt mapping information, global peripheral disable 
-	condition, naming of register arrays, enhanced naming schemes, etc.</li>
-	<li>Version 1.0: SVD versioning and updated schema file</li>
-	<li>Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.</li>
-	<li>Version 1.02: Adding the use case of device header file generation.</li>
-</ul>
-
-<p>&nbsp;</p>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
-  <li class="LI2"><a href="#1">About</a></li>
-  <li class="LI2"><a href="#2">Motivation</a></li>
-  <li class="LI2"><a href="#3">Requirements</a></li>
-  <li class="LI2"><a href="#4">Format</a></li>
-  <li class="LI2"><a href="#5">Example</a></li>
-  <li class="LI2"><a href="#6">Questions &amp; Answers</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
-  The <strong>Cortex Microcontroller Software Interface Standard - System View 
-	Description</strong> (CMSIS - SVD) answers the challenges
-  of accurate, detailed and timely device aware peripheral debugging support for Cortex 
-	Microcontroller based devices by the software development 
-	tools vendor community.
-</p>
-<p>
-  Silicon vendors shall create and maintain a formalized description of the 
-	debug view for all the peripherals contained in their Cortex 
-	Microcontroller based devices. Tool vendors use such descriptions to 
-	establish device specific debug support in their debugging tools with minimal turn around times and 
-	manageable effort. Device support across many development tools&nbsp; is 
-	essential for silicon provider in order to promote new devices and device 
-	variants entering the market. Device aware debug views provide fast and 
-	convenient access to all registers and fields as well as a detailed 
-	description. This enables software developer to 
-	develop and debug code most efficiently and adopt new devices early and 
-	quickly.</p>
-<p>
-  A standardized System View Description shall provide a common approach to 
-	capturing peripheral debug related information in a machine readable files. 
-	The scope of the contained information is agreed to match the level usually 
-	provided by silicon vendors in their device reference manuals, however in a 
-	formalized XML based format. There 
-	are other description languages already available. IP-XACT from the SPIRIT 
-	consortium is a prominent example. IP-XACT covers the register description 
-	sufficiently, however it comprises many other aspects of the devices like 
-	ports, bus-protocols, modeling, tool flows, etc. making a direct use of 
-	IP-XACT too complex. The design of the SVD language is 
-	taking some guidance from IP-XACT thus allowing straight forward conversion 
-	from IP-XACT to CMSIS-SVD where IP-XACT device information is already 
-	available.</p>
-<p>
-  In a second step the CMSIS-SVD description shall be used for automatically 
-	generating CMSIS compliant a device header file. This enables the 
-	information in the header file to be consistent with what the debugger will 
-	display and CMSIS compliant by construction. The header file generation will 
-	require some additional pieces of information and therefore a future version 
-	of the description will need to include some extensions for this purpose.</p>
-<p>
-  Device aware debugging support is only one aspect of device 
-	support essential to software development environments, however it is one of 
-	the most time consuming and error prone ones.</p>
-<h2><a name="2"></a>Motivation</h2>
-<p>
-
-The software developer of microcontroller devices is faced with a growing number 
-of devices with an ever increasing number of peripheral blocks providing a wide 
-range of distinct and complex functionality. The development of drivers for 
-these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the 
-software to run according to the requirements. A debugger providing peripheral awareness improves the 
-ability to access and interpret complex configuration and status information of 
-peripherals. Even though this is only one aspect of device support within microcontroller 
-development environments it is essential for the successful and timely adoption 
-of development tools and the device by the market.</p>
-<p>Today software development environments address device aware 
-debugging in various ways. They either use documents or proprietary file formats 
-as input for providing peripheral views in the debuggers. 
-Extracting peripheral information from written documentation is a very time 
-consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views 
-is going to make device support more affordable, reliable and timely. 
-The challenge for the tool providers is the support of many 
-different and incompatible file formats from a growing number of silicon vendors. 
-For silicon vendors it is time consuming and costly to engage with many tool 
-provider in order to achieve device support in a wide range of development 
-environments.</p>
-<p>Standardizing on a System View Description aims to ease this challenge 
-by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner 
-shall upload and maintain such descriptions in a tool vendor agnostic device 
-database, hosted e.g. by the web server infrastructure 
-<a href="http://cmsis.arm.com">
-cmsis.arm.com</a> . Access control to sensitive information is managed on a per user 
-basis. This allows silicon vendors to upload information for devices that have 
-not been made public.&nbsp; </p>
-<p>Such an approach provides benefits for silicon and tool vendors as well as 
-software developers of Cortex-M based microcontroller devices</p>
-<ul>
-  <li>timely and accurate device support provided by a whole range of tool providers </li>
-	<li>tool providers become more efficient in supporting a multitude of devices 
-	and device variants</li>
-	<li>less interaction required between silicon vendors and the  
-	tool providers</li>
-	<li>silicon provider has control over and maintains the System View 
-	Description during the life cycle of the device</li>
-	<li>high quality device support in terms of completeness and correctness of 
-	device aware debugging</li>
-	<li>improved productivity and user experience for the software developer</li>
-</ul>
-<h2><a name="3"></a>Requirements</h2>
-<p>The debug description shall capture the information about all 
-the peripherals contained in a specific device. This section describes which 
-items of information are deemed relevant for a debugger. Silicon vendors are expected to 
-provide the System View Description for their devices, matching the information 
-contained in device reference manuals. The System View Description shall be suitable for straight forward 
-generation from existing databases like IP-XACT descriptions or SIDSC. The size 
-of device description is a concern and therefore redundancy in the description 
-shall be avoided. The size of SVD files affects the efficiency of 
-distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for 
-the purpose of customization by SW developers.</p>
-<h4>Required content of the description</h4>
-<p>From a programmer's perspective a peripheral can be seen as a set of registers 
-with unique<em> names</em> being mapped to fixed<em> addresses</em> allocated 
-within a defined <em>range</em> of an address space.</p>
-<p>From a debugger's point of view read accesses to a physical register need to be 
-executed in order to display its current value. The debugger executes a write 
-access to a register when a user edits its value. For this purpose the debugger 
-needs to know about the following additional attributes: </p>
-<ul>
-				<li><em>minimal addressable unit </em>= smallest series of bits 
-				identified by a unique address (e.g. byte-addressable memory) </li>
-				<li><em>register size</em> = number of bits forming a register (ARM Cortex-M usually 
-				32 bits)</li>
-				<li><em>access permission</em> = read and write, read only, 
-				write only</li>
-				<li><em>access side effects</em> = accesses by the debugger must 
-				be avoided if it has side effects. Some side effects may be 
-				reversed by the debugger to compensate for the side effect</li>
-</ul>
-<p>In many cases peripheral registers are partitioned into chunks of bits of 
-distinct functionality. In this document these chunks are referred to as <em>
-field</em>. Each 
-register that consists of fields shall&nbsp; be described by a list 
-of <em>uniquely named</em> fields (Note: field names are not required to be 
-unique across registers). In order for a debugger to extract the 
-value of a field from the corresponding register the following attributes are required:</p>
-<ul>
-				<li><em>most significant bit </em>= highest bit position of the 
-				bit-field in the corresponding register</li>
-				<li><em>least significant bit</em> = lowest bit position of the 
-				bit-field within the corresponding register</li>
-				<li><em>access permission</em> = read and write, read only, 
-				write only</li>
-</ul>
-<p>An enumerated value maps a number to a specific descriptive string 
-representing the semantics of the value of a field. The debugger displays the 
-descriptive string rather than the number to simplify the access to the 
-information thus 
-avoiding the necessity of a look-up in the device reference manual. Each item of 
-an enumerated value has the following attributes:</p>
-<ul>
-				<li><em>value</em> = value of the bit-field that corresponds to 
-				the string attribute</li>
-				<li><em>name</em> = short string that describes the semantics of a 
-				field when the corresponding value is set</li>
-				<li><em>description</em> = detailed description of the semantics 
-				of the field when the corresponding value is set</li>
-</ul>
-<p>The hierarchical structure of the description looks like this:</p>
-<p><strong>Device =</strong></p>
-<ul>
-	<li>
-		<p>&nbsp;<strong>Peripherals</strong></p>
-		<ul>
-						<li>
-						<p class="style2"><strong>Peripheral</strong></p>
-						<ul>
-										<li>
-										<p class="style2"><strong>Registers</strong></p>
-										<ul>
-														<li>
-														<p class="style2">
-														<strong>Register</strong></p>
-														<ul>
-																		<li>
-																		<p class="style2">
-																		<strong>Fields</strong></p>
-																		<ul>
-																						<li>
-																						<p class="style2"><strong>Field</strong></p>
-																						<ul>
-																										<li>
-																										<p class="style2"><strong>Enumerated Values</strong></p>
-																										<ul>
-																														<li>
-																														<p class="style2"><strong>Enumerated Value</strong></p>
-																														</li>
-																										</ul>
-																										</li>
-																						</ul>
-																						</li>
-																		</ul>
-																		</li>
-														</ul>
-														</li>
-										</ul>
-										</li>
-						</ul>
-						</li>
-		</ul>
-	</li>
-</ul>
-
-<p>One file can only contain a description for a single device or device family 
-sharing the identical description. Devices consists of a one or more peripherals. 
-Each peripheral contains 
-one or more registers, where each register may consist of one or more fields. 
-The values of a field maybe represented through descriptive strings and detailed 
-descriptions, the enumerated values.</p>
-<p>In many cases there are multiple 
-instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For 
-this reason the description has the concept of deriving a peripheral from a peripheral 
-that has already been described. The attribute <em>derivedFrom </em>specifies 
-such a relationship. 
-Similarly registers or fields can be reused within the device description. The 
-grouping of&nbsp; peripherals providing 
-similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element <em>groupName</em>. 
-All peripherals associated with the same group name are collectively listed under this group 
-in the order they have been specified in the file. 
-Collecting&nbsp; 
-similar or related peripherals into peripheral groups helps structuring the list 
-of peripherals e.g. in a drop down menu (tool dependent). Devices with a large 
-set of peripherals will benefit from this additional level of structure.</p>
-<p>Each of the items (i.e. Device, Peripheral, Register and 
-Field) owns an <em>description </em>element containing verbose information about 
-the respective element. The description field plays 
-an important part in improving the software development productivity. Instead of 
-searching through the reference manual the detailed explanation from the manual 
-could become immediately accessible from within the development environment.</p>
-<p>Details about the exact display format and layout of the peripheral view are 
-considered beyond the scope of the description. It is up to the tool vendor to 
-visualize the contained information appropriately. The  
-silicon vendor provides details about the device's peripherals that is commonly available. </p>
-<p>System View Description files need to be validated for:</p>
-<ol>
-				<li>syntactical correctness using XML-Schema checking utilities</li>
-				<li>consistency&nbsp; of the provided information (e.g. multiple registers mapped to the same address, 
-				all registers located within the specified address ranges of a 
-				peripheral, all fields are within the range of the register 
-				size, etc.) by a utility developed by ARM (SVDConv.exe)</li>
-				<li>&nbsp;semantical correctness of the System View Description 
-				against the silicon specification executed by the silicon vendor</li>
-</ol>
-<p>The SVD description format was extended by numerous elements during the 
-review period targeting version 1.0 and new extensions are expected for future 
-versions of this format. A new section named &quot;vendorExtensions&quot; has been added 
-to the end of the top level to allow silicon vendors and tool partners to 
-innovate and expand the description in order to overcome limitations of the 
-current specification until these can be incorporated into new versions of 
-CMSIS-SVD. <br>
-</p>
-
-<h2>&nbsp;<a name="4"></a><span class="style9">Format</span></h2>
-
-<p>
-  The following section describes the SVD file format in detail. Each subsection 
-	defines a single hierarchy level of the description and lists all mandatory 
-	and optional language elements for that specific level including type 
-	information for each element. Each element is discussed in more detail and a 
-	brief snippet is provided as an example. The sequence of elements shown 
-	below is binding. Optional elements are highlighted in green, blue elements 
-	are mandatory unless they have been already specified globally on a higher 
-	level.</p>
-<p>
-  An XML-schema file is provided alongside this document for syntactical 
-	checking of descriptions being developed.</p>
-<h4>&lt;device schemaVersion=&quot;xs:decimal&quot; <span class="style2"><em>xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd</em></span>&quot;&gt;</h4>
-<p>&nbsp;&nbsp; &lt;<span class="style2">name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
-&nbsp;&nbsp; &lt;version<em>&gt;xs:string&lt;</em>/version&gt;<br>
-&nbsp;&nbsp; &lt;description&gt;<em>xs:string</em>&lt;/description&gt;<br>
-</span>&nbsp;&nbsp; &lt;<span class="style2">addressUnitBits&gt;<em>scaledNonNegativeInteger</em>&lt;/addressUnitBits&gt;<br>
-&nbsp;&nbsp; &lt;width&gt;<em>scaledNonNegativeInteger</em> &lt;/width&gt;</span><br>
-<br>
-&nbsp;&nbsp;<span class="style4"> &lt;</span><span class="style2"><span class="style4">size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<em><br>
-</em>&nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
-&nbsp;&nbsp; &lt;resetValue&gt;<em>scaledNonNegativeIntege</em>r&lt;/resetValue&gt;<br>
-&nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;</span></span></p>
-<p>&nbsp;&nbsp; &lt;peripherals&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/peripherals&gt;<br>
-<span class="style4">&nbsp;&nbsp; &lt;vendorExtensions&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp;&nbsp; &lt;/vendorExtensions&gt;</span></p>
-<h4>&lt;/device&gt;</h4>
-<p>The <strong>device</strong> provides the outermost frame of the description. All other 
-elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals.
-The optional elements size, access, resetValue and resetMask are used as default values throughout the 
-device description unless they get overruled on a lower level of the description 
-(e.g. peripheral or register).</p>
-<h4>Mandatory items:</h4>
-<p><strong>name = </strong>the unique name string is used to identify the device. 
-All devices of a silicon vendor are required to have a unique name. In case an 
-SVD description covers a family or series of devices, the name of the series or 
-family is placed here. The device names of the members of the series or family 
-are listed in &lt;memberDevices&gt;</p>
-<p><strong>description = </strong>string describing main features of a device 
-(e.g. CPU, clock frequency, peripheral overview, etc.)</p>
-<p><strong>version = </strong>the string is defining the version of the 
-description for this device. Silicon vendors will maintain the description 
-throughout the lifecycle of the device and need to ensure that all updated and 
-released copies have a unique version string indicating the order in which. Note: this must not be used for 
-detailing the version of the device.</p>
-<p>&nbsp;</p>
-<p><strong>addressUnitBits = </strong>defines the number of data bits for each address 
-increment. The value for Cortex-M based devices is&nbsp; 8 (byte-addressable).</p>
-<p><strong>width = </strong>defines the number of bits for the maximum single 
-transfer size allowed by the bus interface hence the maximum size of a single 
-register that can be defined for the address space. This information is relevant 
-for debuggers when determining the size of debug transfers. The expected value 
-for Cortex-M based devices is 32.</p>
-<p><strong>peripherals = </strong>next level of description (see next section 
-for details)</p>
-<h4>Optional Items:</h4>
-<p><strong>size = </strong>defines the default bit-width of registers contained 
-in the device. This element can be overruled by re-specifying the size element on a lower level of the 
-description.</p>
-<p><strong>access =</strong> defines the default access permissions for all 
-registers in the device. The allowed tokens are:<br>
-&nbsp; - <em>read-only</em>: read access is permitted. Write operations have an undefined 
-result.<br>
-&nbsp; - <em>write-only</em>: write access is permitted. Read operations have an 
-undefined result. <br>
-&nbsp; -<em>read-write</em>: both read and write accesses are permitted. Writes affect 
-the state of the register and reads return a value related to the register<br>
-&nbsp; -<em>writeOnce</em>: only the first write after reset has an effect on the 
-register. Read operations deliver undefined results<br>
-&nbsp; -<em>read-writeOnce</em>: Read operations deliver a result related to the register 
-content. Only the first write access to this register after a reset will have an 
-effect on the register content.</p>
-<p><strong>resetValue = </strong>defines the default value of all registers 
-after a reset. There are scenarios where SW developers need to know, what the 
-reset value of a register or field is. Even though listed as optional on this 
-level of the description, silicon vendors should ensure that this information is 
-provided for all registers. </p>
-<p><strong>resetMask =</strong> defines those bit positions set to one to be 
-taken from resetValue element. All other elements are undefined. If a register 
-does not have a defined reset value the resetMask needs to be set to 0.</p>
-<p><strong>vendorExtensions </strong>= the content and format of this section of 
-the description is unspecified. Silicon vendors may choose to provide additional 
-information. The assumption is that by default this section is completely 
-ignored by the debugger. It is up to the silicon vendor to specify the content 
-of this section and share the specification with the tool vendors. The new 
-elements shall be considered for a future version of the description format.</p>
-<h4>Example:</h4>
-<pre>&lt;device schemaVersion=&quot;1.0&quot; xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd&quot; &gt;
-  &lt;name&gt;CMSIS_Cortex-M3&lt;/name&gt;
-  &lt;version&gt;0.1&lt;/version&gt;
-  &lt;description&gt;ARM Cortex-M3 based Microcontroller demonstration device&lt;/description&gt;
-  &lt;addressUnitBits&gt;8&lt;/addressUnitBits&gt;
-  &lt;width&gt;32&lt;/width&gt;
-  &lt;size&gt;32&lt;/size&gt;
-  &lt;access&gt;read-write&lt;/access&gt;
-  &lt;resetValue&gt;0&lt;/resetValue&gt;
-  &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt;</pre>
-<pre>  &lt;peripherals&gt;
-    ...
-  &lt;/peripherals&gt;
-&lt;/device&gt;</pre>
-<p>The device description above is at version 0.1 and uniquely identifies the 
-device by the name &quot;CMSIS_Cortex-M3&quot;. The peripherals are memory mapped in a 
-byte-addressable address space with a bus width of 32 bits. The default size of 
-the registers contained in the peripherals is set to 32 bits. Unless redefined 
-for specific peripherals, registers or fields all registers are read-write 
-accessible. A reset value of 0 valid for all 32 bits as specified by the reset 
-mask is set for all registers unless overruled at a lower level of the description.</p>
-<hr>
-<h4>&lt;peripherals&gt;</h4>
-<p>&nbsp;&nbsp; &lt;peripheral&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/peripheral&gt;</p>
-<p>&nbsp;&nbsp;&nbsp;&nbsp; ...</p>
-<p>&nbsp;&nbsp; &lt;peripheral&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/peripheral&gt;</p>
-<h4>&lt;/peripherals&gt;</h4>
-<p>This construct sets the frame for all peripherals and peripheral groups contained in a device. This 
-creates a container element which ease-up processing with languages like Java.</p>
-<hr>
-<h4>&lt;peripheral <span class="style2"><span class="style4">derivedFrom=<em>&quot;xs:Name&quot;</em></span></span>&gt;</h4>
-<p>&nbsp;&nbsp; &lt;name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
-&nbsp;&nbsp; <span class="style4">&lt;version&gt;xs:string&lt;/name&gt;</span><br>
-&nbsp;&nbsp; &lt;description&gt;<em>xs:string </em>&lt;/description&gt;<br>
-&nbsp;&nbsp; <span class="style4">&lt;groupName&gt;<em>xs:string</em>&lt;/groupName&gt;<br>
-&nbsp;&nbsp; &lt;prependToName&gt;<em>xs:string</em>&lt;/prependToName&gt;<br>
-&nbsp;&nbsp; &lt;appendToName&gt;<em>xs:string</em>&lt;/appendToName&gt;</span><br>
-&nbsp;&nbsp; <span class="style4">&lt;disableCondition&gt;<em>xs:string</em>&lt;/disableCondition&gt;</span><br>
-&nbsp;&nbsp; &lt;baseAddress&gt;<em>scaledNonNegativeInteger</em>&lt;/baseAddress&gt;<br>
-&nbsp;&nbsp;<span class="style4"> &lt;</span><span class="style2"><span class="style4">size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<em><br>
-</em>&nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
-&nbsp;&nbsp; &lt;resetValue&gt;<em>scaledNonNegativeIntege</em>r&lt;/resetValue&gt;<br>
-&nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;</span></span></p>
-<p>&nbsp;&nbsp; <span class="style10">&lt;addressBlock&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;offset&gt;</span><em>scaledNonNegativeInteger</em><span class="style10">&lt;/offset&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;size&gt;</span><em>scaledNonNegativeInteger</em><span class="style10">&lt;/size&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;usage<em>&gt;usageType&lt;</em>/usage&gt;<br>
-<em>&nbsp;&nbsp; &lt;/</em>addressBlock&gt;<em><br>
-</em>&nbsp;&nbsp; ...<br>
-</span>&nbsp; <span class="style10"><span class="style4">&lt;addressBlock&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;offset&gt;</span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4">&lt;/offset&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;size&gt;</span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4">&lt;/size&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;usage&gt;<em>usageType</em>&lt;/usage&gt;<br>
-<em>&nbsp;&nbsp; &lt;/</em>addressBlock&gt;<br>
-&nbsp;&nbsp; &lt;interrupt&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;name&gt;<em>xs:string</em>&lt;/name&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;value&gt;<em>scaledNonNegativeInteger</em>&lt;/value&gt;<br>
-&nbsp;&nbsp; &lt;/interrupt&gt;</span><em><br>
-</em></span>&nbsp;&nbsp; &lt;registers&gt;<br>
-&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/registers&gt;</p>
-<h4>&lt;/peripheral&gt;</h4>
-<p>A peripheral encloses the description of one or more registers belonging to 
-this named peripheral. The address range allocated in the address space for this 
-peripheral is defined through one or more address ranges. An address range is 
-specified relative to the base address of the peripheral. This information 
-allows to display a memory map overview for all peripherals. Please note that 
-such a memory map does not contain any information for memories and unoccupied 
-address ranges.</p>
-<h4>Mandatory items:</h4>
-<p><strong>name = </strong>name string used to identify the peripheral. Peripheral 
-names are required to be unique within the scope of a device.</p>
-<p><strong>baseAddress </strong>= lowest address reserved or used by the peripheral</p>
-<p><strong>description = </strong>string providing an overview of the purpose 
-and functionality of the peripheral</p>
-<p><strong>addressBlock = </strong>a peripheral may occupy one or more disparate 
-blocks in the address space. An addressBlock is a complex element consisting of 
-the mandatory elements:<br>
-&nbsp;&nbsp;&nbsp; <strong>offset</strong>: specifying the start address of an address block. It 
-is calculated from the sum of baseAddress and offset<br>
-&nbsp;&nbsp;&nbsp; <strong>size</strong>: specifying the number of addressUnitBits being covered 
-by this address block. The end address of an address block is the sum of start 
-address and the size - 1.<br>
-&nbsp;&nbsp;&nbsp; <strong>usage</strong>: the usage element is of <em>usageType </em>specifying 
-if the addresses within the specified address block is used for<strong> </strong>
-<em>registers</em><strong> </strong>or <em>buffer</em><strong> </strong>or is <em>reserved</em>. 
-<br>
-Note: registers must not be allocated 
-to an address within a reserved or buffer address range.</p>
-<p><strong>registers = </strong>next lower level of description (see next section 
-for details)</p>
-<h4>Optional items:</h4>
-<p><strong>derivedFrom = </strong>this attribute specifies the name of a peripheral 
-that has already been described for this device. The description of that device 
-will be copied. It is mandatory to overwrite the name as well as the 
-addressOffset. All other specified information will overwrite the respective 
-elements in the copy.</p>
-<p><strong>version = </strong>the string specifies the version of this 
-peripheral description.</p>
-<p><strong>disableCondition = </strong>C language compliant logical expression 
-resulting in a true or false result. If &quot;true&quot; the refresh of the display 
-for this peripheral is disabled 
-and related accesses by the debugger are suppressed. Only constants and references to other registers 
-contained in the description are allowed:&nbsp; 
-&lt;peripheral&gt;-&gt;&lt;register&gt;-&gt;&lt;field&gt; (e.g.: (System-&gt;ClockControl-&gt;apbEnable == 0)). 
-Only the following operators are allowed [&amp;&amp;,||, ==, !=, &gt;&gt;, &lt;&lt;, &amp;, |]. Warning! 
-This feature must only be use in case accesses from the debugger to registers of 
-un-clocked peripherals result in severe debugging failures. SVD is intended to 
-be fully static information and not include any run-time computation or 
-functions such capabilities may be added by the tools but is considered beyond 
-the scope of this description language.</p>
-<p><strong>prependToName = </strong>all register names of this peripheral have 
-their names prepended with the string specified</p>
-<p><strong>appendToName = </strong>all register names of this peripheral have 
-their names appended with the string specified</p>
-<p><strong>size = </strong>defines the default bit-width of registers contained 
-in the device. This element can be overruled by re-specifying the size element on a lower level of the 
-description.</p>
-<p><strong>access =</strong> defines the default access permissions for all 
-registers in the peripheral. The value can be reset on a lower level of the 
-description. The allowed tokens are:<br>
-&nbsp; - <em>read-only</em>: read access is permitted. Write operations have an undefined 
-result.<br>
-&nbsp; - <em>write-only</em>: write access is permitted. Read operations have an 
-undefined result. <br>
-&nbsp; -<em>read-write</em>: both read and write accesses are permitted. Writes affect 
-the state of the register and reads return a value related to the register<br>
-&nbsp; -<em>writeOnce</em>: only the first write after reset has an effect on the 
-register. Read operations deliver undefined results<br>
-&nbsp; -<em>read-writeOnce</em>: Read operations deliver a result related to the register 
-content. Only the first write access to this register after a reset will have an 
-effect on the register content.</p>
-<p><strong>resetValue = </strong>defines the default value of all registers 
-after a reset but can be set for individual registers and fields on a lower 
-level of the description.</p>
-<p><strong>resetMask =</strong> defines those bit positions set to one to be 
-taken from resetValue element. All other elements are undefined. This is the 
-default value for the whole peripheral but can be readjusted on lower levels. If 
-a register does not have a defined reset value the resetMask needs to be set to 
-0.</p>
-<p><strong>interrupt = </strong>is a complex type that consists of the <strong>name</strong> of 
-the interrupt and the associated enumeration<strong> value</strong>. A peripheral can also have 
-multiple associated interrupts. This entry is mainly intended for information 
-only purposes in order to display the interrupts and respective interrupt 
-numbers associated with a peripheral.</p>
-<h4>Example:</h4>
-<pre>...&nbsp;
-    &lt;peripheral&gt;
-       &lt;name&gt;Timer0&lt;/name&gt;
-       &lt;version&gt;1.0.32&lt;/version&gt;
-       &lt;description&gt;Timer 0 is a simple 16 bit timer counting down ... &lt;/description&gt;
-       &lt;baseAddress&gt;0x40000000&lt;/baseAddress&gt;
-       &lt;addressBlock&gt;
-         &lt;offset&gt;0x0&lt;/offset&gt;
-         &lt;size&gt;0x400&lt;/size&gt;
-         &lt;usage&gt;registers&lt;/usage&gt;
-       &lt;/addressBlock&gt;
-       &lt;interrupt&gt;&lt;name&gt;TIM0_INT&lt;/name&gt;&lt;value&gt;34&lt;/value&gt;&lt;/interrupt&gt;
-       &lt;registers&gt;
-         ...
-       &lt;/registers&gt;
-    &lt;/peripheral&gt;
-    &lt;peripheral derivedFrom=&quot;Timer0&quot;&gt;
-      &lt;name&gt;Timer1&lt;/name&gt;
-      &lt;baseAddress&gt;0x40000400&lt;/baseAddress&gt;
-    &lt;/peripheral&gt;
-
-...</pre>
-<hr>
-<h4>&lt;registers&gt; ... &lt;/registers&gt;</h4>
-<p>This construct sets the frame for all registers contained in a peripheral. 
-This creates container elements which ease-up processing with languages like Java.</p>
-<hr>
-<h4>&lt;register <span class="style2">derivedFrom=<em>xs:Name</em></span>&gt;</h4>
-<p>&nbsp;&nbsp; <span class="style4">&lt;dim&gt;<em>scaledNonNegativeInteger</em>&lt;/dim&gt;<br>
-&nbsp;&nbsp; &lt;dimIncrement&gt;<em>scaledNonNegativeInteger</em>&lt;/dimIncrement&gt;<br>
-&nbsp;&nbsp; &lt;dimIndex&gt;<em>xs:string</em>&lt;/dimIndex&gt;</span><br>
-&nbsp;&nbsp; &lt;<span class="style2">name&gt;<em>xs:Name</em>&lt;/name&gt;<br>
-&nbsp;&nbsp; <span class="style4">&lt;displayName&gt;<em>xs:string</em>&lt;/displayName&gt;</span><br>
-</span>&nbsp;&nbsp; <span class="style2">&lt;description&gt;<em>xs:string</em>&lt;/description&gt;</span><br>
-&nbsp;<span class="style2">&nbsp; <span class="style4">&lt;alternateGroup&gt;<em>xs:Name</em>&lt;/alternateGroup&gt;</span><br>
-</span>&nbsp; <span class="style2">&nbsp;&lt;addressOffset&gt;<em>scaledNonNegativeInteger</em> 
-&lt;/addressOffset&gt;<br>
-&nbsp;<span class="style5">&nbsp;&nbsp; &lt;size&gt;<em>scaledNonNegativeInteger</em>&lt;/size&gt;<br>
-</span><span class="style4">&nbsp;</span><span class="style5">&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
-&nbsp;&nbsp; </span><span class="style4">&lt;</span><span class="style5">resetValue&gt;<em>scaledNonNegativeInteger</em>&lt;/resetValue&gt;<br>
-&nbsp;&nbsp; &lt;resetMask&gt;<em>scaledNonNegativeInteger</em>&lt;/resetMask&gt;<br>
-</span>
-</span><span class="style4">&nbsp;&nbsp; &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;<br>
-&nbsp;&nbsp; &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;<br>
-&nbsp;&nbsp; &lt;readAction&gt;<em>readActionType</em> &lt;/readAction&gt;</span><span class="style2"><br>
-</span>&nbsp;&nbsp; <span class="style4">&lt;fields&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/fields&gt;</span> </p>
-<h4>&lt;/register&gt;</h4>
-<p>The definition of registers is the central part of the description. A 
-register may use its complete size for a single purpose and therefore not 
-consist of fields. Otherwise the description 
-of fields is mandatory.</p>
-<h4>Mandatory items:<br>
-</h4>
-<p><strong>name = </strong>name string used to identify the register. Register 
-names are required to be unique within the scope of a peripheral.</p>
-<p><strong>description = </strong>string describing the details of the register.</p>
-<p><strong>addressOffset = </strong>value defining the address of the register relative to 
-the baseAddress defined by the peripheral the register belongs to.<br>
-</p>
-<p><span class="style5">The following elements can be omitted</span> if the corresponding value has been set 
-on a higher level of the description and matches the value required for this register:</p>
-<p><strong>size =</strong>value defining the bit-width of the register</p>
-<p><strong>access =</strong> predefined tokens: read-only, write-only, read-write, 
-writeOnce, read-writeOnce strings defining the allowed 
-accesses for this register.</p>
-<p><strong>resetValue =</strong> element defining the value of the register 
-immediately after a reset.</p>
-<p><strong>resetMask= </strong>element specifying those bits of the resetValue that 
-are defined<strong> </strong>(bit positions containing a 0 bit are ignored, bit 
-positions containing a 1 bit are taken from the corresponding bit position of 
-the resetValue). If a register does not have a defined reset value the resetMask 
-needs to be set to 0.</p>
-<h4>Optional items:</h4>
-<p><strong>dim = </strong>if this field is specified the value defines the 
-number of elements in an array of registers.</p>
-<p><strong>dimIncrement =</strong> if dim is specified this element becomes 
-mandatory and specifies the address increment in between 
-two neighboring registers of the register array in the address map.</p>
-<p><strong>dimIndex = </strong>this element specifies the substrings within the 
-register array names that will replace the %s within the register name. By 
-default the index is a decimal value starting with 0 for the first register. 
-Examples:<br>
-&nbsp;&nbsp; &lt;dim&gt;6&lt;/dim&gt; &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; &lt;dimIndex&gt;A,B,C,D,E,Z&lt;/dimIndex&gt; 
-&lt;name&gt;GPIO_%s_CTRL&lt;/name&gt; ...<br>
-&nbsp;&nbsp; =&gt; GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL, 
-GPIO_Z_CTRL<br>
-&nbsp;&nbsp; &lt;dim&gt;4&lt;/dim&gt; &lt;dimIncrement&gt;4&lt;/dimIncrement&gt; &lt;dimIndex&gt;3-6&lt;/dimIndex&gt; 
-&lt;name&gt;IRQ%s&lt;/name&gt; ... <br>
-&nbsp;&nbsp; =&gt; IRQ3, IRQ4, IRQ5, IRQ6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </p>
-<p><strong>displayName = </strong>when used, this is the string being used by a 
-graphical frontend to visualize the register otherwise the name element is used. 
-Note: the display name may contain special characters and white spaces. It also 
-uses &quot;%s&quot; as the place holder for the dimIndex substring.</p>
-<p><strong>alternateGroup =</strong> when used, this element specifies a name of 
-a group that all alternate register with the same name a associated with. At the 
-same time it indicates that there is a register description allocating the same 
-absolute address in the address space. </p>
-<p><strong>modifiedWriteValues = </strong>element to describe the manipulation of 
-data written to a register. If not specified the value written to the field is the 
-value stored in the field. The other options are bitwise operations: <br>
-&nbsp; <em>oneToClear:</em> write data bits of one shall clear (set to zero) the 
-corresponding bit in the register<br>
-&nbsp; <em>oneToSet:</em> write data bits of one shall set (set to one) the 
-corresponding bit in the register<br>
-&nbsp; <em>oneToToggle:</em> write data bits of one shall toggle (invert) the 
-corresponding bit in the register<br>
-&nbsp; <em>zeroToClear:</em> write data bits of zero shall clear (set to zero) 
-the corresponding bit in the register<br>
-&nbsp; <em>zeroToSet:</em> write data bits of zero shall set (set to one) the 
-corresponding bit in the register<br>
-&nbsp; <em>zeroToToggle:</em> write data bits of zero shall toggle (invert) the 
-corresponding bit in the register<br>
-&nbsp; <em>clear:</em> after a write operation all bits in the field are cleared (set to 
-zero)<br>
-&nbsp; <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
-&nbsp; <em>modify:</em> after a write operation all bit in the field may be modified 
-(default)</p>
-<p><strong>writeConstraint: </strong>has a set of options:<br>
-&nbsp; <em>writeAsRead</em> = if true only the last read value can be written<br>
-&nbsp; <em>useEnumeratedValues</em> = if true only those values listed in the 
-enumeratedValues list are considered valid write values<br>
-&nbsp; <em>minimum</em> = specifies the smallest number to be written to the 
-register<br>
-&nbsp; <em>maximum</em> = specifies the largest number to be written to the 
-register</p>
-<p><strong>readAction: </strong>if set it specifies the side effect following 
-read operations. If not set the register is not modified following a read 
-operations. The defined side effects are:<br>
-&nbsp; <em>clear:</em> indicates that the register is cleared (set to zero) 
-following a read operation<br>
-&nbsp; <em>set:</em> indicates that the register is set (set to ones) following a 
-read operation<br>
-&nbsp; <em>modify</em>: indicates that the register is modified in some way 
-after a read operation<br>
-&nbsp; <em>modifyExternal: </em>indicates that one or more dependent resources 
-other than the current register 
-are immediately affected by a read (it is recommended that the register 
-description specifies these dependencies). Debuggers are not expected to read 
-this register location unless explicitly instructed by user.</p>
-<p><strong>fields = </strong>next lower level of description (see next section 
-for details).</p>
-<h4>Optional attribute:</h4>
-<p><strong>derivedFrom = </strong>specifies the name of the register to be 
-replicated. Elements being specified underneath will override the values specified 
-from the register being derived from. Note that it is mandatory to overwrite at 
-least name and addressOffset.</p>
-<h4>Example:</h4>
-<pre>...&nbsp;
-       &lt;register&gt;
-         &lt;name&gt;TimerCtrl0&lt;/name&gt;
-         &lt;description&gt;Timer Control Register&lt;/description&gt;
-         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x00008001&lt;/resetValue&gt;
-         &lt;resetMask&gt;0x0000ffff&lt;/resetMask&gt;
-         &lt;size&gt;32&lt;size&gt;
-         &lt;fields&gt;
-           ...
-         &lt;/fields&gt;
-       &lt;/register&gt;
-       &lt;register derivedFrom=&quot;TimerCtrl0&quot;&gt;
-         &lt;name&gt;TimerCtrl1&lt;/name&gt;
-         &lt;addressOffset&gt;0x4&lt;addressOffset&gt;
-       &lt;/register&gt;
-...</pre>
-<hr>
-<h4>&lt;fields&gt; ... &lt;/fields&gt;</h4>
-<p>This construct sets the frame for all fields contained in a register. 
-This creates container elements which ease-up processing with languages like Java.</p>
-<hr>
-<h4>&nbsp;&lt;field <span class="style2">derivedFrom=<em>&quot;xs:Name</em>&quot;</span>&gt;</h4>
-<p>&nbsp;<span class="style2">&nbsp; &lt;name&gt;<em>xs:Name&lt;/name&gt;<br>
-&nbsp;</em></span>&nbsp; &lt;description&gt;<em>xs:string</em>&lt;/description&gt;<br>
-<span class="style5">&nbsp;</span><span class="style2"><span class="style5"><em>&nbsp; </em>
-</span>&lt;<span class="style5">bitOffset&gt;<em>scaledNonNegativeInteger&lt;/</em>bitOffset&gt;
-</span>&lt;<span class="style5">bitWidth&gt;<em>scaledNonNegativeInteger</em>&lt;/bitWidth&gt;<br>
-&nbsp;&nbsp; </span><span class="style6">or</span><span class="style5"><br>
-&nbsp;&nbsp; &lt;lsb&gt;scaledNonNegativeInteger&lt;/lsb&gt; &lt;msb&gt;scaledNonNegativeInteger&lt;/msb&gt;<br>
-&nbsp;&nbsp; </span><span class="style6">or</span><span class="style5"><br>
-&nbsp;&nbsp; &lt;bitRange&gt;<em>pattern</em>&lt;/bitRange&gt;<br>
-&nbsp;&nbsp; &lt;access&gt;<em>accessType</em>&lt;/access&gt;<br>
-</span></span><span class="style4">&nbsp;&nbsp; &lt;modifiedWriteValues&gt;<em>writeValueType</em>&lt;/modifiedWriteValues&gt;<br>
-&nbsp;&nbsp; &lt;writeConstraint&gt;<em>writeConstraintType</em>&lt;/writeConstraint&gt;<br>
-&nbsp;&nbsp; &lt;readAction&gt;<em>readActionType</em> &lt;/readAction&gt;</span><span class="style2"><br>
-&nbsp;</span>&nbsp; <span class="style4">&lt;enumeratedValues&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/enumeratedValues&gt;</span></p>
-<h4>&lt;/field&gt;</h4>
-<p>A bit-field has a name that is unique for the register it belongs to. The 
-position and size within the register is either described by the combination of 
-the least significant bit's position (lsb) and the most significant bit's 
-position (msb) or the lsb and the size, specifying the bit-width of the 
-field.&nbsp; A field may define an enumeratedValue in order to make the display 
-more intuitive to read. </p>
-<h4>Mandatory items:</h4>
-<p><strong>name = </strong>name string used to identify the field. Field names 
-are required to be unique within the scope of a register.<br>
-</p>
-<p><strong>description = </strong>string describing the details of the register.<br>
-</p>
-<p>There are 3 ways to describe a field to be used mutually exclusive:<br>
-a) specifying bitOffset and bitWidth (IP-XACT like)<br>
-b) specifying lsb and msb of the field.<br>
-c) specifying a bit range in the format &quot;[&lt;msb&gt;:&lt;lsb&gt;]&quot;</p>
-<p><strong>bitOffset = </strong>value defining the position of the least significant bit 
-of the field within the register it belongs to.<br>
-<strong>bitWidth = </strong>value defining the bit-width of the bitfield within the 
-register it belongs to.<br>
-</p>
-<p>
-<strong>lsb =</strong> value defining the bit position of the least significant 
-bit within the register it belongs to.<br>
-<strong>msb =</strong> value defining the bit position of the most significant 
-bit within the register it belongs to. 
-</p>
-<p><strong>bitRange = </strong>a string in the format: [&lt;msb&gt;:&lt;lsb&gt;]<br>
-</p>
-<h4>Optional items:</h4>
-<p><strong>derivedFrom = </strong>the field is cloned 
-from a previously defined field with a unique name.</p>
-<p><strong>access =</strong> predefined strings defining the allowed 
-accesses for this register: <em>read-only, write-only, read-write, writeOnce, 
-read-writeOnce</em><strong>.</strong> Can be omitted if it matches the access permission set for the parent register.</p>
-<p><strong>enumeratedValues = </strong>next lower level of description (see next section 
-for details)</p>
-<p><strong>modifiedWriteValues = </strong>element to describe the manipulation of 
-data written to a field. If not specified the value written to the field is the 
-value stored in the field. The other options are bitwise operations: <br>
-&nbsp; <em>oneToClear:</em> write data bit of one shall clear (set to zero) the 
-corresponding bit in the field<br>
-&nbsp; <em>oneToSet:</em> write data bit of one shall set (set to one) the corresponding 
-bit in the field<br>
-&nbsp; <em>oneToToggle:</em> write data bit of one shall toggle (invert) the 
-corresponding bit in the field<br>
-&nbsp; <em>zeroToClear:</em> write data bit of zero shall clear (set to zero) the 
-corresponding bit in the field<br>
-&nbsp; <em>zeroToSet:</em> write data bit of zero shall set (set to one) the 
-corresponding bit in the field<br>
-&nbsp; <em>zeroToToggle:</em> write data bit of zero shall toggle (invert) the 
-corresponding bit in the field<br>
-&nbsp; <em>clear:</em> after a write operation all bits in the field are cleared (set to 
-zero)<br>
-&nbsp; <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
-&nbsp; <em>modify:</em> after a write operation all bit in the field may be modified 
-(default)</p>
-<p><strong>writeConstraint: </strong>has a set of options:<br>
-&nbsp; <em>writeAsRead</em> = if true only the last read value can be written<br>
-&nbsp; <em>useEnumeratedValues</em> = if true only those values listed in the 
-enumeratedValues list are considered valid write values<br>
-&nbsp; <em>minimum</em> = specifies the smallest number to be written to the field<br>
-&nbsp; <em>maximum</em> = specifies the largest number to be written to the field</p>
-<p><strong>readAction: </strong>if set it specifies the side effect following 
-read operations. If not set the field is not modified following a read 
-operations. The defined side effects are:<br>
-&nbsp; <em>clear:</em> indicates that the field is cleared (set to zero) 
-following a read operation<br>
-&nbsp; <em>set:</em> indicates that the field is set (set to ones) following a 
-read operation<br>
-&nbsp; <em>modify</em>: indicates that the field is modified in some way after a 
-read operation&nbsp;
-<br>
-&nbsp; <em>modifyExternal: </em>indicates that one or more dependent resources 
-other than this field are immediately affected by a read (it is recommended that 
-the field description specifies these dependencies). Debuggers are not expected 
-to read the field unless explicitly instructed by user.</p>
-<h4>Example:</h4>
-<pre>...
-         &lt;field&gt;
-           &lt;name&gt;TimerCtrl0_IntSel&lt;/name&gt;
-           &lt;description&gt;Select interrupt line t<span class="style8">hat is triggered by timer overflow</span>.&lt;/description&gt;
-	   &lt;bitOffset&gt;1&lt;/bitOffset&gt;
-           &lt;bitWidth&gt;3&lt;/bitWidth&gt;
-           &lt;access&gt;read-write&lt;/access&gt;
-	   &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-           &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
-           &lt;writeConstraint&gt;
-              &lt;range&gt;
-                &lt;minimum&gt;0&lt;/minimum&gt;
-                &lt;maximum&gt;5&lt;/maximum&gt;
-              &lt;/range&gt;
-           &lt;/writeConstraint&gt;
-           &lt;readAction&gt;clear&lt;/readAction&gt;
- 
-           &lt;enumeratedValues&gt;
-              ...
-           &lt;/enumeratedValues&gt;
-         &lt;/field&gt;
-...</pre>
-<hr>
-<h4 class="style3">&lt;enumeratedValues <span class="style2">
-<span class="style4">derivedFrom=</span><em>&quot;<span class="style4">xs:Name&quot;</span></em></span>&gt;</h4>
-<p>&nbsp;<span class="style2"><span class="style4">&nbsp; &lt;name&gt;<em>xs:Name</em>&lt;/name</span></span>&gt;<span class="style4"><br>
-&nbsp;&nbsp; &lt;usage&gt;<em>usageType</em>&lt;/usage&gt;</span><br>
-&nbsp;&nbsp; &lt;enumeratedValue&gt;<br>
-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/enumeratedValue&gt;</p>
-<p>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ...&nbsp;</p>
-<p>&nbsp;&nbsp;&nbsp;&lt;enumeratedValue&gt;<br>
-&nbsp;&nbsp; &nbsp;&nbsp; ...<br>
-&nbsp;&nbsp; &lt;/enumeratedValue&gt;</p>
-<h4>&lt;/enumeratedValues&gt;</h4>
-<p>An enumerated value provides one or more enumeration items (enumeratedValue), defining a map 
-between all possible values of the bit-field it belongs to and the corresponding 
-human readable semantics of that value.</p>
-<p>Mandatory items:<br>
-<strong>enumeratedValue = </strong>next lower level of description (see next section 
-for details)</p>
-<p>Optional items:<br>
-<strong>derivedFrom = </strong>the enumeratedValues can be copied or derived 
-from a previously defined enumeratedValue that has been given a unique name.<br>
-<strong>name =</strong> name string to identify an enumeratedValue. Named 
-enumeratedValues need to be unique in the scope of a device in order to be reusable 
-throughout the description of a device.<br>
-<strong>usage = </strong>possible values are <strong>read, write </strong>or
-<strong>read-write.</strong> This allows to specify two different enumerated values 
-depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.</p>
-<h4>Example:</h4>
-<pre>...
-           &lt;enumeratedValues&gt;
-              &lt;name&gt;TimerIntSelect&lt;/name&gt;
-              &lt;usage&gt;read-write&lt;/usage&gt;
-              &lt;enumeratedValue&gt;
-                &lt;name&gt;disabled&lt;/name&gt;
-                &lt;description&gt;disabled bit&lt;/description&gt;
-                &lt;value&gt;0&lt;/value&gt;
-              &lt;/enumeratedValue&gt;
-              ...
-              &lt;enumeratedValue&gt;
-                &lt;name&gt;reserved&lt;/name&gt;
-	        &lt;description&gt;reserved values. Do not use&lt;/description&gt;
-                &lt;isDefault&gt;true&lt;/isDefault&gt;
-              &lt;/enumeratedValue&gt;
-           &lt;/enumeratedValues&gt;
-...</pre>
-<hr>
-<h4>&lt;enumeratedValue&gt;</h4>
-<p>&nbsp;&nbsp; &lt;name<em>&gt;xs:name</em>&lt;/name&gt;<br>
-&nbsp;&nbsp; <span class="style10"><span class="style4">&lt;description&gt;xs:<em>string</em>&lt;/description&gt;</span><br>
-</span><em>&nbsp;&nbsp; &lt;</em>value<span class="style2">&gt;<em>scaledNonNegativeInteger</em>&lt;/value&gt;<em><br>
-&nbsp;&nbsp;
-</em>or<em><br>
-&nbsp;&nbsp; &lt;</em>isDefault&gt;<em>xs:boolean</em>&lt;/isDefault&gt;<em><br>
-</em></span></p>
-<h4>&lt;/enumeratedValue&gt;</h4>
-<p>An enumeratedValue defines a map between a value and the string reading the 
-corresponding human readable semantics for that value in a brief and a detailed 
-version</p>
-<h4>Mandatory items:</h4>
-<p><strong>name=</strong> brief string verbally describing the semantics of the value 
-defined for this enumeratedValue. E.g. used for display in visualization of a bit-field 
-instead of the value.</p>
-<p>
-<strong>value = </strong>defines the constant of the bit-field that the name 
-corresponds to<strong>.</strong></p>
-<p><strong>isDefault = </strong>defines the name and description for all other 
-values that are not explicitly listed</p>
-<h4>Optional item:</h4>
-<p><strong>description = </strong>extended string verbally describing the semantics 
-of the value defined for this enumeratedValue in full detail.</p>
-<h4>Example:</h4>
-<pre>...
-         &lt;enumeratedValue&gt;
-            &lt;name&gt;disabled&lt;/name&gt;
-            &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
-            &lt;value&gt;0&lt;/value&gt;
-         &lt;/enumeratedValue&gt;
-         ...
-         &lt;enumeratedValue&gt;
-            &lt;name&gt;enabled&lt;/name&gt;
-            &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
-            &lt;isDefault&gt;true&lt;/isDefault&gt;
-         &lt;/enumeratedValue&gt;
-
-...</pre>
-<hr>
-<h4>Names</h4>
-<p>Names shall comply with ANSI C variable naming restrictions.</p>
-<h4>Constants</h4>
-<p>Number constants shall be entered in hexadecimal, decimal or binary format.</p>
-<ul>
-				<li>hexadecimal is indicated by a leading &quot;0x&quot;</li>
-				<li>binary format is indicated by a leading&nbsp; &quot;#&quot;</li>
-				<li>all other formats are interpreted as decimal numbers</li>
-				<li>the value tag in enumeratedValue accepts do not care bits 
-				represented by &quot;x&quot;</li>
-</ul>
-<h4><b>Comments</b> </h4>
-<p>Comments have the standard XML format <strong>&quot;&lt;!--&quot;</strong> starts a comment
-	<strong><span class="style2">&quot;--&gt;&quot;</span></strong> terminates a comment</p>
-<h2>Example</h2>
-<pre>
-&lt;?xml version=&quot;1.0&quot; encoding=&quot;utf-8&quot;?&gt;
-&nbsp;
-&lt;device schemaVersion=&quot;1.0&quot; xmlns:xs=&quot;http://www.w3.org/2001/XMLSchema-instance&quot; xs:noNamespaceSchemaLocation=&quot;CMSIS-SVD_Schema_1_0.xsd&quot; &gt;
-  &lt;name&gt;Cortex_M3_Sample&lt;/name&gt;
-  &lt;version&gt;0.1&lt;/version&gt;
-  &lt;description&gt;ARM Cortex-M3 based Microcontroller dummy device&lt;/description&gt;
-  &lt;!-- Bus Interface Properties --&gt;
-  &lt;!-- Cortex-M3 is byte addressable --&gt;
-  &lt;addressUnitBits&gt;8&lt;/addressUnitBits&gt;
-  &lt;!-- the maximum data bit width accessible within a single transfer is 32bits --&gt;
-  &lt;width&gt;32&lt;/width&gt;
-
-  &lt;!-- Register Default Properties --&gt;
-  &lt;!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers --&gt;
-  &lt;size&gt;32&lt;/size&gt;
-  &lt;!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers --&gt;
-  &lt;access&gt;read-write&lt;/access&gt;
-  &lt;!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description --&gt;
-  &lt;resetValue&gt;0&lt;/resetValue&gt;
-  &lt;!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value --&gt;
-  &lt;resetMask&gt;0&lt;/resetMask&gt;
-
-  &lt;peripherals&gt;
-    &lt;peripheral&gt;
-      &lt;name&gt;Timer0&lt;/name&gt;
-      &lt;description&gt;A simple 16 bit timer counting down ... &lt;/description&gt;
-      &lt;groupName&gt;Timer&lt;/groupName&gt;
-      &lt;baseAddress&gt;0x40000000&lt;/baseAddress&gt;
-      &lt;!-- the first addressBlock is occupied by registers. The second block is reserved -&gt; no access permission --&gt;
-      &lt;addressBlock&gt;
-        &lt;offset&gt;0&lt;/offset&gt;
-        &lt;size&gt;0x8&lt;/size&gt;
-        &lt;usage&gt;registers&lt;/usage&gt;
-      &lt;/addressBlock&gt;
-      &lt;addressBlock&gt;
-        &lt;offset&gt;0x8&lt;/offset&gt;
-        &lt;size&gt;0x3f8&lt;/size&gt;
-        &lt;usage&gt;reserved&lt;/usage&gt;
-      &lt;/addressBlock&gt;
-      &lt;interrupt&gt;
-        &lt;name&gt;TIM0_IRQn&lt;/name&gt;
-        &lt;value&gt;34&lt;/value&gt;
-      &lt;/interrupt&gt;
-      &lt;registers&gt;
-        &lt;register&gt; 
-          &lt;name&gt;TimerCtrl0&lt;/name&gt;
-          &lt;!-- the display name is an unrestricted string. --&gt;
-          &lt;displayName&gt;Timer Ctrl 0&lt;/displayName&gt;
-          &lt;description&gt;Timer Control Register&lt;/description&gt;
-          &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
-          &lt;!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false --&gt;
-          &lt;fields&gt;
-            &lt;field&gt;
-              &lt;name&gt;TimerCtrl0_En&lt;/name&gt;
-              &lt;description&gt;Enable Bit activates the timer.&lt;/description&gt;
-              &lt;!-- Spirit like bit range description: [0:0] --&gt;
-              &lt;bitOffset&gt;0&lt;/bitOffset&gt;
-              &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-              &lt;!-- Writing 1 enables, writing 0 has no effect --&gt;
-	      &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
-              &lt;!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed --&gt;
-              &lt;writeConstraint&gt;
-                &lt;useEnumeratedValues&gt;true&lt;/useEnumeratedValues&gt;
-              &lt;/writeConstraint&gt;
-              &lt;!-- there is no side effect on reads, therefore &lt;readAction&gt; is not set --&gt;
-              &lt;!-- oneBitEnable named enumeration that can be reused in other parts of the description --&gt;
-              &lt;enumeratedValues&gt;
-                &lt;name&gt;oneBitEnable&lt;/name&gt;
-                &lt;!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing --&gt;
-                &lt;usage&gt;read-write&lt;/usage&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;enabled&lt;/name&gt;
-                  &lt;description&gt;Timer is enabled and active&lt;/description&gt;
-                  &lt;value&gt;0x0&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;disabled&lt;/name&gt;
-                  &lt;description&gt;Timer is disabled and inactive&lt;/description&gt;
-                  &lt;value&gt;0x1&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-              &lt;/enumeratedValues&gt;
-            &lt;/field&gt;
-            &lt;field&gt;
-              &lt;name&gt;TimerCtrl0_Dis&lt;/name&gt;
-              &lt;description&gt;Disable Bit deactivates the timer.&lt;/description&gt;
-              &lt;!-- Spirit like bit range description: [1:1] --&gt;
-              &lt;bitOffset&gt;1&lt;/bitOffset&gt;
-              &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-              &lt;!-- Writing 1 sets, writing 0 has no effect --&gt;
-	      &lt;modifiedWriteValues&gt;oneToSet&lt;/modifiedWriteValues&gt;
-              &lt;!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed --&gt;
-              &lt;writeConstraint&gt;
-                &lt;useEnumeratedValues&gt;true&lt;/useEnumeratedValues&gt;
-              &lt;/writeConstraint&gt;
-              &lt;!-- there is no side effect on reads, therefore &lt;readAction&gt; is not set --&gt;
-              &lt;!-- oneBitEnable named enumeration that can be reused in other parts of the description --&gt;
-              &lt;enumeratedValues derivedFrom=&quot;oneBitEnable&quot;&gt;&lt;/enumeratedValues&gt;
-            &lt;/field&gt;
-            &lt;field&gt;
-              &lt;name&gt;TimerCtrl0_Int&lt;/name&gt;
-              &lt;description&gt;Select interrupt line that is triggered by timer overflow.&lt;/description&gt;
-              &lt;!-- the position of the bit field is described in the bitRange style. --&gt;
-              &lt;bitRange&gt;[4:2]&lt;/bitRange&gt;
-              &lt;enumeratedValues&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;disabled&lt;/name&gt;
-                  &lt;description&gt;Timer does not generate interrupts&lt;/description&gt;
-                  &lt;value&gt;0&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;int 0&lt;/name&gt;
-                  &lt;description&gt;Timer does generate interrupts on interrupt line 0&lt;/description&gt;
-                  &lt;value&gt;1&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;int 1&lt;/name&gt;
-                  &lt;description&gt;Timer does generate interrupts on interrupt line 1&lt;/description&gt;
-                  &lt;value&gt;2&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;int 2&lt;/name&gt;
-                  &lt;description&gt;Timer does generate interrupts on interrupt line 2&lt;/description&gt;
-                  &lt;value&gt;3&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;int 3&lt;/name&gt;
-                  &lt;description&gt;Timer does generate interrupts on interrupt line 3&lt;/description&gt;
-                  &lt;value&gt;4&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;int 4&lt;/name&gt;
-                  &lt;description&gt;Timer does generate interrupts on interrupt line 4&lt;/description&gt;
-                  &lt;value&gt;5&lt;/value&gt;
-                &lt;/enumeratedValue&gt;
-                &lt;!-- this is the default element. All the valid value not listed above (6,7) have the following name and description --&gt;
-                &lt;enumeratedValue&gt;
-                  &lt;name&gt;reserved&lt;/name&gt;
-                  &lt;description&gt;Timer is configured incorrectly and the functionality is considered unpredictable&lt;/description&gt;
-                  &lt;isDefault&gt;true&lt;/isDefault&gt;
-                &lt;/enumeratedValue&gt;
-              &lt;/enumeratedValues&gt;
-            &lt;/field&gt;
-          &lt;/fields&gt;
-        &lt;/register&gt;
-        &lt;register&gt;
-          &lt;name&gt;TimerCounter0&lt;/name&gt;
-          &lt;description&gt;Timer0 16 Bit Counter Register&lt;/description&gt;
-          &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
-          &lt;size&gt;16&lt;/size&gt;
-        &lt;/register&gt;
-        &lt;!-- a copy of the counter register TimerCounter0 with the name=&quot;TimerCounter1&quot; and the addressOffset=&quot;0x8&quot; --&gt;
-        &lt;register derivedFrom=&quot;TimerCounter0&quot;&gt;
-          &lt;name&gt;TimerCounter1&lt;/name&gt;
-          &lt;addressOffset&gt;0x6&lt;/addressOffset&gt;
-        &lt;/register&gt;
-        &lt;!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete --&gt;
-      &lt;/registers&gt;
-    &lt;/peripheral&gt;
-    &lt;!-- a copy of Timer0 with the name=&quot;Timer1 and the baseAddress=&quot;0x40000400&quot; --&gt;
-    &lt;peripheral derivedFrom=&quot;Timer0&quot;&gt;
-      &lt;name&gt;Timer1&lt;/name&gt;
-      &lt;baseAddress&gt;0x40000400&lt;/baseAddress&gt;
-      &lt;interrupt&gt;
-        &lt;name&gt;TIM1_IRQn&lt;/name&gt;
-        &lt;value&gt;35&lt;/value&gt;
-      &lt;/interrupt&gt;
-    &lt;/peripheral&gt;
-  &lt;/peripherals&gt;
-&lt;/device&gt;</pre>
-
-<h2><a name="6"></a>Questions &amp; Answers</h2>
-<h3>Is there any relation between the System View Description and the CMSIS 
-standard?</h3>
-<p>Initiallly there was no immediate link but both initiatives had a common goal: 
-Create a sound software development eco-system for Cortex-M based 
-Microcontroller, giving the customers the free choice of devices and software 
-development environments and all resources required for a successful product 
-development in a single location.&nbsp;Meanwhile we have started to generate 
-CMSIS compliant device header files from the same CMSIS-SVD description. We will 
-introduce a small number of additional description tags in the next version of 
-the specification. The benefit is the synchronization between symbols used in 
-the application and the symbols displayed by the debugger.&nbsp; </p>
-<h3>Why does the format not provide constructs like macros and 
-conditional statements?</h3>
-<p>It is assumed that the description is generated from other sources and 
-therefore such concepts would only complicate the language unnecessarily. It is 
-recommended to use a standard C pre-processor to generate the debug description 
-format from a redundancy optimized description.</p>
-<h3>Do we need to consider endianess in the description?</h3>
-<p>This should be specified on a device configuration level and is not specific 
-to the visualization of peripheral details in a System View. Endianess becomes 
-relevant when using bit fields in the CMSIS compliant device header file.</p>
-<h3>Is the System View Description limited to Cortex-M based devices ?</h3>
-
-
-<p>There may have been assumptions made about the structure of the device due to 
-it being developed around a Cortex-M processor. E.g. that all peripherals are 
-assumed to be memory mapped and to reside in a single address space. It is quite 
-likely that the description format may also serve other architectures 
-sufficiently. There is no intent to limit the format to Cortex-M 
-processor based devices. </p>
-
-
-</body></html>

bsp/stm32f0x/Libraries/CMSIS/Include/arm_common_tables.h

@@ -1,35 +0,0 @@
-/* ---------------------------------------------------------------------- 
-* Copyright (C) 2010 ARM Limited. All rights reserved. 
-* 
-* $Date:        11. November 2010  
-* $Revision: 	V1.0.2  
-* 
-* Project: 	    CMSIS DSP Library 
-* Title:	    arm_common_tables.h 
-* 
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
-* 
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.0.2 2010/11/11 
-*    Documentation updated.  
-* 
-* Version 1.0.1 2010/10/05  
-*    Production release and review comments incorporated. 
-* 
-* Version 1.0.0 2010/09/20  
-*    Production release and review comments incorporated. 
-* -------------------------------------------------------------------- */ 
- 
-#ifndef _ARM_COMMON_TABLES_H 
-#define _ARM_COMMON_TABLES_H 
- 
-#include "arm_math.h" 
- 
-extern uint16_t armBitRevTable[256]; 
-extern q15_t armRecipTableQ15[64]; 
-extern q31_t armRecipTableQ31[64]; 
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
- 
-#endif /*  ARM_COMMON_TABLES_H */ 

bsp/stm32f0x/Libraries/CMSIS/Include/arm_math.h

@@ -1,7051 +0,0 @@
-/* ----------------------------------------------------------------------   
- * Copyright (C) 2010 ARM Limited. All rights reserved.   
- *   
- * $Date:        15. July 2011  
- * $Revision: 	V1.0.10  
- *   
- * Project: 	    CMSIS DSP Library   
- * Title:	     arm_math.h
- *   
- * Description:	 Public header file for CMSIS DSP Library
- *   
- * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
- *  
- * Version 1.0.10 2011/7/15 
- *    Big Endian support added and Merged M0 and M3/M4 Source code.  
- *   
- * Version 1.0.3 2010/11/29  
- *    Re-organized the CMSIS folders and updated documentation.   
- *    
- * Version 1.0.2 2010/11/11   
- *    Documentation updated.    
- *   
- * Version 1.0.1 2010/10/05    
- *    Production release and review comments incorporated.   
- *   
- * Version 1.0.0 2010/09/20    
- *    Production release and review comments incorporated.   
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * <b>Introduction</b>
-   *
-   * This user manual describes the CMSIS DSP software library, 
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of modules each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values. 
-   *
-   * <b>Processor Support</b>
-   *
-   * The library is completely written in C and is fully CMSIS compliant. 
-   * High performance is achieved through maximum use of Cortex-M4 intrinsics. 
-   *
-   * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
-   * with the DSP intrinsics being emulated through software. 
-   *
-   *
-   * <b>Toolchain Support</b>
-   *
-   * The library has been developed and tested with MDK-ARM version 4.21. 
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * <b>Using the Library</b>
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
-   * ARM_MATH_CM0 depending on the target processor in the application.
-   *
-   * <b>Examples</b>
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * <b>Building the Library</b>
-   *
-   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.
-   * - arm_cortexM0b_math.uvproj
-   * - arm_cortexM0l_math.uvproj
-   * - arm_cortexM3b_math.uvproj
-   * - arm_cortexM3l_math.uvproj  
-   * - arm_cortexM4b_math.uvproj
-   * - arm_cortexM4l_math.uvproj
-   * - arm_cortexM4bf_math.uvproj
-   * - arm_cortexM4lf_math.uvproj
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * <b>ARM_MATH_CMx:</b>
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on cortex-M0 target.
-   *
-   * <b>ARM_MATH_BIG_ENDIAN:</b>
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * <b>ARM_MATH_MATRIX_CHECK:</b>
-   * Define macro for checking on the input and output sizes of matrices
-   *
-   * <b>ARM_MATH_ROUNDING:</b>
-   * Define macro for rounding on support functions
-   *
-   * <b>__FPU_PRESENT:</b>
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
-   *
-   *
-   * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
-   *
-   * <b>Copyright Notice</b>
-   *
-   * Copyright (C) 2010 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the #define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef  __CMSIS_GENERIC              /* enable NVIC and Systick functions */
-#include "string.h"
-    #include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#define PI					3.14159265358979f
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define TABLE_SIZE			256
-#define TABLE_SPACING_Q31	0x800000
-#define TABLE_SPACING_Q15	0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-    {
-      ARM_MATH_SUCCESS = 0,              /**< No error */
-      ARM_MATH_ARGUMENT_ERROR = -1,      /**< One or more arguments are incorrect */
-      ARM_MATH_LENGTH_ERROR = -2,        /**< Length of data buffer is incorrect */
-      ARM_MATH_SIZE_MISMATCH = -3,       /**< Size of matrices is not compatible with the operation. */
-      ARM_MATH_NANINF = -4,              /**< Not-a-number (NaN) or infinity is generated */
-      ARM_MATH_SINGULAR = -5,            /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-      ARM_MATH_TEST_FAILURE = -6         /**< Test Failed  */
-    } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#define __SIMD32(addr)  (*(int32_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else								
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-								
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  static __INLINE q31_t clip_q63_to_q31(
-					q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  static __INLINE q15_t clip_q63_to_q15(
-					q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  static __INLINE q7_t clip_q31_to_q7(
-				      q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  static __INLINE q15_t clip_q31_to_q15(
-					q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  static __INLINE q63_t mult32x64(
-				  q63_t x,
-				  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
-#define __CLZ __clz
-#endif 
-
-#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
-  static __INLINE  uint32_t __CLZ(q31_t data);
-
-
-  static __INLINE uint32_t __CLZ(q31_t data)
-  {
-	  uint32_t count = 0;
-	  uint32_t mask = 0x80000000;
-
-	  while((data & mask) ==  0)
-	  {
-		  count += 1u;
-		  mask = mask >> 1u;
-	  }
-
-	  return(count);
-
-  }
-
-#endif 
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
-   */
-
-  static __INLINE uint32_t arm_recip_q31(
-					 q31_t in,
-					 q31_t * dst,
-					 q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-      {
-	signBits = __CLZ(in) - 1;
-      }
-    else
-      {
-	signBits = __CLZ(-in) - 1;
-      }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-      {
-	tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-	tempVal = 0x7FFFFFFF - tempVal;
-	/*      1.31 with exp 1 */
-	//out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-	out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-      }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
-   */
-  static __INLINE uint32_t arm_recip_q15(
-					 q15_t in,
-					 q15_t * dst,
-					 q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-      {
-	signBits = __CLZ(in) - 17;
-      }
-    else
-      {
-	signBits = __CLZ(-in) - 17;
-      }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-      {
-	tempVal = (q15_t) (((q31_t) in * out) >> 15);
-	tempVal = 0x7FFF - tempVal;
-	/*      1.15 with exp 1 */
-	out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0)
-
-  static __INLINE q31_t __SSAT(
-			       q31_t x,
-			       uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-      {
-	posMax = posMax * 2;
-      }
-
-    if(x > 0)
-      {
-	posMax = (posMax - 1);
-
-	if(x > posMax)
-	  {
-	    x = posMax;
-	  }
-      }
-    else
-      {
-	negMin = -posMax;
-
-	if(x < negMin)
-	  {
-	    x = negMin;
-	  }
-      }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0 */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD8(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (char) x;
-    s = (char) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB8(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (char) x;
-    s = (char) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD16(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHADD16(
-				  q31_t x,
-				  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB16(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSUB16(
-				  q31_t x,
-				  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QASX(
-			       q31_t x,
-			       q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHASX(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSAX(
-			       q31_t x,
-			       q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSAX(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSDX(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    return ((q31_t)(((short) x * (short) (y >> 16)) -
-		    ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUADX(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    return ((q31_t)(((short) x * (short) (y >> 16)) +
-		    ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD(
-			       q31_t x,
-			       q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB(
-			       q31_t x,
-			       q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLAD(
-				q31_t x,
-				q31_t y,
-				q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLADX(
-				 q31_t x,
-				 q31_t y,
-				 q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLSDX(
-				 q31_t x,
-				 q31_t y,
-				 q31_t sum)
-  {
-
-    return (sum - ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALD(
-				 q31_t x,
-				 q31_t y,
-				 q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALDX(
-				  q31_t x,
-				  q31_t y,
-				  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) y)) +
-      ((short) x * (short) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUAD(
-				q31_t x,
-				q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSD(
-				q31_t x,
-				q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-
-
-#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-		  const arm_fir_instance_q7 * S,
-		   q7_t * pSrc,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-		       arm_fir_instance_q7 * S,
-		       uint16_t numTaps,
-		       q7_t * pCoeffs,
-		       q7_t * pState,
-		       uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-		   const arm_fir_instance_q15 * S,
-		    q15_t * pSrc,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-			const arm_fir_instance_q15 * S,
-			 q15_t * pSrc,
-			q15_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-   
-       arm_status arm_fir_init_q15(
-			      arm_fir_instance_q15 * S,
-			      uint16_t numTaps,
-			      q15_t * pCoeffs,
-			      q15_t * pState,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-		   const arm_fir_instance_q31 * S,
-		    q31_t * pSrc,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-			const arm_fir_instance_q31 * S,
-			 q31_t * pSrc,
-			q31_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-			arm_fir_instance_q31 * S,
-			uint16_t numTaps,
-			q31_t * pCoeffs,
-			q31_t * pState,
-			uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-		   const arm_fir_instance_f32 * S,
-		    float32_t * pSrc,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-			arm_fir_instance_f32 * S,
-			uint16_t numTaps,
-			float32_t * pCoeffs,
-			float32_t * pState,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-				  const arm_biquad_casd_df1_inst_q15 * S,
-				   q15_t * pSrc,
-				  q15_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-				       arm_biquad_casd_df1_inst_q15 * S,
-				       uint8_t numStages,
-				       q15_t * pCoeffs,
-				       q15_t * pState,
-				       int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-				       const arm_biquad_casd_df1_inst_q15 * S,
-				        q15_t * pSrc,
-				       q15_t * pDst,
-				       uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-				  const arm_biquad_casd_df1_inst_q31 * S,
-				   q31_t * pSrc,
-				  q31_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-				       const arm_biquad_casd_df1_inst_q31 * S,
-				        q31_t * pSrc,
-				       q31_t * pDst,
-				       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-				       arm_biquad_casd_df1_inst_q31 * S,
-				       uint8_t numStages,
-				       q31_t * pCoeffs,
-				       q31_t * pState,
-				       int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-				  const arm_biquad_casd_df1_inst_f32 * S,
-				   float32_t * pSrc,
-				  float32_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-				       arm_biquad_casd_df1_inst_f32 * S,
-				       uint8_t numStages,
-				       float32_t * pCoeffs,
-				       float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-			     const arm_matrix_instance_f32 * pSrcA,
-			     const arm_matrix_instance_f32 * pSrcB,
-			     arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-			     const arm_matrix_instance_q15 * pSrcA,
-			     const arm_matrix_instance_q15 * pSrcB,
-			     arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-			     const arm_matrix_instance_q31 * pSrcA,
-			     const arm_matrix_instance_q31 * pSrcB,
-			     arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-			       const arm_matrix_instance_f32 * pSrc,
-			       arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-			       const arm_matrix_instance_q15 * pSrc,
-			       arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-			       const arm_matrix_instance_q31 * pSrc,
-			       arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-			      const arm_matrix_instance_f32 * pSrcA,
-			      const arm_matrix_instance_f32 * pSrcB,
-			      arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-			      const arm_matrix_instance_q15 * pSrcA,
-			      const arm_matrix_instance_q15 * pSrcB,
-			      arm_matrix_instance_q15 * pDst,
-			      q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results  
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-				   const arm_matrix_instance_q15 * pSrcA,
-				   const arm_matrix_instance_q15 * pSrcB,
-				   arm_matrix_instance_q15 * pDst,
-				   q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-			      const arm_matrix_instance_q31 * pSrcA,
-			      const arm_matrix_instance_q31 * pSrcB,
-			      arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-				   const arm_matrix_instance_q31 * pSrcA,
-				   const arm_matrix_instance_q31 * pSrcB,
-				   arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-			     const arm_matrix_instance_f32 * pSrcA,
-			     const arm_matrix_instance_f32 * pSrcB,
-			     arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-			     const arm_matrix_instance_q15 * pSrcA,
-			     const arm_matrix_instance_q15 * pSrcB,
-			     arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-			     const arm_matrix_instance_q31 * pSrcA,
-			     const arm_matrix_instance_q31 * pSrcB,
-			     arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-			       const arm_matrix_instance_f32 * pSrc,
-			       float32_t scale,
-			       arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-			       const arm_matrix_instance_q15 * pSrc,
-			       q15_t scaleFract,
-			       int32_t shift,
-			       arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-			       const arm_matrix_instance_q31 * pSrc,
-			       q31_t scaleFract,
-			       int32_t shift,
-			       arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-			arm_matrix_instance_q31 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			q31_t   *pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-			arm_matrix_instance_q15 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			q15_t    *pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-			arm_matrix_instance_f32 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			float32_t   *pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0; 	 /**< The derived gain, A0 = Kp + Ki + Kd . */
-	#ifdef ARM_MATH_CM0  
-	q15_t A1;
-	q15_t A2; 
-	#else 	      
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-	#endif 
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-			arm_pid_instance_f32 * S,
-			int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-			 arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-			arm_pid_instance_q31 * S,
-			int32_t resetStateFlag);
-
- 
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-			 arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-			arm_pid_instance_q15 * S,
-			int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-			 arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;
-    float32_t x1;
-    float32_t xSpacing;
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    float32_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q31_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q15_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows; 	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q7_t *pData;		/**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-		    q7_t * pSrcA,
-		    q7_t * pSrcB,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-		     q15_t * pSrcA,
-		     q15_t * pSrcB,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-		     q31_t * pSrcA,
-		     q31_t * pSrcB,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-		     float32_t * pSrcA,
-		     float32_t * pSrcB,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t  fftLen;                /**< length of the FFT. */
-    uint8_t   ifftFlag;              /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t   bitReverseFlag;        /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t     *pTwiddle;             /**< points to the twiddle factor table. */
-    uint16_t  *pBitRevTable;         /**< points to the bit reversal table. */
-    uint16_t  twidCoefModifier;      /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t  bitRevFactor;          /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t    fftLen;              /**< length of the FFT. */
-    uint8_t     ifftFlag;            /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t     bitReverseFlag;      /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t       *pTwiddle;           /**< points to the twiddle factor table. */
-    uint16_t    *pBitRevTable;       /**< points to the bit reversal table. */
-    uint16_t    twidCoefModifier;    /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t    bitRevFactor;        /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t     fftLen;               /**< length of the FFT. */
-    uint8_t      ifftFlag;             /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t      bitReverseFlag;       /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t    *pTwiddle;            /**< points to the twiddle factor table. */
-    uint16_t     *pBitRevTable;        /**< points to the bit reversal table. */
-    uint16_t     twidCoefModifier;     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t     bitRevFactor;         /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-	float32_t    onebyfftLen;          /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-  /**
-   * @brief Processing function for the Q15 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q15(
-			   const arm_cfft_radix4_instance_q15 * S,
-			   q15_t * pSrc);
-
-  /**
-   * @brief Initialization function for the Q15 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix4_init_q15(
-				      arm_cfft_radix4_instance_q15 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q31(
-			   const arm_cfft_radix4_instance_q31 * S,
-			   q31_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the Q31 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-  
-  arm_status arm_cfft_radix4_init_q31(
-				      arm_cfft_radix4_instance_q31 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_f32(
-			   const arm_cfft_radix4_instance_f32 * S,
-			   float32_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the floating-point CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-  
-  arm_status arm_cfft_radix4_init_f32(
-				      arm_cfft_radix4_instance_f32 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-
-
-  /*----------------------------------------------------------------------
-   *		Internal functions prototypes FFT function
-   ----------------------------------------------------------------------*/
-
-  /**
-   * @brief  Core function for the floating-point CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_f32(
-				float32_t * pSrc,
-				uint16_t fftLen,
-				float32_t * pCoef,
-				uint16_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the floating-point CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @param[in]      onebyfftLen      value of 1/fftLen.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_inverse_f32(
-					float32_t * pSrc,
-					uint16_t fftLen,
-					float32_t * pCoef,
-					uint16_t twidCoefModifier,
-					float32_t onebyfftLen);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
-   * @param[in]      fftSize      length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
-   * @param[in]      *pBitRevTab  points to the bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_f32(
-			   float32_t *pSrc,
-			   uint16_t fftSize,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q31 CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_q31(
-				q31_t *pSrc,
-				uint32_t fftLen,
-				q31_t *pCoef,
-				uint32_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the Q31 CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_inverse_q31(
-					q31_t * pSrc,
-					uint32_t fftLen,
-					q31_t * pCoef,
-					uint32_t twidCoefModifier);
-  
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q31(
-			   q31_t * pSrc,
-			   uint32_t fftLen,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q15 CFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_q15(
-				q15_t *pSrc16,
-				uint32_t fftLen,
-				q15_t *pCoef16,
-				uint32_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the Q15 CIFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_inverse_q15(
-					q15_t *pSrc16,
-					uint32_t fftLen,
-					q15_t *pCoef16,
-					uint32_t twidCoefModifier);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q15(
-			   q15_t * pSrc,
-			   uint32_t fftLen,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
-    uint8_t  ifftFlagR;                       /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-	uint8_t  bitReverseFlagR;                 /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */  
-    q15_t    *pTwiddleAReal;                  /**< points to the real twiddle factor table. */
-    q15_t    *pTwiddleBReal;                  /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q15 *pCfft;	  /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t  ifftFlagR;                         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-	uint8_t  bitReverseFlagR;                   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t    *pTwiddleAReal;                    /**< points to the real twiddle factor table. */
-    q31_t    *pTwiddleBReal;                    /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t  fftLenReal;                       /**< length of the real FFT. */
-    uint16_t  fftLenBy2;                        /**< length of the complex FFT. */
-    uint8_t   ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t   bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-	uint32_t  twidCoefRModifier;                /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  /**
-   * @brief Processing function for the Q15 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q15(
-		    const arm_rfft_instance_q15 * S,
-		    q15_t * pSrc,
-		    q15_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q15 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q15(
-			       arm_rfft_instance_q15 * S,
-			       arm_cfft_radix4_instance_q15 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q31(
-		    const arm_rfft_instance_q31 * S,
-		    q31_t * pSrc,
-		    q31_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q31 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q31(
-			       arm_rfft_instance_q31 * S,
-			       arm_cfft_radix4_instance_q31 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief  Initialization function for the floating-point RFFT/RIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLenReal     length of the FFT.
-   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_f32(
-			       arm_rfft_instance_f32 * S,
-			       arm_cfft_radix4_instance_f32 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_f32(
-		    const arm_rfft_instance_f32 * S,
-		    float32_t * pSrc,
-		    float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-			       arm_dct4_instance_f32 * S,
-			       arm_rfft_instance_f32 * S_RFFT,
-			       arm_cfft_radix4_instance_f32 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-		    const arm_dct4_instance_f32 * S,
-		    float32_t * pState,
-		    float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-			       arm_dct4_instance_q31 * S,
-			       arm_rfft_instance_q31 * S_RFFT,
-			       arm_cfft_radix4_instance_q31 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-		    const arm_dct4_instance_q31 * S,
-		    q31_t * pState,
-		    q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-			       arm_dct4_instance_q15 * S,
-			       arm_rfft_instance_q15 * S_RFFT,
-			       arm_cfft_radix4_instance_q15 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-		    const arm_dct4_instance_q15 * S,
-		    q15_t * pState,
-		    q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-		   float32_t * pSrcA,
-		   float32_t * pSrcB,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-		  q7_t * pSrcA,
-		  q7_t * pSrcB,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-		    q15_t * pSrcA,
-		    q15_t * pSrcB,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-		    q31_t * pSrcA,
-		    q31_t * pSrcB,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-		    float32_t * pSrcA,
-		    float32_t * pSrcB,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-		   q7_t * pSrcA,
-		   q7_t * pSrcB,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-		    q15_t * pSrcA,
-		    q15_t * pSrcB,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-		    q31_t * pSrcA,
-		    q31_t * pSrcB,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-		      float32_t * pSrc,
-		     float32_t scale,
-		     float32_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-		     q7_t * pSrc,
-		    q7_t scaleFract,
-		    int8_t shift,
-		    q7_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-		      q15_t * pSrc,
-		     q15_t scaleFract,
-		     int8_t shift,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-		      q31_t * pSrc,
-		     q31_t scaleFract,
-		     int8_t shift,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-		   q7_t * pSrc,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-		    float32_t * pSrc,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-		    q15_t * pSrc,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-		    q31_t * pSrc,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-			 float32_t * pSrcA,
-			 float32_t * pSrcB,
-			uint32_t blockSize,
-			float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-		        q7_t * pSrcA,
-		        q7_t * pSrcB,
-		       uint32_t blockSize,
-		       q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-			 q15_t * pSrcA,
-			 q15_t * pSrcB,
-			uint32_t blockSize,
-			q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-			 q31_t * pSrcA,
-			 q31_t * pSrcB,
-			uint32_t blockSize,
-			q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-		     q7_t * pSrc,
-		    int8_t shiftBits,
-		    q7_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-		      q15_t * pSrc,
-		     int8_t shiftBits,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-		      q31_t * pSrc,
-		     int8_t shiftBits,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-		       float32_t * pSrc,
-		      float32_t offset,
-		      float32_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-		      q7_t * pSrc,
-		     q7_t offset,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-		       q15_t * pSrc,
-		      q15_t offset,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-		       q31_t * pSrc,
-		      q31_t offset,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-		       float32_t * pSrc,
-		      float32_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-		      q7_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-		       q15_t * pSrc,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-		       q31_t * pSrc,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-		     float32_t * pSrc,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-		    q7_t * pSrc,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-		     q15_t * pSrc,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-		     q31_t * pSrc,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-		     float32_t value,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-		    q7_t value,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-		     q15_t value,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-		     q31_t value,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-
-/**  
- * @brief Convolution of floating-point sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */ 
-
-  void arm_conv_f32(
-		     float32_t * pSrcA,
-		    uint32_t srcALen,
-		     float32_t * pSrcB,
-		    uint32_t srcBLen,
-		    float32_t * pDst);
-
-/**  
- * @brief Convolution of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */
-
-  void arm_conv_q15(
-		     q15_t * pSrcA,
-		    uint32_t srcALen,
-		     q15_t * pSrcB,
-		    uint32_t srcBLen,
-		    q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-		     q31_t * pSrcA,
-		    uint32_t srcALen,
-		     q31_t * pSrcB,
-		    uint32_t srcBLen,
-		    q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-			  q31_t * pSrcA,
-			 uint32_t srcALen,
-			  q31_t * pSrcB,
-			 uint32_t srcBLen,
-			 q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-		    q7_t * pSrcA,
-		   uint32_t srcALen,
-		    q7_t * pSrcB,
-		   uint32_t srcBLen,
-		   q7_t * pDst);
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-				   float32_t * pSrcA,
-				  uint32_t srcALen,
-				   float32_t * pSrcB,
-				  uint32_t srcBLen,
-				  float32_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-				   q15_t * pSrcA,
-				  uint32_t srcALen,
-				   q15_t * pSrcB,
-				  uint32_t srcBLen,
-				  q15_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-				   q31_t * pSrcA,
-				  uint32_t srcALen,
-				   q31_t * pSrcB,
-				  uint32_t srcBLen,
-				  q31_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-				        q31_t * pSrcA,
-				       uint32_t srcALen,
-				        q31_t * pSrcB,
-				       uint32_t srcBLen,
-				       q31_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-				  q7_t * pSrcA,
-				 uint32_t srcALen,
-				  q7_t * pSrcB,
-				 uint32_t srcBLen,
-				 q7_t * pDst,
-				 uint32_t firstIndex,
-				 uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-			    const arm_fir_decimate_instance_f32 * S,
-			     float32_t * pSrc,
-			    float32_t * pDst,
-			    uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-				       arm_fir_decimate_instance_f32 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       float32_t * pCoeffs,
-				       float32_t * pState,
-				       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-			    const arm_fir_decimate_instance_q15 * S,
-			     q15_t * pSrc,
-			    q15_t * pDst,
-			    uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-				 const arm_fir_decimate_instance_q15 * S,
-				  q15_t * pSrc,
-				 q15_t * pDst,
-				 uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-				       arm_fir_decimate_instance_q15 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       q15_t * pCoeffs,
-				       q15_t * pState,
-				       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-			    const arm_fir_decimate_instance_q31 * S,
-			     q31_t * pSrc,
-			    q31_t * pDst,
-			    uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-				 arm_fir_decimate_instance_q31 * S,
-				  q31_t * pSrc,
-				 q31_t * pDst,
-				 uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-				       arm_fir_decimate_instance_q31 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       q31_t * pCoeffs,
-				       q31_t * pState,
-				       uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-			       const arm_fir_interpolate_instance_q15 * S,
-			        q15_t * pSrc,
-			       q15_t * pDst,
-			       uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-					  arm_fir_interpolate_instance_q15 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  q15_t * pCoeffs,
-					  q15_t * pState,
-					  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-			       const arm_fir_interpolate_instance_q31 * S,
-			        q31_t * pSrc,
-			       q31_t * pDst,
-			       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-					  arm_fir_interpolate_instance_q31 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  q31_t * pCoeffs,
-					  q31_t * pState,
-					  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-			       const arm_fir_interpolate_instance_f32 * S,
-			        float32_t * pSrc,
-			       float32_t * pDst,
-			       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-					  arm_fir_interpolate_instance_f32 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  float32_t * pCoeffs,
-					  float32_t * pState,
-					  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-				    const arm_biquad_cas_df1_32x64_ins_q31 * S,
-				     q31_t * pSrc,
-				    q31_t * pDst,
-				    uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-					 arm_biquad_cas_df1_32x64_ins_q31 * S,
-					 uint8_t numStages,
-					 q31_t * pCoeffs,
-					 q63_t * pState,
-					 uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t   numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-				   const arm_biquad_cascade_df2T_instance_f32 * S,
-				    float32_t * pSrc,
-				   float32_t * pDst,
-				   uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-					arm_biquad_cascade_df2T_instance_f32 * S,
-					uint8_t numStages,
-					float32_t * pCoeffs,
-					float32_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
-   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-				arm_fir_lattice_instance_q15 * S,
-				uint16_t numStages,
-				q15_t * pCoeffs,
-				q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-			   const arm_fir_lattice_instance_q15 * S,
-			    q15_t * pSrc,
-			   q15_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-				arm_fir_lattice_instance_q31 * S,
-				uint16_t numStages,
-				q31_t * pCoeffs,
-				q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-			   const arm_fir_lattice_instance_q31 * S,
-			    q31_t * pSrc,
-			   q31_t * pDst,
-			   uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-				arm_fir_lattice_instance_f32 * S,
-				uint16_t numStages,
-				float32_t * pCoeffs,
-				float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-			   const arm_fir_lattice_instance_f32 * S,
-			    float32_t * pSrc,
-			   float32_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-			   const arm_iir_lattice_instance_f32 * S,
-			    float32_t * pSrc,
-			   float32_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-				arm_iir_lattice_instance_f32 * S,
-				uint16_t numStages,
-				float32_t *pkCoeffs,
-				float32_t *pvCoeffs,
-				float32_t *pState,
-				uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-			   const arm_iir_lattice_instance_q31 * S,
-			    q31_t * pSrc,
-			   q31_t * pDst,
-			   uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-				arm_iir_lattice_instance_q31 * S,
-				uint16_t numStages,
-				q31_t *pkCoeffs,
-				q31_t *pvCoeffs,
-				q31_t *pState,
-				uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-			   const arm_iir_lattice_instance_q15 * S,
-			    q15_t * pSrc,
-			   q15_t * pDst,
-			   uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-				arm_iir_lattice_instance_q15 * S,
-				uint16_t numStages,
-				q15_t *pkCoeffs,
-				q15_t *pvCoeffs,
-				q15_t *pState,
-				uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-		   const arm_lms_instance_f32 * S,
-		    float32_t * pSrc,
-		    float32_t * pRef,
-		   float32_t * pOut,
-		   float32_t * pErr,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-			arm_lms_instance_f32 * S,
-			uint16_t numTaps,
-			float32_t * pCoeffs,
-			float32_t * pState,
-			float32_t mu,
-			uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-			arm_lms_instance_q15 * S,
-			uint16_t numTaps,
-			q15_t * pCoeffs,
-			q15_t * pState,
-			q15_t mu,
-			uint32_t blockSize,
-			uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-		   const arm_lms_instance_q15 * S,
-		    q15_t * pSrc,
-		    q15_t * pRef,
-		   q15_t * pOut,
-		   q15_t * pErr,
-		   uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-		   const arm_lms_instance_q31 * S,
-		    q31_t * pSrc,
-		    q31_t * pRef,
-		   q31_t * pOut,
-		   q31_t * pErr,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-			arm_lms_instance_q31 * S,
-			uint16_t numTaps,
-			q31_t *pCoeffs,
-			q31_t *pState,
-			q31_t mu,
-			uint32_t blockSize,
-			uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t  numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-			arm_lms_norm_instance_f32 * S,
-			 float32_t * pSrc,
-			 float32_t * pRef,
-			float32_t * pOut,
-			float32_t * pErr,
-			uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-			     arm_lms_norm_instance_f32 * S,
-			     uint16_t numTaps,
-			     float32_t * pCoeffs,
-			     float32_t * pState,
-			     float32_t mu,
-			     uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-			arm_lms_norm_instance_q31 * S,
-			 q31_t * pSrc,
-			 q31_t * pRef,
-			q31_t * pOut,
-			q31_t * pErr,
-			uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-			     arm_lms_norm_instance_q31 * S,
-			     uint16_t numTaps,
-			     q31_t * pCoeffs,
-			     q31_t * pState,
-			     q31_t mu,
-			     uint32_t blockSize,
-			     uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-			arm_lms_norm_instance_q15 * S,
-			 q15_t * pSrc,
-			 q15_t * pRef,
-			q15_t * pOut,
-			q15_t * pErr,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-			     arm_lms_norm_instance_q15 * S,
-			     uint16_t numTaps,
-			     q15_t * pCoeffs,
-			     q15_t * pState,
-			     q15_t mu,
-			     uint32_t blockSize,
-			     uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-			  float32_t * pSrcA,
-			 uint32_t srcALen,
-			  float32_t * pSrcB,
-			 uint32_t srcBLen,
-			 float32_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-			  q31_t * pSrcA,
-			 uint32_t srcALen,
-			  q31_t * pSrcB,
-			 uint32_t srcBLen,
-			 q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-			       q31_t * pSrcA,
-			      uint32_t srcALen,
-			       q31_t * pSrcB,
-			      uint32_t srcBLen,
-			      q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-			 q7_t * pSrcA,
-			uint32_t srcALen,
-			 q7_t * pSrcB,
-			uint32_t srcBLen,
-			q7_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-			  arm_fir_sparse_instance_f32 * S,
-			   float32_t * pSrc,
-			  float32_t * pDst,
-			  float32_t * pScratchIn,
-			  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-			       arm_fir_sparse_instance_f32 * S,
-			       uint16_t numTaps,
-			       float32_t * pCoeffs,
-			       float32_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-			  arm_fir_sparse_instance_q31 * S,
-			   q31_t * pSrc,
-			  q31_t * pDst,
-			  q31_t * pScratchIn,
-			  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-			       arm_fir_sparse_instance_q31 * S,
-			       uint16_t numTaps,
-			       q31_t * pCoeffs,
-			       q31_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-			  arm_fir_sparse_instance_q15 * S,
-			   q15_t * pSrc,
-			  q15_t * pDst,
-			  q15_t * pScratchIn,
-			  q31_t * pScratchOut,
-			  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-			       arm_fir_sparse_instance_q15 * S,
-			       uint16_t numTaps,
-			       q15_t * pCoeffs,
-			       q15_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-			 arm_fir_sparse_instance_q7 * S,
-			  q7_t * pSrc,
-			 q7_t * pDst,
-			 q7_t * pScratchIn,
-			 q31_t * pScratchOut,
-			 uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-			      arm_fir_sparse_instance_q7 * S,
-			      uint16_t numTaps,
-			      q7_t * pCoeffs,
-			      q7_t * pState,
-			      int32_t *pTapDelay,
-			      uint16_t maxDelay,
-			      uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cos output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-		       float32_t theta,
-		       float32_t *pSinVal,
-		       float32_t *pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cosine output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-		       q31_t theta,
-		       q31_t *pSinVal,
-		       q31_t *pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-			   float32_t * pSrc,
-			  float32_t * pDst,
-			  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-			   q31_t * pSrc,
-			  q31_t * pDst,
-			  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-			   q15_t * pSrc,
-			  q15_t * pDst,
-			  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-				  float32_t * pSrc,
-				 float32_t * pDst,
-				 uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-				  q31_t * pSrc,
-				 q31_t * pDst,
-				 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-				  q15_t * pSrc,
-				 q15_t * pDst,
-				 uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   * 
-   * \par 
-   * \image html PID.gif "Proportional Integral Derivative Controller" 
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.  
-   * The proportional value determines the reaction to the current error, 
-   * the integral value determines the reaction based on the sum of recent errors, 
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure 
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
-   * A separate instance structure must be defined for each PID Controller. 
-   * There are separate instance structure declarations for each of the 3 supported data types. 
-   * 
-   * \par Reset Functions 
-   * There is also an associated reset function for each data type which clears the state array. 
-   *
-   * \par Initialization Functions 
-   * There is also an associated initialization function for each data type. 
-   * The initialization function performs the following operations: 
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.   
-   * 
-   * \par 
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
-   *
-   * \par Fixed-Point Behavior 
-   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
-   * Refer to the function specific documentation below for usage guidelines. 
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  static __INLINE float32_t arm_pid_f32(
-					arm_pid_instance_f32 * S,
-					float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using an internal 64-bit accumulator. 
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
-   * Thus, if the accumulator result overflows it wraps around rather than clip. 
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
-   */
-
-  static __INLINE q31_t arm_pid_q31(
-				    arm_pid_instance_q31 * S,
-				    q31_t in)
-  {
-    q63_t acc;
-	q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using a 64-bit internal accumulator. 
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  static __INLINE q15_t arm_pid_q15(
-				    arm_pid_instance_q15 * S,
-				    q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-    /* Implementation of PID controller */
-
-	#ifdef ARM_MATH_CM0
-
- 	/* acc = A0 * x[n]  */
-	acc = ((q31_t) S->A0 )* in ;
-
-    #else
-				
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-	
-	#endif
-
-	#ifdef ARM_MATH_CM0
-						   
-	/* acc += A1 * x[n-1] + A2 * x[n-2]  */
-	acc += (q31_t) S->A1  *  S->state[0] ;
-	acc += (q31_t) S->A2  *  S->state[1] ;
-
-	#else
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
-
-	#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-  
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-				 const arm_matrix_instance_f32 * src,
-				 arm_matrix_instance_f32 * dst);
-
-  
- 
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  static __INLINE void arm_clarke_f32(
-				      float32_t Ia,
-				      float32_t Ib,
-				      float32_t * pIalpha,
-				      float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_clarke_q31(
-				      q31_t Ia,
-				      q31_t Ib,
-				      q31_t * pIalpha,
-				      q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-		     q7_t * pSrc,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-
- 
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   * 
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   */
-
-
-  static __INLINE void arm_inv_clarke_f32(
-					  float32_t Ialpha,
-					  float32_t Ibeta,
-					  float32_t * pIa,
-					  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version 
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_inv_clarke_q31(
-					  q31_t Ialpha,
-					  q31_t Ibeta,
-					  q31_t * pIa,
-					  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-		      q7_t * pSrc,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents 
-   * from the stationary to the moving reference frame and control the spatial relationship between 
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,  
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  static __INLINE void arm_park_f32(
-				    float32_t Ialpha,
-				    float32_t Ibeta,
-				    float32_t * pId,
-				    float32_t * pIq,
-				    float32_t sinVal,
-				    float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version 
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_park_q31(
-				    q31_t Ialpha,
-				    q31_t Ibeta,
-				    q31_t * pId,
-				    q31_t * pIq,
-				    q31_t sinVal,
-				    q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-		        q7_t * pSrc,
-		       float32_t * pDst,
-		       uint32_t blockSize);
-
- 
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,  
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  static __INLINE void arm_inv_park_f32(
-					float32_t Id,
-					float32_t Iq,
-					float32_t * pIalpha,
-					float32_t * pIbeta,
-					float32_t sinVal,
-					float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version 
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_inv_park_q31(
-					q31_t Id,
-					q31_t Iq,
-					q31_t * pIalpha,
-					q31_t * pIbeta,
-					q31_t sinVal,
-					q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-   
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-			 q31_t * pSrc,
-			float32_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par 
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   * 
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
-   * if x is below input range and returns last value of table if x is above range.  
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  static __INLINE float32_t arm_linear_interp_f32(
-						  arm_linear_interp_instance_f32 * S,
-						  float32_t x)
-  {
-
-	  float32_t y;
-	  float32_t x0, x1;						/* Nearest input values */
-	  float32_t y0, y1;	  					/* Nearest output values */
-	  float32_t xSpacing = S->xSpacing;		/* spacing between input values */
-	  int32_t i;  							/* Index variable */
-	  float32_t *pYData = S->pYData;	    /* pointer to output table */
-
-	  /* Calculation of index */
-	  i =   (x - S->x1) / xSpacing;
-
-	  if(i < 0)
-	  {
-	     /* Iniatilize output for below specified range as least output value of table */
-		 y = pYData[0];
-	  }
-	  else if(i >= S->nValues)
-	  {
-	  	  /* Iniatilize output for above specified range as last output value of table */
-	  	  y = pYData[S->nValues-1];	
-	  }
-	  else
-	  {	 
-	  	  /* Calculation of nearest input values */
-		  x0 = S->x1 + i * xSpacing;
-		  x1 = S->x1 + (i +1) * xSpacing;
-		 
-		 /* Read of nearest output values */
-		  y0 = pYData[i];
-		  y1 = pYData[i + 1];
-		
-		  /* Calculation of output */
-		  y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));	
-		
-	  }
-
-      /* returns output value */
-	  return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
-					      q31_t x, uint32_t nValues)
-  {
-    q31_t y;                                   /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                              /* Index to read nearest output values */
-    
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-
-	if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{
-
-	    /* 20 bits for the fractional part */
-	    /* shift left by 11 to keep fract in 1.31 format */
-	    fract = (x & 0x000FFFFF) << 11;
-	
-	    /* Read two nearest output values from the index in 1.31(q31) format */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-	    y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-	
-	    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-	    y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-	
-	    /* Convert y to 1.31 format */
-	    return (y << 1u);
-
-	}
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12. 
-   *
-   */
-
-
-  static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
-  {
-    q63_t y;                                   /* output */
-    q15_t y0, y1;                              /* Nearest output values */
-    q31_t fract;                               /* fractional part */
-    int32_t index;                            /* Index to read nearest output values */ 
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u); 
-
-	if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{	
-	    /* 20 bits for the fractional part */
-	    /* fract is in 12.20 format */
-	    fract = (x & 0x000FFFFF);
-	
-	    /* Read two nearest output values from the index */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-	    y = ((q63_t) y0 * (0xFFFFF - fract));
-	
-	    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-	    y += ((q63_t) y1 * (fract));
-	
-	    /* convert y to 1.15 format */
-	    return (y >> 20);
-	}
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x,  uint32_t nValues)
-  {
-    q31_t y;                                   /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                              /* Index to read nearest output values */
-    
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-
-    if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{
-
-	    /* 20 bits for the fractional part */
-	    /* fract is in 12.20 format */
-	    fract = (x & 0x000FFFFF);
-	
-	    /* Read two nearest output values from the index and are in 1.7(q7) format */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-	    y = ((y0 * (0xFFFFF - fract)));
-	
-	    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-	    y += (y1 * fract);
-	
-	    /* convert y to 1.7(q7) format */
-	    return (y >> 20u);
-
-	}
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-			 float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-		     q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-		     q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-			 float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-		     q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-		     q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.  
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-
-  static __INLINE arm_status  arm_sqrt_f32(
-					  float32_t in, float32_t *pOut)
-  {
-  	if(in > 0)
-	{
-
-//	#if __FPU_USED
-    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
-		*pOut = __sqrtf(in);
-	#else	  
-		*pOut = sqrtf(in);
-	#endif
-
-		return (ARM_MATH_SUCCESS);
-	}
-  	else
-	{
-		*pOut = 0.0f;
-		return (ARM_MATH_ARGUMENT_ERROR);
-	}
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-		      q31_t in, q31_t *pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-		      q15_t in, q15_t *pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_f32(
-					     int32_t * circBuffer,
-					     int32_t L,
-					     uint16_t * writeOffset,
-					     int32_t bufferInc,
-					     const int32_t * src,
-					     int32_t srcInc,
-					     uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  static __INLINE void arm_circularRead_f32(
-					    int32_t * circBuffer,
-					    int32_t L,
-					    int32_t * readOffset,
-					    int32_t bufferInc,
-					    int32_t * dst,
-					    int32_t * dst_base,
-					    int32_t dst_length,
-					    int32_t dstInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (int32_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update rOffset.  Watch out for positive and negative value  */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q15(
-					     q15_t * circBuffer,
-					     int32_t L,
-					     uint16_t * writeOffset,
-					     int32_t bufferInc,
-					     const q15_t * src,
-					     int32_t srcInc,
-					     uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q15(
-					    q15_t * circBuffer,
-					    int32_t L,
-					    int32_t * readOffset,
-					    int32_t bufferInc,
-					    q15_t * dst,
-					    q15_t * dst_base,
-					    int32_t dst_length,
-					    int32_t dstInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (q15_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q7(
-					    q7_t * circBuffer,
-					    int32_t L,
-					    uint16_t * writeOffset,
-					    int32_t bufferInc,
-					    const q7_t * src,
-					    int32_t srcInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q7(
-					   q7_t * circBuffer,
-					   int32_t L,
-					   int32_t * readOffset,
-					   int32_t bufferInc,
-					   q7_t * dst,
-					   q7_t * dst_base,
-					   int32_t dst_length,
-					   int32_t dstInc,
-					   uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (q7_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update rOffset.  Watch out for positive and negative value */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-		      q31_t * pSrc,
-		     uint32_t blockSize,
-		     q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-		      float32_t * pSrc,
-		     uint32_t blockSize,
-		     float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-		      q15_t * pSrc,
-		     uint32_t blockSize,
-		     q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-		     q7_t * pSrc,
-		    uint32_t blockSize,
-		    q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-		    q7_t * pSrc,
-		   uint32_t blockSize,
-		   q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-		     q15_t * pSrc,
-		    uint32_t blockSize,
-		    q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-		     q31_t * pSrc,
-		    uint32_t blockSize,
-		    q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-		     float32_t * pSrc,
-		    uint32_t blockSize,
-		    float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q63_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-			  float32_t * pSrc,
-			 float32_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-			  q31_t * pSrc,
-			 q31_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-			  q15_t * pSrc,
-			 q15_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-			       q15_t * pSrcA,
-			       q15_t * pSrcB,
-			      uint32_t numSamples,
-			      q31_t * realResult,
-			      q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-			       q31_t * pSrcA,
-			       q31_t * pSrcB,
-			      uint32_t numSamples,
-			      q63_t * realResult,
-			      q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-			       float32_t * pSrcA,
-			       float32_t * pSrcB,
-			      uint32_t numSamples,
-			      float32_t * realResult,
-			      float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-			        q15_t * pSrcCmplx,
-			        q15_t * pSrcReal,
-			       q15_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-			        q31_t * pSrcCmplx,
-			        q31_t * pSrcReal,
-			       q31_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-			        float32_t * pSrcCmplx,
-			        float32_t * pSrcReal,
-			       float32_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-		   q7_t * pSrc,
-		  uint32_t blockSize,
-		  q7_t * result,
-		  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-		   q7_t * pSrc,
-		  uint32_t blockSize,
-		  q7_t * pResult,
-		  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-			        q15_t * pSrcA,
-			        q15_t * pSrcB,
-			       q15_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-			        q31_t * pSrcA,
-			        q31_t * pSrcB,
-			       q31_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-			        float32_t * pSrcA,
-			        float32_t * pSrcB,
-			       float32_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return none. 
-   */
-  void arm_float_to_q31(
-			       float32_t * pSrc,
-			      q31_t * pDst,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q15(
-			       float32_t * pSrc,
-			      q15_t * pDst,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q7(
-			      float32_t * pSrc,
-			     q7_t * pDst,
-			     uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-		       q31_t * pSrc,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-		      q31_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-			 q15_t * pSrc,
-			float32_t * pDst,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-		       q15_t * pSrc,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-		      q15_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.  
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-  
-  static __INLINE float32_t arm_bilinear_interp_f32(
-						    const arm_bilinear_interp_instance_f32 * S,
-						    float32_t X,
-						    float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0  || yIndex > ( S->numCols-1))
-	{
-		return(0);
-	}
-	
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex-1) *  S->numCols ;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex-1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-   /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q31_t arm_bilinear_interp_q31(
-						arm_bilinear_interp_instance_q31 * S,
-						q31_t X,
-						q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                             /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q15_t arm_bilinear_interp_q15(
-						arm_bilinear_interp_instance_q15 * S,
-						q31_t X,
-						q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                             /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q7_t arm_bilinear_interp_q7(
-					      arm_bilinear_interp_instance_q7 * S,
-					      q31_t X,
-					      q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                             /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-
-
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */

bsp/stm32f0x/Libraries/CMSIS/Include/core_cm0.h

@@ -1,665 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M0
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-
-  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks */
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
-  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/stm32f0x/Libraries/CMSIS/Include/core_cm3.h

@@ -1,1236 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M3
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks */
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
-  Type definitions for the Cortex-M System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/** \brief  Set Priority Grouping
-
-  This function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
-    \return                Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    This function reads the active register in NVIC and returns the active bit.
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The returned priority value can be used for NVIC_SetPriority(...) function
-
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    This function decodes an interrupt priority value with the given priority group to
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The priority value can be retrieved with NVIC_GetPriority(...) function
-
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief  ITM Send Character
-
-    This function transmits a character via the ITM channel 0.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    This function inputs a character via external variable ITM_RxBuffer.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \return             Received character
-    \return         -1  No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    This function checks external variable ITM_RxBuffer whether a character is available or not.
-    It returns '1' if a character is available and '0' if no character is available.
-
-    \return          0  No character available
-    \return          1  Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/stm32f0x/Libraries/CMSIS/Include/core_cm4.h

@@ -1,1378 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M4
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-     - Cortex-M SIMD instructions
-
-  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks to define __FPU_USED */
-    #define __FPU_USED         0
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
-#include <core_cmFunc.h>                 /*!< Core Function Access                            */
-#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
-  Type definitions for the Cortex-M System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU CMSIS FPU
-  Type definitions for the Cortex-M Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/** \brief  Set Priority Grouping
-
-  This function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
-    \return                Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    This function reads the active register in NVIC and returns the active bit.
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The returned priority value can be used for NVIC_SetPriority(...) function
-
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    This function decodes an interrupt priority value with the given priority group to
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The priority value can be retrieved with NVIC_GetPriority(...) function
-
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief  ITM Send Character
-
-    This function transmits a character via the ITM channel 0.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    This function inputs a character via external variable ITM_RxBuffer.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \return             Received character
-    \return         -1  No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    This function checks external variable ITM_RxBuffer whether a character is available or not.
-    It returns '1' if a character is available and '0' if no character is available.
-
-    \return          0  No character available
-    \return          1  Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/stm32f0x/Libraries/CMSIS/Include/core_cm4_simd.h

@@ -1,701 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
-/* intrinsic __SADD8      see intrinsics.h */
-/* intrinsic __QADD8      see intrinsics.h */
-/* intrinsic __SHADD8     see intrinsics.h */
-/* intrinsic __UADD8      see intrinsics.h */
-/* intrinsic __UQADD8     see intrinsics.h */
-/* intrinsic __UHADD8     see intrinsics.h */
-/* intrinsic __SSUB8      see intrinsics.h */
-/* intrinsic __QSUB8      see intrinsics.h */
-/* intrinsic __SHSUB8     see intrinsics.h */
-/* intrinsic __USUB8      see intrinsics.h */
-/* intrinsic __UQSUB8     see intrinsics.h */
-/* intrinsic __UHSUB8     see intrinsics.h */
-/* intrinsic __SADD16     see intrinsics.h */
-/* intrinsic __QADD16     see intrinsics.h */
-/* intrinsic __SHADD16    see intrinsics.h */
-/* intrinsic __UADD16     see intrinsics.h */
-/* intrinsic __UQADD16    see intrinsics.h */
-/* intrinsic __UHADD16    see intrinsics.h */
-/* intrinsic __SSUB16     see intrinsics.h */
-/* intrinsic __QSUB16     see intrinsics.h */
-/* intrinsic __SHSUB16    see intrinsics.h */
-/* intrinsic __USUB16     see intrinsics.h */
-/* intrinsic __UQSUB16    see intrinsics.h */
-/* intrinsic __UHSUB16    see intrinsics.h */
-/* intrinsic __SASX       see intrinsics.h */
-/* intrinsic __QASX       see intrinsics.h */
-/* intrinsic __SHASX      see intrinsics.h */
-/* intrinsic __UASX       see intrinsics.h */
-/* intrinsic __UQASX      see intrinsics.h */
-/* intrinsic __UHASX      see intrinsics.h */
-/* intrinsic __SSAX       see intrinsics.h */
-/* intrinsic __QSAX       see intrinsics.h */
-/* intrinsic __SHSAX      see intrinsics.h */
-/* intrinsic __USAX       see intrinsics.h */
-/* intrinsic __UQSAX      see intrinsics.h */
-/* intrinsic __UHSAX      see intrinsics.h */
-/* intrinsic __USAD8      see intrinsics.h */
-/* intrinsic __USADA8     see intrinsics.h */
-/* intrinsic __SSAT16     see intrinsics.h */
-/* intrinsic __USAT16     see intrinsics.h */
-/* intrinsic __UXTB16     see intrinsics.h */
-/* intrinsic __SXTB16     see intrinsics.h */
-/* intrinsic __UXTAB16    see intrinsics.h */
-/* intrinsic __SXTAB16    see intrinsics.h */
-/* intrinsic __SMUAD      see intrinsics.h */
-/* intrinsic __SMUADX     see intrinsics.h */
-/* intrinsic __SMLAD      see intrinsics.h */
-/* intrinsic __SMLADX     see intrinsics.h */
-/* intrinsic __SMLALD     see intrinsics.h */
-/* intrinsic __SMLALDX    see intrinsics.h */
-/* intrinsic __SMUSD      see intrinsics.h */
-/* intrinsic __SMUSDX     see intrinsics.h */
-/* intrinsic __SMLSD      see intrinsics.h */
-/* intrinsic __SMLSDX     see intrinsics.h */
-/* intrinsic __SMLSLD     see intrinsics.h */
-/* intrinsic __SMLSLDX    see intrinsics.h */
-/* intrinsic __SEL        see intrinsics.h */
-/* intrinsic __QADD       see intrinsics.h */
-/* intrinsic __QSUB       see intrinsics.h */
-/* intrinsic __PKHBT      see intrinsics.h */
-/* intrinsic __PKHTB      see intrinsics.h */
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-  
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else	\
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

bsp/stm32f0x/Libraries/CMSIS/Include/core_cmFunc.h

@@ -1,609 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.10
- * @date     26. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static __INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static __INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static __INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
- 
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

bsp/stm32f0x/Libraries/CMSIS/Include/core_cmInstr.h

@@ -1,585 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz 
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-  
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

bsp/stm32f0x/Libraries/CMSIS/README.txt

@@ -1,34 +0,0 @@
-* -------------------------------------------------------------------
-* Copyright (C) 2011 ARM Limited. All rights reserved.  
-* 
-* Date:        25 July 2011  
-* Revision:    V2.10 
-*  
-* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
-* Title:       Release Note for CMSIS
-*
-* -------------------------------------------------------------------
-
-
-NOTE - Open the index.html file to access CMSIS documentation
-
-
-The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
-Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
-and reduces time-to-market for new embedded applications.
-
-CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
-Any user of the software package is bound to the terms and conditions of the end user license agreement.
-
-
-You will find the following sub-directories:
-
-Documentation           - Contains CMSIS documentation.
- 
-DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
-                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
-
-Include                 - CMSIS Core Support and CMSIS DSP Include Files.
-
-Lib                     - CMSIS DSP Binaries 
----

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Include/stm32f0xx.h

@@ -1,3220 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32F0xx devices.  
-  *          
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_STDPERIPH_DRIVER"
-  *              - To change few application-specific parameters such as the HSE 
-  *                crystal frequency
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx
-  * @{
-  */
-    
-#ifndef __STM32F0XX_H
-#define __STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/* Uncomment the line below according to the target STM32F-0 device used in your 
-   application 
-  */
-
-#if !defined (STM32F0XX)
-  #define STM32F0XX    /*!< STM32F0XX: STM32F0xx devices */
-#endif
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-
- - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory 
-   density ranges between 32 and 64 Kbytes.
-  */
-
-#if !defined (STM32F0XX)
- #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
-#endif /* STM32F0XX */
-
-#if !defined  USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
-   used in your application 
-   
-   Tip: To avoid modifying this file each time you need to use different HSE, you
-        can define the HSE value in your toolchain compiler preprocessor.
-  */
-#if !defined  (HSE_VALUE)     
-#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
-   Timeout value 
-   */
-#if !defined  (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
-   Timeout value 
-   */
-#if !defined  (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-#if !defined  (HSI_VALUE) 
-#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI_VALUE */
-
-#if !defined  (HSI14_VALUE) 
-#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* HSI14_VALUE */
-
-#if !defined  (LSI_VALUE) 
-#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.  */
-#endif /* LSI_VALUE */
-
-#if !defined  (LSE_VALUE) 
-#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.0.0
-   */
-#define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
-                                             |(__STM32F0XX_STDPERIPH_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
- * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
-#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
-
-/******  STM32F-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TS_IRQn                     = 8,      /*!< TS Interrupt                                            */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
-  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
-  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
-  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
-  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0.h"
-#include "system_stm32f0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief HDMI-CEC 
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
-  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
-  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
-  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
-  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
-  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
-} COMP_TypeDef;
-
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;       /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint8_t  IDR;      /*!< CRC Independent data register,               Address offset: 0x04 */
-  uint8_t   RESERVED0;    /*!< Reserved,                                                    0x05 */
-  uint16_t  RESERVED1;    /*!< Reserved,                                                    0x06 */
-  __IO uint32_t CR;       /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t  RESERVED2;    /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;     /*!< Initial CRC value register,                  Address offset: 0x10 */
-} CRC_TypeDef;
-
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-       uint32_t RESERVED[6];  /*!< Reserved,                                                                 0x14 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-       uint32_t RESERVED1;    /*!< Reserved,                                                                 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
-  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
-  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
-  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
-  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
-  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
-  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
-  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
-  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
-  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
-  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
-  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
-  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
-  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
-  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
-  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
-  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
-  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
-  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
-}GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
-       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
-  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
-  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
-  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
-  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
-  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
-  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
-  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
-  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
-  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
-  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
-  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
-  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{                           
-  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
-       uint32_t RESERVED0;  /*!< Reserved,                                                 Address offset: 0x14 */
-       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
-       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CAL;        /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
-       uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
-  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
-  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
-  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
-  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
-  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
-  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
-  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
-  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
-} SPI_TypeDef;
-
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
-  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
-  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
-  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
-  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
-  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
-  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
-  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
-  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
-  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
-  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
-  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
-  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
-  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
-  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
-  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
-  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
-  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
-  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
-  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
-  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
-  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
-  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
-  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
-  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
-  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
-  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
-  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
-  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
-  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
-  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
-  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
-  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
-  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
-  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
-  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
-  __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
-  __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */ 
-  __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
-  __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
-  __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
-  __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
-  __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
-  __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-48 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
-  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
-  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
-  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
-} USART_TypeDef;
-
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
-#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
-#define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
-#define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
-#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
-#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
-#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
-#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
-
-#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
-#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define CEC                 ((CEC_TypeDef *) CEC_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
-#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
-#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
-#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
-#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
-#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
-#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
-#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
-#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
-#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
-#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
-#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
-#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
-#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
-#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
-#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
-#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
-#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
-#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
-#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
-#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
-#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
-#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
-#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
-#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
-#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
-#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
-#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
-#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
-#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
-#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define  ADC_CFGR2_JITOFFDIV4                 ((uint32_t)0x80000000)       /*!< Jitter Off when ADC clocked by PCLK div4 */
-#define  ADC_CFGR2_JITOFFDIV2                 ((uint32_t)0x40000000)       /*!< Jitter Off when ADC clocked by PCLK div2 */
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define  ADC_SMPR1_SMPR                      ((uint32_t)0x00000007)        /*!< SMPR[2:0] bits (Sampling time selection) */
-#define  ADC_SMPR1_SMPR_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMPR_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMPR_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
-#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
-#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
-#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
-#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
-#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
-#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
-#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
-#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
-#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
-#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
-#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
-#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
-#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
-#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
-#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
-#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
-#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
-#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
-#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
-#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 HDMI-CEC (CEC)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CEC_CR register  *********************/
-#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
-#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
-#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
-
-/*******************  Bit definition for CEC_CFGR register  *******************/
-#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
-#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
-#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
-#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
-#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
-#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
-#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
-#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
-#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
-
-/*******************  Bit definition for CEC_TXDR register  *******************/
-#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
-
-/*******************  Bit definition for CEC_RXDR register  *******************/
-#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
-
-/*******************  Bit definition for CEC_ISR register  ********************/
-#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
-#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
-#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
-#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
-#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
-#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
-#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
-#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
-#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
-#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
-#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
-#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
-#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
-
-/*******************  Bit definition for CEC_IER register  ********************/
-#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
-#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
-#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
-#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
-#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
-#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
-#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
-#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
-#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
-#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
-#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
-#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
-#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/***********************  Bit definition for COMP_CSR register  ***************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
-#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
-#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
-#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
-#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
-#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
-#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
-#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
-#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
-#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
-#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
-#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
-#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
-#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
-#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
-#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
-#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
-#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
-#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
-#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
-#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
-
-#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
-
-/******************  Bit definition for FLASH_KEYR register  ******************/
-#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
-
-/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
-
-/******************  FLASH Keys  **********************************************/
-#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
-#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
-                                                                                to unlock the write access to the FPEC. */
-                                                               
-#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
-#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
-                                                                                unlock the write access to the option byte block */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
-
-/*******************  Bit definition for FLASH_CR register  *******************/
-#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
-#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
-#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
-#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
-#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
-#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
-#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
-#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
-#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
-#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
-#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
-
-/*******************  Bit definition for FLASH_AR register  *******************/
-#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
-#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
-#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
-
-#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
-#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
-#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
-
-/* Old BOOT1 bit definition, maintained for legacy purpose */
-#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
-
-/* Old BOOT1 bit definition, maintained for legacy purpose */
-#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/******************  Bit definition for OB_RDP register  **********************/
-#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
-#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
-
-/******************  Bit definition for OB_USER register  *********************/
-#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
-#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
-
-/******************  Bit definition for OB_WRP0 register  *********************/
-#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for OB_WRP1 register  *********************/
-#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
-#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_0                 ((uint32_t)0x00000001)
-#define GPIO_IDR_1                 ((uint32_t)0x00000002)
-#define GPIO_IDR_2                 ((uint32_t)0x00000004)
-#define GPIO_IDR_3                 ((uint32_t)0x00000008)
-#define GPIO_IDR_4                 ((uint32_t)0x00000010)
-#define GPIO_IDR_5                 ((uint32_t)0x00000020)
-#define GPIO_IDR_6                 ((uint32_t)0x00000040)
-#define GPIO_IDR_7                 ((uint32_t)0x00000080)
-#define GPIO_IDR_8                 ((uint32_t)0x00000100)
-#define GPIO_IDR_9                 ((uint32_t)0x00000200)
-#define GPIO_IDR_10                ((uint32_t)0x00000400)
-#define GPIO_IDR_11                ((uint32_t)0x00000800)
-#define GPIO_IDR_12                ((uint32_t)0x00001000)
-#define GPIO_IDR_13                ((uint32_t)0x00002000)
-#define GPIO_IDR_14                ((uint32_t)0x00004000)
-#define GPIO_IDR_15                ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_0                 ((uint32_t)0x00000001)
-#define GPIO_ODR_1                 ((uint32_t)0x00000002)
-#define GPIO_ODR_2                 ((uint32_t)0x00000004)
-#define GPIO_ODR_3                 ((uint32_t)0x00000008)
-#define GPIO_ODR_4                 ((uint32_t)0x00000010)
-#define GPIO_ODR_5                 ((uint32_t)0x00000020)
-#define GPIO_ODR_6                 ((uint32_t)0x00000040)
-#define GPIO_ODR_7                 ((uint32_t)0x00000080)
-#define GPIO_ODR_8                 ((uint32_t)0x00000100)
-#define GPIO_ODR_9                 ((uint32_t)0x00000200)
-#define GPIO_ODR_10                ((uint32_t)0x00000400)
-#define GPIO_ODR_11                ((uint32_t)0x00000800)
-#define GPIO_ODR_12                ((uint32_t)0x00001000)
-#define GPIO_ODR_13                ((uint32_t)0x00002000)
-#define GPIO_ODR_14                ((uint32_t)0x00004000)
-#define GPIO_ODR_15                ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
-#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
-#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
-
-#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
-#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE configuration */
-#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
-#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADCPRE bit (ADC prescaler) */
-
-#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK divided by 2 */
-#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK divided by 4 */
-
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
-
-#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
-#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
-#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
-#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
-#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
-#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
-#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
-#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
-#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
-#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
-#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
-#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
-#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
-#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
-#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
-#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
-#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
-#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
-#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
-#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
-#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
-#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
-#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
-#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
-#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
-#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
-#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
-#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
-
-/*******************  Bit definition for RCC_BDCR register  *******************/
-#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
-#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
-#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-
-#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
-#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
-
-/*******************  Bit definition for RCC_CSR register  ********************/  
-#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-#define  RCC_CSR_V18PWRRSTF                 ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
-#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/*******************  Bit definition for RCC_AHBRSTR register  ****************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
-#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS clock reset */
-
-/*******************  Bit definition for RCC_CFGR2 register  ******************/
-/*!< PREDIV1 configuration */
-#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
-#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
-
-#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
-#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
-#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
-#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
-#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
-#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
-#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
-#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
-#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
-#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
-#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
-#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
-#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
-#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
-#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
-#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
-
-/*******************  Bit definition for RCC_CFGR3 register  ******************/
-/*!< USART1 Clock source selection */
-#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
-#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
-/*!< I2C1 Clock source selection */
-#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
-#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
-#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */ 
-
-/*******************  Bit definition for RCC_CR2 register  ********************/
-#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
-#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
-#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
-#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
-#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */
-#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)        /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */
-#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */
-#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)        /*!<  */
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)        /*!<  */
-#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)        /*!<  */
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
-#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
-#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
-#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
-#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
-#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
-#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
-#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
-#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
-#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
-#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
-#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
-#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
-#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
-#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
-#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
-#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
-#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
-#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
-#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
-#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
-#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
-#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
-#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
-#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
-#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
-#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0003) /*!< PF[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0030) /*!< PF[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0003) /*!< PF[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0030) /*!< PF[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0300) /*!< PF[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x3000) /*!< PF[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
-#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
-#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
-#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
-#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
-#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
-#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
-#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
-#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
-#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
-#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
-#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
-#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
-#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
-#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
-#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
-#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
-#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
-#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
-#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
-#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
-
-#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
-
-#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
-#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
-#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
-#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
-#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
-#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
-#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
-#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
-#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
-#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
-#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
-#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
-#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-
-#ifdef USE_STDPERIPH_DRIVER
-  #include "stm32f0xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Include/system_stm32f0xx.h

@@ -1,104 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F0XX_H
-#define __SYSTEM_STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F0xx_System_Exported_types
-  * @{
-  */
-
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s

@@ -1,305 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f0xx.s
-  * @author    MCD Application Team
-  * @version   V1.0.0
-  * @date      23-March-2012
-  * @brief     STM32F0xx Devices vector table for Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
-
-LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
-  bcc CopyDataInit
-  ldr r2, =_sbss
-  b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs r3, #0
-  str  r3, [r2]
-  adds r2, r2, #4
-
-
-LoopFillZerobss:
-  ldr r3, = _ebss
-  cmp r2, r3
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  
-LoopForever:
-    b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word 0
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_1_IRQHandler
-  .word EXTI2_3_IRQHandler
-  .word EXTI4_15_IRQHandler
-  .word TS_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_3_IRQHandler
-  .word DMA1_Channel4_5_IRQHandler
-  .word ADC1_COMP_IRQHandler 
-  .word TIM1_BRK_UP_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word 0  
-  .word TIM14_IRQHandler
-  .word TIM15_IRQHandler
-  .word TIM16_IRQHandler
-  .word TIM17_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word CEC_IRQHandler
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32F0xx devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-  
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-  
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-  
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-  
-  .weak EXTI0_1_IRQHandler
-  .thumb_set EXTI0_1_IRQHandler,Default_Handler
-  
-  .weak EXTI2_3_IRQHandler
-  .thumb_set EXTI2_3_IRQHandler,Default_Handler
-  
-  .weak EXTI4_15_IRQHandler
-  .thumb_set EXTI4_15_IRQHandler,Default_Handler
-  
-  .weak TS_IRQHandler
-  .thumb_set TS_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel2_3_IRQHandler
-  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel4_5_IRQHandler
-  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-  
-  .weak ADC1_COMP_IRQHandler
-  .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-   
-  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
-  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-  
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-  
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-  
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-  
-  .weak TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-  
-  .weak TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-  
-  .weak TIM15_IRQHandler
-  .thumb_set TIM15_IRQHandler,Default_Handler
-  
-  .weak TIM16_IRQHandler
-  .thumb_set TIM16_IRQHandler,Default_Handler
-  
-  .weak TIM17_IRQHandler
-  .thumb_set TIM17_IRQHandler,Default_Handler
-  
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Default_Handler
-  
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Default_Handler
-  
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-  
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-  
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-  
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-  
-  .weak CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s

@@ -1,256 +0,0 @@
-;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
-;* File Name          : startup_stm32f0xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 23-March-2012
-;* Description        : STM32F0xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM0 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-;  @attention
-; 
-;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;  You may not use this file except in compliance with the License.
-;  You may obtain a copy of the License at:
-; 
-;         http://www.st.com/software_license_agreement_liberty_v2
-; 
-;  Unless required by applicable law or agreed to in writing, software 
-;  distributed under the License is distributed on an "AS IS" BASIS, 
-;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;  See the License for the specific language governing permissions and
-;  limitations under the License.
-; 
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000180
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                   ; Top of Stack
-                DCD     Reset_Handler                  ; Reset Handler
-                DCD     NMI_Handler                    ; NMI Handler
-                DCD     HardFault_Handler              ; Hard Fault Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     SVC_Handler                    ; SVCall Handler
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     PendSV_Handler                 ; PendSV Handler
-                DCD     SysTick_Handler                ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_IRQHandler                 ; RCC
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TS_IRQHandler                  ; TS
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
-                DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     TIM14_IRQHandler               ; TIM14
-                DCD     TIM15_IRQHandler               ; TIM15
-                DCD     TIM16_IRQHandler               ; TIM16
-                DCD     TIM17_IRQHandler               ; TIM17
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     0                              ; Reserved
-                DCD     CEC_IRQHandler                 ; CEC
-                DCD     0                              ; Reserved
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_IRQHandler                 [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TS_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_IRQHandler     [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
-                EXPORT  TIM1_CC_IRQHandler             [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM14_IRQHandler               [WEAK]
-                EXPORT  TIM15_IRQHandler               [WEAK]
-                EXPORT  TIM16_IRQHandler               [WEAK]
-                EXPORT  TIM17_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  CEC_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TS_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_COMP_IRQHandler 
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-CEC_IRQHandler   
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-                
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-                
-                 ELSE
-                
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-                 
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s

@@ -1,293 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32f0xx.s
-  * @author    MCD Application Team
-  * @version   V1.0.0
-  * @date      23-March-2012
-  * @brief     STM32F0xx Devices vector table for RIDE7 toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-    
-  .syntax unified
-  .cpu cortex-m0
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section. 
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */  
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called. 
- * @param  None
- * @retval : None
-*/
-
-    .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */  
-  movs r1, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
-    
-LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
-  bcc CopyDataInit
-  ldr r2, =_sbss
-  b LoopFillZerobss
-/* Zero fill the bss segment. */  
-FillZerobss:
-  movs r3, #0
-  str r3, [r2, #4]
-  adds r2, r2, #4
-    
-LoopFillZerobss:
-  ldr r3, = _ebss
-  cmp r2, r3
-  bcc FillZerobss
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an 
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/*******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word 0
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word RTC_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_1_IRQHandler
-  .word EXTI2_3_IRQHandler
-  .word EXTI4_15_IRQHandler
-  .word TS_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_3_IRQHandler
-  .word DMA1_Channel4_5_IRQHandler
-  .word ADC1_COMP_IRQHandler 
-  .word TIM1_BRK_UP_TRG_COM_IRQHandler
-  .word TIM1_CC_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM6_DAC_IRQHandler
-  .word 0
-  .word TIM14_IRQHandler
-  .word TIM15_IRQHandler
-  .word TIM16_IRQHandler
-  .word TIM17_IRQHandler
-  .word I2C1_IRQHandler
-  .word I2C2_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word 0
-  .word CEC_IRQHandler
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32F0xx devices. */
-   
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler. 
-* As they are weak aliases, any function with the same name will override 
-* this definition.
-*
-*******************************************************************************/
-    
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-  
-  .weak RTC_IRQHandler
-  .thumb_set RTC_IRQHandler,Default_Handler
-  
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-  
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-  
-  .weak EXTI0_1_IRQHandler
-  .thumb_set EXTI0_1_IRQHandler,Default_Handler
-  
-  .weak EXTI2_3_IRQHandler
-  .thumb_set EXTI2_3_IRQHandler,Default_Handler
-  
-  .weak EXTI4_15_IRQHandler
-  .thumb_set EXTI4_15_IRQHandler,Default_Handler
-  
-  .weak TS_IRQHandler
-  .thumb_set TS_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel2_3_IRQHandler
-  .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-  
-  .weak DMA1_Channel4_5_IRQHandler
-  .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-  
-  .weak ADC1_COMP_IRQHandler
-  .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-   
-  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
-  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-  
-  .weak TIM1_CC_IRQHandler
-  .thumb_set TIM1_CC_IRQHandler,Default_Handler
-  
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-  
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-  
-  .weak TIM6_DAC_IRQHandler
-  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-  
-  .weak TIM14_IRQHandler
-  .thumb_set TIM14_IRQHandler,Default_Handler
-  
-  .weak TIM15_IRQHandler
-  .thumb_set TIM15_IRQHandler,Default_Handler
-  
-  .weak TIM16_IRQHandler
-  .thumb_set TIM16_IRQHandler,Default_Handler
-  
-  .weak TIM17_IRQHandler
-  .thumb_set TIM17_IRQHandler,Default_Handler
-  
-  .weak I2C1_IRQHandler
-  .thumb_set I2C1_IRQHandler,Default_Handler
-  
-  .weak I2C2_IRQHandler
-  .thumb_set I2C2_IRQHandler,Default_Handler
-  
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-  
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-  
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-  
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-  
-  .weak CEC_IRQHandler
-  .thumb_set CEC_IRQHandler,Default_Handler   
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s

@@ -1,330 +0,0 @@
-;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
-;* File Name          : startup_stm32f0xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 23-March-2012
-;* Description        : STM32F0xx Devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      After Reset the Cortex-M0 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-;  @attention
-; 
-;  Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;  You may not use this file except in compliance with the License.
-;  You may obtain a copy of the License at:
-; 
-;         http://www.st.com/software_license_agreement_liberty_v2
-; 
-;  Unless required by applicable law or agreed to in writing, software 
-;  distributed under the License is distributed on an "AS IS" BASIS, 
-;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;  See the License for the specific language governing permissions and
-;  limitations under the License.
-; 
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                  ; Reset Handler
-
-        DCD     NMI_Handler                    ; NMI Handler
-        DCD     HardFault_Handler              ; Hard Fault Handler
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     SVC_Handler                    ; SVCall Handler
-        DCD     0                              ; Reserved
-        DCD     0                              ; Reserved
-        DCD     PendSV_Handler                 ; PendSV Handler
-        DCD     SysTick_Handler                ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDG_IRQHandler                ; Window Watchdog
-        DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-        DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-        DCD     FLASH_IRQHandler               ; FLASH
-        DCD     RCC_IRQHandler                 ; RCC
-        DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-        DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-        DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-        DCD     TS_IRQHandler                  ; TS
-        DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-        DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-        DCD     DMA1_Channel4_5_IRQHandler     ; DMA1 Channel 4 and Channel 5
-        DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
-        DCD     TIM1_CC_IRQHandler             ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                ; TIM2
-        DCD     TIM3_IRQHandler                ; TIM3
-        DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-        DCD     0                              ; Reserved
-        DCD     TIM14_IRQHandler               ; TIM14
-        DCD     TIM15_IRQHandler               ; TIM15
-        DCD     TIM16_IRQHandler               ; TIM16
-        DCD     TIM17_IRQHandler               ; TIM17
-        DCD     I2C1_IRQHandler                ; I2C1
-        DCD     I2C2_IRQHandler                ; I2C2
-        DCD     SPI1_IRQHandler                ; SPI1
-        DCD     SPI2_IRQHandler                ; SPI2
-        DCD     USART1_IRQHandler              ; USART1
-        DCD     USART2_IRQHandler              ; USART2
-        DCD     0                              ; Reserved
-        DCD     CEC_IRQHandler                 ; CEC
-        DCD     0                              ; Reserved
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-       
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TS_IRQHandler
-        B TS_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
-        B DMA1_Channel4_5_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
-        B TIM1_BRK_UP_TRG_COM_IRQHandler
-        
-                
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-                
-        PUBWEAK TIM14_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
-        B TIM14_IRQHandler
-        
-                
-        PUBWEAK TIM15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
-        B TIM15_IRQHandler
-        
-                
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-        
-                
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-        
-                
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-                
-        PUBWEAK CEC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
-        B CEC_IRQHandler
-
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32f0x/Libraries/CMSIS/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c

@@ -1,353 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f0xx.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
-  *          This file contains the system clock configuration for STM32F0xx devices,
-  *          and is generated by the clock configuration tool  
-  *          STM32F0xx_Clock_Configuration_V1.0.0.xls
-  *
-  * 1.  This file provides two functions and one global variable to be called from 
-  *     user application:
-  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
-  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
-  *                      depending on the configuration made in the clock xls tool.
-  *                      This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32f0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
-  *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
-  *    configure the system clock before to branch to main program.
-  *
-  * 3. If the system clock source selected by user fails to startup, the SystemInit()
-  *    function will do nothing and HSI still used as system clock source. User can 
-  *    add some code to deal with this issue inside the SetSysClock() function.
-  *
-  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
-  *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
-  *    through PLL, and you are using different crystal you have to adapt the HSE
-  *    value to your own configuration.
-  *
-  * 5. This file configures the system clock as follows:
-  *=============================================================================
-  *                         System Clock Configuration
-  *=============================================================================
-  *        System Clock source          | PLL(HSE)
-  *-----------------------------------------------------------------------------
-  *        SYSCLK                       | 48000000 Hz
-  *-----------------------------------------------------------------------------
-  *        HCLK                         | 48000000 Hz
-  *-----------------------------------------------------------------------------
-  *        AHB Prescaler                | 1
-  *-----------------------------------------------------------------------------
-  *        APB1 Prescaler               | 1
-  *-----------------------------------------------------------------------------
-  *        APB2 Prescaler               | 1
-  *-----------------------------------------------------------------------------
-  *        HSE Frequency                | 8000000 Hz
-  *-----------------------------------------------------------------------------
-  *        PLL MUL                      | 6
-  *-----------------------------------------------------------------------------
-  *        VDD                          | 3.3 V
-  *-----------------------------------------------------------------------------
-  *        Flash Latency                | 1 WS
-  *-----------------------------------------------------------------------------
-  *=============================================================================
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f0xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32F0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32f0xx.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
-  * @{
-  */
-uint32_t SystemCoreClock    = 48000000;
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-static void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{    
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80C;
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
-  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-  /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
-      }      
-      break;
-    default: /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK clock frequency ----------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;  
-}
-
-/**
-  * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
-  *         settings.
-  * @note   This function should be called only once the RCC clock configuration
-  *         is reset to the default reset state (done in SystemInit() function).
-  * @param  None
-  * @retval None
-  */
-static void SetSysClock(void)
-{
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-  
-  /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
-  /* Enable HSE */    
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;  
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-  {
-    HSEStatus = (uint32_t)0x01;
-  }
-  else
-  {
-    HSEStatus = (uint32_t)0x00;
-  }  
-
-  if (HSEStatus == (uint32_t)0x01)
-  {
-    /* Enable Prefetch Buffer and set Flash Latency */
-    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
- 
-    /* HCLK = SYSCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-      
-    /* PCLK = HCLK */
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
-
-    /* PLL configuration = HSE * 6 = 48 MHz */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
-            
-    /* Enable PLL */
-    RCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till PLL is ready */
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Select PLL as system clock source */
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
-
-    /* Wait till PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock 
-         configuration. User can add here some code to deal with this error */
-  }  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/CMSIS/index.htm

@@ -1,115 +0,0 @@
-<html>
-
-<head>
-<title>CMSIS Release Notes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 12.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
------------------------------------------------------------*/
-body         { color: #000000; background-color: #FFFFFF; font-size: 75%; font-family: 
-               Verdana, Arial, 'Sans Serif' }
-a:link       { color: #0000FF; text-decoration: underline }
-a:visited    { color: #0000FF; text-decoration: underline }
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-a:hover      { color: #FF0000; text-decoration: underline }
-h1           { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold; 
-               text-align: Center; margin-right: 3 }
-h2           { font-family: Verdana; font-size: 14pt; color: #000080; font-weight: bold; 
-               background-color: #CCCCCC; margin-top: 24; margin-bottom: 3; 
-               padding: 6 }
-h3           { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color: 
-               #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre          { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC; 
-               margin-left: 24; margin-right: 24 }
-ul           { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
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-li           { clear: both; margin-bottom: 6pt }
-table        { font-size: 100%; border-width: 0; padding: 0 }
-th           { color: #FFFFFF; background-color: #000080; text-align: left; vertical-align: 
-               bottom; padding-right: 6pt }
-tr           { text-align: left; vertical-align: top }
-td           { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT       { font-size: 8pt; color: #808080 }
-.TinyT       { font-size: 8pt; text-align: Center }
-code         { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier; 
-               line-height: 120%; font-style: normal }
-/*-----------------------------------------------------------
-Notes
------------------------------------------------------------*/
-p.note       { font-weight: bold; clear: both; margin-bottom: 3pt; padding-top: 6pt }
-/*-----------------------------------------------------------
-Expanding/Contracting Divisions
------------------------------------------------------------*/
-#expand      { text-decoration: none; margin-bottom: 3pt }
-img.expand   { border-style: none; border-width: medium }
-div.expand   { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
-Where List Tags
------------------------------------------------------------*/
-p.wh         { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh     { width: 100% }
-td.whItem    { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom: 
-               6pt }
-td.whDesc    { padding-bottom: 6pt }
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-table.kt     { border: 1pt solid #000000 }
-th.kt        { white-space: nowrap; border-bottom: 1pt solid #000000; padding-left: 6pt; 
-               padding-right: 6pt; padding-top: 4pt; padding-bottom: 4pt }
-tr.kt        {  }
-td.kt        { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0; 
-               padding-left: 6pt; padding-right: 6pt; padding-top: 2pt; 
-               padding-bottom: 2pt }
-/*-----------------------------------------------------------
------------------------------------------------------------*/
--->
-
-</style>
-</head>
-
-<body>
-
-<h1>CMSIS Release Notes</h1>
-<p align="center">Release Notes for CMSIS V2.00</p>
-<p align="center">November 2010</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
-                 Copyright © ARM Ltd.<br>All rights reserved.
-<p align="center"><img src="Documentation/CMSIS_Logo_Final.jpg" height="78" width="197">
-</p>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ul>
-  <li class="LI2"><a href="Documentation/CMSIS_History.htm">CMSIS Version History</a>
-    lists the changes between the different CMSIS versions.
-  </li>
-  <li class="LI2"><a href="Documentation/CMSIS_Core.htm">CMSIS Core Support</a>
-    contains a general description for CMSIS.
-  </li>
-  <li class="LI2"><a href="Documentation/DSP_Lib/html/index.html">CMSIS DSP Software Library</a>
-    describes the CMSIS DSP software library.
-  </li>
-  <li class="LI2"><a href="Documentation/CMSIS_System_View_Description.htm">CMSIS System View Description</a>
-    describes the CMSIS System View Description.
-  </li>
-  <li class="LI2"><a href="Documentation/CMSIS_CM4_SIMD.htm">CMSIS Support for Cortex-M4 SIMD Instructions</a>
-    lists the Cortex-M4 instructions supported by CMSIS.
-  </li>
-  <li class="LI2"><a href="Documentation/CMSIS_DebugSupport.htm">CMSIS Debug Support</a>
-    describes the available CMSIS Debug functions and the used methods.
-  </li>
-  <li class="LI2"><a href="CMSIS END USER LICENCE AGREEMENT.pdf">License</a></li>
-</ul>
-
-
-</body>
-
-</html>

bsp/stm32f0x/Libraries/SConscript

@@ -1,31 +0,0 @@
-import rtconfig
-Import('RTT_ROOT')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-CMSIS/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c
-""")
-
-src += Glob('STM32F0xx_StdPeriph_Driver/src/*.c')
-
-#add for startup script 
-if rtconfig.CROSS_TOOL == 'gcc':
-     src = src + ['CMSIS/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s']
-elif rtconfig.CROSS_TOOL == 'keil':
-     src = src + ['CMSIS/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s']
-elif rtconfig.CROSS_TOOL == 'iar':
-     src = src + ['CMSIS/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s']
-
-path = [cwd + '/STM32F0xx_StdPeriph_Driver/inc', 
-    cwd + '/CMSIS/ST/STM32F0xx/Include',
-    cwd + '/CMSIS/Include']
-
-#CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
-CPPDEFINES = ['USE_STDPERIPH_DRIVER']
-group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h

@@ -1,432 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_adc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the ADC firmware 
-  *          library
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_ADC_H
-#define __STM32F0XX_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  ADC Init structure definition
-  */
-  
-typedef struct
-{
-  uint32_t ADC_Resolution;                  /*!< Selects the resolution of the conversion.
-                                                 This parameter can be a value of @ref ADC_Resolution */
-
-  FunctionalState ADC_ContinuousConvMode;   /*!< Specifies whether the conversion is performed in
-                                                 Continuous or Single mode.
-                                                 This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t ADC_ExternalTrigConvEdge;        /*!< Selects the external trigger Edge and enables the
-                                                 trigger of a regular group. This parameter can be a value
-                                                 of @ref ADC_external_trigger_edge_conversion */
-
-  uint32_t ADC_ExternalTrigConv;            /*!< Defines the external trigger used to start the analog
-                                                 to digital conversion of regular channels. This parameter
-                                                 can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
-
-  uint32_t ADC_DataAlign;                   /*!< Specifies whether the ADC data alignment is left or right.
-                                                 This parameter can be a value of @ref ADC_data_align */
-
-  uint32_t  ADC_ScanDirection;              /*!< Specifies in which direction the channels will be scanned
-                                                 in the sequence. 
-                                                 This parameter can be a value of @ref ADC_Scan_Direction */
-}ADC_InitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
-  * @{
-  */ 
-#define IS_ADC_ALL_PERIPH(PERIPH)                  ((PERIPH) == ADC1)
-
-/** @defgroup ADC_JitterOff
-  * @{
-  */ 
-#define ADC_JitterOff_PCLKDiv2                    ADC_CFGR2_JITOFFDIV2
-#define ADC_JitterOff_PCLKDiv4                    ADC_CFGR2_JITOFFDIV4
-
-#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Resolution
-  * @{
-  */ 
-#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
-#define ADC_Resolution_10b                         ADC_CFGR1_RES_0
-#define ADC_Resolution_8b                          ADC_CFGR1_RES_1
-#define ADC_Resolution_6b                          ADC_CFGR1_RES
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
-                                       ((RESOLUTION) == ADC_Resolution_10b) || \
-                                       ((RESOLUTION) == ADC_Resolution_8b) || \
-                                       ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_external_trigger_edge_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConvEdge_None              ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising            ADC_CFGR1_EXTEN_0
-#define ADC_ExternalTrigConvEdge_Falling           ADC_CFGR1_EXTEN_1
-#define ADC_ExternalTrigConvEdge_RisingFalling     ADC_CFGR1_EXTEN
-
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
-                                    ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
-                                    ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
-                                    ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_external_trigger_sources_for_channels_conversion
-  * @{
-  */ 
-
-/* TIM1 */
-#define ADC_ExternalTrigConv_T1_TRGO               ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC4                ADC_CFGR1_EXTSEL_0
-
-/* TIM2 */
-#define ADC_ExternalTrigConv_T2_TRGO               ADC_CFGR1_EXTSEL_1
-
-/* TIM3 */
-#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
-
-/* TIM15 */
-#define ADC_ExternalTrigConv_T15_TRGO              ADC_CFGR1_EXTSEL_2
-
-#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
-                                         ((CONV) == ADC_ExternalTrigConv_T1_CC4)   || \
-                                         ((CONV) == ADC_ExternalTrigConv_T2_TRGO)  || \
-                                         ((CONV) == ADC_ExternalTrigConv_T3_TRGO)  || \
-                                         ((CONV) == ADC_ExternalTrigConv_T15_TRGO)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_data_align 
-  * @{
-  */ 
-  
-#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left                         ADC_CFGR1_ALIGN
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
-                                  ((ALIGN) == ADC_DataAlign_Left))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_Direction 
-  * @{
-  */ 
-  
-#define ADC_ScanDirection_Upward                   ((uint32_t)0x00000000)
-#define ADC_ScanDirection_Backward                 ADC_CFGR1_SCANDIR
-
-#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
-                                          ((DIRECTION) == ADC_ScanDirection_Backward))
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_Scan_Direction 
-  * @{
-  */ 
-  
-#define ADC_DMAMode_OneShot                        ((uint32_t)0x00000000)
-#define ADC_DMAMode_Circular                       ADC_CFGR1_DMACFG
-
-#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
-                               ((MODE) == ADC_DMAMode_Circular))
-/**
-  * @}
-  */ 
-    
-/** @defgroup ADC_analog_watchdog_selection 
-  * @{
-  */ 
-  
-#define ADC_AnalogWatchdog_Channel_0                 ((uint32_t)0x00000000)
-#define ADC_AnalogWatchdog_Channel_1                 ((uint32_t)0x04000000)
-#define ADC_AnalogWatchdog_Channel_2                 ((uint32_t)0x08000000)
-#define ADC_AnalogWatchdog_Channel_3                 ((uint32_t)0x0C000000)
-#define ADC_AnalogWatchdog_Channel_4                 ((uint32_t)0x10000000)
-#define ADC_AnalogWatchdog_Channel_5                 ((uint32_t)0x14000000)
-#define ADC_AnalogWatchdog_Channel_6                 ((uint32_t)0x18000000)
-#define ADC_AnalogWatchdog_Channel_7                 ((uint32_t)0x1C000000)
-#define ADC_AnalogWatchdog_Channel_8                 ((uint32_t)0x20000000)
-#define ADC_AnalogWatchdog_Channel_9                 ((uint32_t)0x24000000)
-#define ADC_AnalogWatchdog_Channel_10                ((uint32_t)0x28000000)
-#define ADC_AnalogWatchdog_Channel_11                ((uint32_t)0x2C000000)
-#define ADC_AnalogWatchdog_Channel_12                ((uint32_t)0x30000000)
-#define ADC_AnalogWatchdog_Channel_13                ((uint32_t)0x34000000)
-#define ADC_AnalogWatchdog_Channel_14                ((uint32_t)0x38000000)
-#define ADC_AnalogWatchdog_Channel_15                ((uint32_t)0x3C000000)
-#define ADC_AnalogWatchdog_Channel_16                ((uint32_t)0x40000000)
-#define ADC_AnalogWatchdog_Channel_17                ((uint32_t)0x44000000)
-#define ADC_AnalogWatchdog_Channel_18                ((uint32_t)0x48000000)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_1)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_2)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_3)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_4)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_5)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_6)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_7)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_8)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_9)  || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
-                                                 ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
-/**
-  * @}
-  */ 
-  
-/** @defgroup ADC_sampling_times 
-  * @{
-  */ 
-
-#define ADC_SampleTime_1_5Cycles                     ((uint32_t)0x00000000)
-#define ADC_SampleTime_7_5Cycles                     ((uint32_t)0x00000001)
-#define ADC_SampleTime_13_5Cycles                    ((uint32_t)0x00000002)
-#define ADC_SampleTime_28_5Cycles                    ((uint32_t)0x00000003)
-#define ADC_SampleTime_41_5Cycles                    ((uint32_t)0x00000004)
-#define ADC_SampleTime_55_5Cycles                    ((uint32_t)0x00000005)
-#define ADC_SampleTime_71_5Cycles                    ((uint32_t)0x00000006)
-#define ADC_SampleTime_239_5Cycles                   ((uint32_t)0x00000007)
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles)   || \
-                                  ((TIME) == ADC_SampleTime_7_5Cycles)   || \
-                                  ((TIME) == ADC_SampleTime_13_5Cycles)  || \
-                                  ((TIME) == ADC_SampleTime_28_5Cycles)  || \
-                                  ((TIME) == ADC_SampleTime_41_5Cycles)  || \
-                                  ((TIME) == ADC_SampleTime_55_5Cycles)  || \
-                                  ((TIME) == ADC_SampleTime_71_5Cycles)  || \
-                                  ((TIME) == ADC_SampleTime_239_5Cycles))
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_thresholds 
-  * @{
-  */ 
-  
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_channels 
-  * @{
-  */ 
-  
-#define ADC_Channel_0                              ADC_CHSELR_CHSEL0
-#define ADC_Channel_1                              ADC_CHSELR_CHSEL1
-#define ADC_Channel_2                              ADC_CHSELR_CHSEL2
-#define ADC_Channel_3                              ADC_CHSELR_CHSEL3
-#define ADC_Channel_4                              ADC_CHSELR_CHSEL4
-#define ADC_Channel_5                              ADC_CHSELR_CHSEL5
-#define ADC_Channel_6                              ADC_CHSELR_CHSEL6
-#define ADC_Channel_7                              ADC_CHSELR_CHSEL7
-#define ADC_Channel_8                              ADC_CHSELR_CHSEL8
-#define ADC_Channel_9                              ADC_CHSELR_CHSEL9
-#define ADC_Channel_10                             ADC_CHSELR_CHSEL10
-#define ADC_Channel_11                             ADC_CHSELR_CHSEL11
-#define ADC_Channel_12                             ADC_CHSELR_CHSEL12
-#define ADC_Channel_13                             ADC_CHSELR_CHSEL13
-#define ADC_Channel_14                             ADC_CHSELR_CHSEL14
-#define ADC_Channel_15                             ADC_CHSELR_CHSEL15
-#define ADC_Channel_16                             ADC_CHSELR_CHSEL16
-#define ADC_Channel_17                             ADC_CHSELR_CHSEL17
-#define ADC_Channel_18                             ADC_CHSELR_CHSEL18
-
-#define ADC_Channel_TempSensor                     ((uint32_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint                        ((uint32_t)ADC_Channel_17)
-#define ADC_Channel_Vbat                           ((uint32_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup ADC_interrupts_definition 
-  * @{
-  */ 
-  
-#define ADC_IT_ADRDY                               ADC_IER_ADRDYIE
-#define ADC_IT_EOSMP                               ADC_IER_EOSMPIE
-#define ADC_IT_EOC                                 ADC_IER_EOCIE
-#define ADC_IT_EOSEQ                               ADC_IER_EOSEQIE
-#define ADC_IT_OVR                                 ADC_IER_OVRIE
-#define ADC_IT_AWD                                 ADC_IER_AWDIE
- 
-#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
-                           ((IT) == ADC_IT_EOC)   || ((IT) == ADC_IT_EOSEQ) || \
-                           ((IT) == ADC_IT_OVR)   || ((IT) == ADC_IT_AWD))
-
-#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup ADC_flags_definition 
-  * @{
-  */ 
-  
-#define ADC_FLAG_ADRDY                             ADC_ISR_ADRDY
-#define ADC_FLAG_EOSMP                             ADC_ISR_EOSMP
-#define ADC_FLAG_EOC                               ADC_ISR_EOC
-#define ADC_FLAG_EOSEQ                             ADC_ISR_EOSEQ
-#define ADC_FLAG_OVR                               ADC_ISR_OVR
-#define ADC_FLAG_AWD                               ADC_ISR_AWD
-
-#define ADC_FLAG_ADEN                              ((uint32_t)0x01000001)
-#define ADC_FLAG_ADDIS                             ((uint32_t)0x01000002)
-#define ADC_FLAG_ADSTART                           ((uint32_t)0x01000004)
-#define ADC_FLAG_ADSTP                             ((uint32_t)0x01000008)
-#define ADC_FLAG_ADCAL                             ((uint32_t)0x11000000)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xEFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY)   || ((FLAG) == ADC_FLAG_EOSMP) || \
-                               ((FLAG) == ADC_FLAG_EOC)     || ((FLAG)== ADC_FLAG_EOSEQ) || \
-                               ((FLAG) == ADC_FLAG_AWD)     || ((FLAG)== ADC_FLAG_OVR) || \
-                               ((FLAG) == ADC_FLAG_ADEN)    || ((FLAG)== ADC_FLAG_ADDIS) || \
-                               ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG)== ADC_FLAG_ADSTP) || \
-                               ((FLAG) == ADC_FLAG_ADCAL))
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */ 
-
-/*  Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(ADC_TypeDef* ADCx);
-
-/* Initialization and Configuration functions *********************************/ 
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Power saving functions *****************************************************/
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Temperature Sensor , Vrefint and Vbat management function ******************/
-void ADC_TempSensorCmd(FunctionalState NewState);
-void ADC_VrefintCmd(FunctionalState NewState);
-void ADC_VbatCmd(FunctionalState NewState);
-
-/* Channels Configuration functions *******************************************/
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
-void ADC_StopOfConversion(ADC_TypeDef* ADCx);
-void ADC_StartOfConversion(ADC_TypeDef* ADCx);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_ADC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h

@@ -1,300 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_cec.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the CEC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CEC_H
-#define __STM32F0XX_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CEC
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-  
-/** 
-  * @brief CEC Init structure definition 
-  */
-typedef struct
-{
-  uint32_t CEC_SignalFreeTime;     /*!< Specifies the CEC Signal Free Time configuration.
-                                   This parameter can be a value of @ref CEC_Signal_Free_Time */
-  uint32_t CEC_RxTolerance;        /*!< Specifies the CEC Reception Tolerance.
-                                   This parameter can be a value of @ref CEC_RxTolerance */
-  uint32_t CEC_StopReception;      /*!< Specifies the CEC Stop Reception.
-                                   This parameter can be a value of @ref CEC_Stop_Reception */
-  uint32_t CEC_BitRisingError;     /*!< Specifies the CEC Bit Rising Error generation.
-                                   This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
-  uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
-                                   This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
-  uint32_t CEC_BRDNoGen;           /*!< Specifies the CEC Broadcast Error generation.
-                                   This parameter can be a value of @ref CEC_BDR_No_Gen */
-  uint32_t CEC_SFTOption;          /*!< Specifies the CEC Signal Free Time option.
-                                   This parameter can be a value of @ref CEC_SFT_Option */
-
-}CEC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup CEC_Signal_Free_Time
-  * @{
-  */
-#define CEC_SignalFreeTime_Standard     ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard         */
-#define CEC_SignalFreeTime_1T           ((uint32_t)0x00000001) /*!< CEC  1.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_2T           ((uint32_t)0x00000002) /*!< CEC  2.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_3T           ((uint32_t)0x00000003) /*!< CEC  3.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_4T           ((uint32_t)0x00000004) /*!< CEC  4.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_5T           ((uint32_t)0x00000005) /*!< CEC  5.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_6T           ((uint32_t)0x00000006) /*!< CEC  6.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_7T           ((uint32_t)0x00000007) /*!< CEC  7.5 nominal data bit periods     */
-
-#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
-                                       ((TIME) == CEC_SignalFreeTime_1T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_2T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_3T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_4T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_5T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_6T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_7T))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_RxTolerance
-  * @{
-  */
-#define CEC_RxTolerance_Standard        ((uint32_t)0x00000000) /*!< Standard Tolerance Margin            */
-#define CEC_RxTolerance_Extended        CEC_CFGR_RXTOL         /*!< Extended Tolerance Margin            */
-
-#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
-                                        ((TOLERANCE) == CEC_RxTolerance_Extended))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Stop_Reception
-  * @{
-  */
-#define CEC_StopReception_Off           ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
-#define CEC_StopReception_On            CEC_CFGR_BRESTP        /*!< RX Stop on bit Rising Error (BRE)    */
-
-#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
-                                          ((RECEPTION) == CEC_StopReception_Off))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Bit_Rising_Error_Generation
-  * @{
-  */
-#define CEC_BitRisingError_Off          ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
-#define CEC_BitRisingError_On           CEC_CFGR_BREGEN        /*!< Bit Rising Error generation turned On  */
-
-#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
-                                        ((ERROR) == CEC_BitRisingError_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Long_Bit_Error_Generation
-  * @{
-  */
-#define CEC_LongBitPeriodError_Off      ((uint32_t)0x00000000)  /*!< Long Bit Period Error generation turned Off */
-#define CEC_LongBitPeriodError_On       CEC_CFGR_LREGEN         /*!< Long Bit Period Error generation turned On  */
-
-#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
-                                             ((ERROR) == CEC_LongBitPeriodError_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_BDR_No_Gen
-  * @{
-  */
-
-#define CEC_BRDNoGen_Off      ((uint32_t)0x00000000)  /*!< Broadcast Bit Rising Error generation turned Off */
-#define CEC_BRDNoGen_On       CEC_CFGR_BRDNOGEN       /*!< Broadcast Bit Rising Error generation turned On  */
-
-#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
-                                        ((ERROR) == CEC_BRDNoGen_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_SFT_Option
-  * @{
-  */
-#define CEC_SFTOption_Off              ((uint32_t)0x00000000)  /*!< SFT option turned Off                   */
-#define CEC_SFTOption_On               CEC_CFGR_SFTOPT         /*!< SFT option turned On                    */
-
-#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
-                                  ((OPTION) == CEC_SFTOption_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Own_Address
-  * @{
-  */
-#define IS_CEC_ADDRESS(ADDRESS)         ((ADDRESS) < 0x10)
-
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Interrupt_Configuration_definition
-  * @{
-  */
-#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
-#define CEC_IT_TXERR                    CEC_IER_TXERRIE
-#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
-#define CEC_IT_TXEND                    CEC_IER_TXENDIE
-#define CEC_IT_TXBR                     CEC_IER_TXBRIE
-#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
-#define CEC_IT_LBPE                     CEC_IER_LBPEIE
-#define CEC_IT_SBPE                     CEC_IER_SBPEIE
-#define CEC_IT_BRE                      CEC_IER_BREIEIE
-#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
-#define CEC_IT_RXEND                    CEC_IER_RXENDIE
-#define CEC_IT_RXBR                     CEC_IER_RXBRIE
-
-#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
-
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
-                           ((IT) == CEC_IT_TXERR)|| \
-                           ((IT) == CEC_IT_TXUDR)|| \
-                           ((IT) == CEC_IT_TXEND)|| \
-                           ((IT) == CEC_IT_TXBR)|| \
-                           ((IT) == CEC_IT_ARBLST)|| \
-                           ((IT) == CEC_IT_RXACKE)|| \
-                           ((IT) == CEC_IT_LBPE)|| \
-                           ((IT) == CEC_IT_SBPE)|| \
-                           ((IT) == CEC_IT_BRE)|| \
-                           ((IT) == CEC_IT_RXOVR)|| \
-                           ((IT) == CEC_IT_RXEND)|| \
-                           ((IT) == CEC_IT_RXBR))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_ISR_register_flags_definition
-  * @{
-  */
-#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR                  CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND                  CEC_ISR_TXEND
-#define CEC_FLAG_TXBR                   CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE                   CEC_ISR_LBPE
-#define CEC_FLAG_SBPE                   CEC_ISR_SBPE
-#define CEC_FLAG_BRE                    CEC_ISR_BRE
-#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND                  CEC_ISR_RXEND
-#define CEC_FLAG_RXBR                   CEC_ISR_RXBR
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
-                               ((FLAG) == CEC_FLAG_TXERR)|| \
-                               ((FLAG) == CEC_FLAG_TXUDR)|| \
-                               ((FLAG) == CEC_FLAG_TXEND)|| \
-                               ((FLAG) == CEC_FLAG_TXBR)|| \
-                               ((FLAG) == CEC_FLAG_ARBLST)|| \
-                               ((FLAG) == CEC_FLAG_RXACKE)|| \
-                               ((FLAG) == CEC_FLAG_LBPE)|| \
-                               ((FLAG) == CEC_FLAG_SBPE)|| \
-                               ((FLAG) == CEC_FLAG_BRE)|| \
-                               ((FLAG) == CEC_FLAG_RXOVR)|| \
-                               ((FLAG) == CEC_FLAG_RXEND)|| \
-                               ((FLAG) == CEC_FLAG_RXBR))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the CEC configuration to the default reset state *****/
-void CEC_DeInit(void);
-
-/* CEC_Initialization and Configuration functions *****************************/
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ListenModeCmd(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_OwnAddressClear(void);
-
-/* CEC_Data transfers functions ***********************************************/
-void CEC_SendData(uint8_t Data);
-uint8_t CEC_ReceiveData(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessage(void);
-
-/* CEC_Interrupts and flags management functions ******************************/
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CEC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h

@@ -1,243 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_comp.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the COMP firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_COMP_H
-#define __STM32F0XX_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup COMP
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  COMP Init structure definition  
-  */
-  
-typedef struct
-{
-
-  uint32_t COMP_InvertingInput;     /*!< Selects the inverting input of the comparator.
-                                          This parameter can be a value of @ref COMP_InvertingInput */
-
-  uint32_t COMP_Output;             /*!< Selects the output redirection of the comparator.
-                                          This parameter can be a value of @ref COMP_Output */
-
-  uint32_t COMP_OutputPol;           /*!< Selects the output polarity of the comparator.
-                                          This parameter can be a value of @ref COMP_OutputPolarity */
-
-  uint32_t COMP_Hysteresis;         /*!< Selects the hysteresis voltage of the comparator.
-                                          This parameter can be a value of @ref COMP_Hysteresis */
-
-  uint32_t COMP_Mode;               /*!< Selects the operating mode of the comparator
-                                         and allows to adjust the speed/consumption.
-                                          This parameter can be a value of @ref COMP_Mode */
-
-}COMP_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-   
-/** @defgroup COMP_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup COMP_Selection
-  * @{
-  */
-
-#define COMP_Selection_COMP1                    ((uint32_t)0x00000000) /*!< COMP1 Selection */
-#define COMP_Selection_COMP2                    ((uint32_t)0x00000010) /*!< COMP2 Selection */
-
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
-                                    ((PERIPH) == COMP_Selection_COMP2))
- 
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_InvertingInput
-  * @{
-  */
-
-#define COMP_InvertingInput_1_4VREFINT          ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_1_2VREFINT          COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_3_4VREFINT          COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_VREFINT             ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_DAC1                COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT connected to comparator inverting input */
-#define COMP_InvertingInput_IO                  ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
-
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
-                                        ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
-                                        ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
-                                        ((INPUT) == COMP_InvertingInput_VREFINT)    || \
-                                        ((INPUT) == COMP_InvertingInput_DAC1)       || \
-                                        ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
-                                        ((INPUT) == COMP_InvertingInput_IO))
-/**
-  * @}
-  */ 
-  
-/** @defgroup COMP_Output
-  * @{
-  */
-
-#define COMP_Output_None                  ((uint32_t)0x00000000)   /*!< COMP output isn't connected to other peripherals */
-#define COMP_Output_TIM1BKIN              COMP_CSR_COMP1OUTSEL_0   /*!< COMP output connected to TIM1 Break Input (BKIN) */
-#define COMP_Output_TIM1IC1               COMP_CSR_COMP1OUTSEL_1   /*!< COMP output connected to TIM1 Input Capture 1 */
-#define COMP_Output_TIM1OCREFCLR          ((uint32_t)0x00000300)   /*!< COMP output connected to TIM1 OCREF Clear */
-#define COMP_Output_TIM2IC4               COMP_CSR_COMP1OUTSEL_2   /*!< COMP output connected to TIM2 Input Capture 4 */
-#define COMP_Output_TIM2OCREFCLR          ((uint32_t)0x00000500)   /*!< COMP output connected to TIM2 OCREF Clear */
-#define COMP_Output_TIM3IC1               ((uint32_t)0x00000600)   /*!< COMP output connected to TIM3 Input Capture 1 */
-#define COMP_Output_TIM3OCREFCLR          COMP_CSR_COMP1OUTSEL     /*!< COMP output connected to TIM3 OCREF Clear */
-
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None)         || \
-                                ((OUTPUT) == COMP_Output_TIM1BKIN)     || \
-                                ((OUTPUT) == COMP_Output_TIM1IC1)      || \
-                                ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
-                                ((OUTPUT) == COMP_Output_TIM2IC4)      || \
-                                ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
-                                ((OUTPUT) == COMP_Output_TIM3IC1)      || \
-                                ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_OutputPolarity
-  * @{
-  */
-#define COMP_OutputPol_NonInverted          ((uint32_t)0x00000000)  /*!< COMP output on GPIO isn't inverted */
-#define COMP_OutputPol_Inverted             COMP_CSR_COMP1POL       /*!< COMP output on GPIO is inverted */
-
-#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted)  || \
-                                 ((POL) == COMP_OutputPol_Inverted))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_Hysteresis
-  * @{
-  */
-/* Please refer to the electrical characteristics in the device datasheet for
-   the hysteresis level */
-#define COMP_Hysteresis_No                         0x00000000           /*!< No hysteresis */
-#define COMP_Hysteresis_Low                        COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
-#define COMP_Hysteresis_Medium                     COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
-#define COMP_Hysteresis_High                       COMP_CSR_COMP1HYST   /*!< Hysteresis level high */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS)    (((HYSTERESIS) == COMP_Hysteresis_No) || \
-                                           ((HYSTERESIS) == COMP_Hysteresis_Low) || \
-                                           ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
-                                           ((HYSTERESIS) == COMP_Hysteresis_High))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Mode
-  * @{
-  */
-/* Please refer to the electrical characteristics in the device datasheet for
-   the power consumption values */
-#define COMP_Mode_HighSpeed                     0x00000000            /*!< High Speed */
-#define COMP_Mode_MediumSpeed                   COMP_CSR_COMP1MODE_0  /*!< Medium Speed */
-#define COMP_Mode_LowPower                      COMP_CSR_COMP1MODE_1 /*!< Low power mode */
-#define COMP_Mode_UltraLowPower                 COMP_CSR_COMP1MODE   /*!< Ultra-low power mode */
-
-#define IS_COMP_MODE(MODE)    (((MODE) == COMP_Mode_UltraLowPower) || \
-                               ((MODE) == COMP_Mode_LowPower)      || \
-                               ((MODE) == COMP_Mode_MediumSpeed)   || \
-                               ((MODE) == COMP_Mode_HighSpeed))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputLevel
-  * @{
-  */ 
-/* When output polarity is not inverted, comparator output is high when
-   the non-inverting input is at a higher voltage than the inverting input */
-#define COMP_OutputLevel_High                   COMP_CSR_COMP1OUT
-/* When output polarity is not inverted, comparator output is low when
-   the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OutputLevel_Low                    ((uint32_t)0x00000000)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the COMP configuration to the default reset state ****/
-void COMP_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
-void COMP_SwitchCmd(FunctionalState NewState);
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
-
-/* Window mode control function ***********************************************/
-void COMP_WindowCmd(FunctionalState NewState);
-
-/* COMP configuration locking function ****************************************/
-void COMP_LockConfig(uint32_t COMP_Selection);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_COMP_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h

@@ -1,100 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_crc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the CRC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CRC_H
-#define __STM32F0XX_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Constants
-  * @{
-  */
-#define CRC_ReverseInputData_No             ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
-#define CRC_ReverseInputData_8bits          CRC_CR_REV_IN_0        /*!< Reverse operation of Input Data on 8 bits */
-#define CRC_ReverseInputData_16bits         CRC_CR_REV_IN_1        /*!< Reverse operation of Input Data on 16 bits */
-#define CRC_ReverseInputData_32bits         CRC_CR_REV_IN          /*!< Reverse operation of Input Data on 32 bits */
-
-#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No)     || \
-                                         ((DATA) == CRC_ReverseInputData_8bits)  || \
-                                         ((DATA) == CRC_ReverseInputData_16bits) || \
-                                         ((DATA) == CRC_ReverseInputData_32bits))
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRC computation unit **********************************/
-void CRC_DeInit(void);
-void CRC_ResetDR(void);
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
-void CRC_ReverseOutputDataCmd(FunctionalState NewState);
-void CRC_SetInitRegister(uint32_t CRC_InitValue);
-
-/* CRC computation ************************************************************/
-uint32_t CRC_CalcCRC(uint32_t CRC_Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-
-/* Independent register (IDR) access (write/read) *****************************/
-void CRC_SetIDRegister(uint8_t CRC_IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CRC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h

@@ -1,207 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dac.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the DAC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DAC_H
-#define __STM32F0XX_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
- 
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DAC Init structure definition
-  */
-  
-typedef struct
-{
-  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
-                                                  This parameter can be a value of @ref DAC_Trigger */
-
-  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                                  This parameter can be a value of @ref DAC_OutputBuffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup DAC_Trigger 
-  * @{
-  */
-  
-#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T3_TRGO                ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T15_TRGO               ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
-                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
-                                 ((TRIGGER) == DAC_Trigger_Software))
-                                 
-/**
-  * @}
-  */
-
-/** @defgroup DAC_OutputBuffer 
-  * @{
-  */
-
-#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable           DAC_CR_BOFF1
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
-                                           ((STATE) == DAC_OutputBuffer_Disable))
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_Channel_selection 
-  * @{
-  */
-
-#define DAC_Channel_1                      ((uint32_t)0x00000000)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1))
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment
-  * @{
-  */
-
-#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
-#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
-#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
-                             ((ALIGN) == DAC_Align_12b_L) || \
-                             ((ALIGN) == DAC_Align_8b_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data 
-  * @{
-  */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_interrupts_definition 
-  * @{
-  */ 
-  
-#define DAC_IT_DMAUDR                      DAC_SR_DMAUDR1
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DAC_flags_definition 
-  * @{
-  */ 
-  
-#define DAC_FLAG_DMAUDR                    DAC_SR_DMAUDR1
-  
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(void);
-
-/*  DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DAC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h

@@ -1,105 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dbgmcu.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the DBGMCU firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DBGMCU_H
-#define __STM32F0XX_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DBGMCU
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup DBGMCU_Exported_Constants
-  * @{
-  */
-
-#define DBGMCU_STOP                  DBGMCU_CR_DBG_STOP
-#define DBGMCU_STANDBY               DBGMCU_CR_DBG_STANDBY
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP
-#define DBGMCU_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP
-#define DBGMCU_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP
-#define DBGMCU_TIM14_STOP            DBGMCU_APB1_FZ_DBG_TIM14_STOP
-#define DBGMCU_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP
-#define DBGMCU_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP
-#define DBGMCU_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP
-#define DBGMCU_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFFDFE2EC) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP             DBGMCU_APB2_FZ_DBG_TIM1_STOP
-#define DBGMCU_TIM15_STOP            DBGMCU_APB2_FZ_DBG_TIM15_STOP
-#define DBGMCU_TIM16_STOP            DBGMCU_APB2_FZ_DBG_TIM16_STOP
-#define DBGMCU_TIM17_STOP            DBGMCU_APB2_FZ_DBG_TIM17_STOP
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */ 
-
-/* Device and Revision ID management functions ********************************/ 
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-
-/* Peripherals Configuration functions ****************************************/ 
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_DBGMCU_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h

@@ -1,351 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dma.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the DMA firmware
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DMA_H
-#define __STM32F0XX_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DMA Init structures definition
-  */
-typedef struct
-{
-  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
-
-  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
-
-  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
-                                        This parameter can be a value of @ref DMA_data_transfer_direction     */
-
-  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
-                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
-                                        or DMA_MemoryDataSize members depending in the transfer direction     */
-
-  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
-                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
-  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
-                                        This parameter can be a value of @ref DMA_memory_incremented_mode     */
-
-  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
-                                        This parameter can be a value of @ref DMA_peripheral_data_size        */
-
-  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
-                                        This parameter can be a value of @ref DMA_memory_data_size            */
-
-  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
-                                        This parameter can be a value of @ref DMA_circular_normal_mode
-                                        @note: The circular buffer mode cannot be used if the memory-to-memory
-                                              data transfer is configured on the selected Channel */
-
-  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
-                                        This parameter can be a value of @ref DMA_priority_level              */
-
-  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
-                                        This parameter can be a value of @ref DMA_memory_to_memory            */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
-  * @{
-  */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
-                                   ((PERIPH) == DMA1_Channel2) || \
-                                   ((PERIPH) == DMA1_Channel3) || \
-                                   ((PERIPH) == DMA1_Channel4) || \
-                                   ((PERIPH) == DMA1_Channel5))
-
-/** @defgroup DMA_data_transfer_direction 
-  * @{
-  */
-
-#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
-#define DMA_DIR_PeripheralDST              DMA_CCR_DIR
-
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
-                         ((DIR) == DMA_DIR_PeripheralDST))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_peripheral_incremented_mode 
-  * @{
-  */
-
-#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
-#define DMA_PeripheralInc_Enable           DMA_CCR_PINC
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
-                                            ((STATE) == DMA_PeripheralInc_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_incremented_mode 
-  * @{
-  */
-
-#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
-#define DMA_MemoryInc_Enable               DMA_CCR_MINC
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
-                                        ((STATE) == DMA_MemoryInc_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_peripheral_data_size 
-  * @{
-  */
-
-#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
-#define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
-                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
-                                           ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_data_size 
-  * @{
-  */
-
-#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
-#define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
-                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
-                                       ((SIZE) == DMA_MemoryDataSize_Word))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_circular_normal_mode 
-  * @{
-  */
-
-#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
-#define DMA_Mode_Circular                  DMA_CCR_CIRC
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_priority_level 
-  * @{
-  */
-
-#define DMA_Priority_VeryHigh              DMA_CCR_PL
-#define DMA_Priority_High                  DMA_CCR_PL_1
-#define DMA_Priority_Medium                DMA_CCR_PL_0
-#define DMA_Priority_Low                   ((uint32_t)0x00000000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
-                                   ((PRIORITY) == DMA_Priority_High) || \
-                                   ((PRIORITY) == DMA_Priority_Medium) || \
-                                   ((PRIORITY) == DMA_Priority_Low))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_memory_to_memory 
-  * @{
-  */
-
-#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
-#define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
-
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupts_definition
-  * @{
-  */
-
-#define DMA_IT_TC                          DMA_CCR_TCIE
-#define DMA_IT_HT                          DMA_CCR_HTIE
-#define DMA_IT_TE                          DMA_CCR_TEIE
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1                        DMA_ISR_GIF1
-#define DMA1_IT_TC1                        DMA_ISR_TCIF1
-#define DMA1_IT_HT1                        DMA_ISR_HTIF1
-#define DMA1_IT_TE1                        DMA_ISR_TEIF1
-#define DMA1_IT_GL2                        DMA_ISR_GIF2
-#define DMA1_IT_TC2                        DMA_ISR_TCIF2
-#define DMA1_IT_HT2                        DMA_ISR_HTIF2
-#define DMA1_IT_TE2                        DMA_ISR_TEIF2
-#define DMA1_IT_GL3                        DMA_ISR_GIF3
-#define DMA1_IT_TC3                        DMA_ISR_TCIF3
-#define DMA1_IT_HT3                        DMA_ISR_HTIF3
-#define DMA1_IT_TE3                        DMA_ISR_TEIF3
-#define DMA1_IT_GL4                        DMA_ISR_GIF4
-#define DMA1_IT_TC4                        DMA_ISR_TCIF4
-#define DMA1_IT_HT4                        DMA_ISR_HTIF4
-#define DMA1_IT_TE4                        DMA_ISR_TEIF4
-#define DMA1_IT_GL5                        DMA_ISR_GIF5
-#define DMA1_IT_TC5                        DMA_ISR_TCIF5
-#define DMA1_IT_HT5                        DMA_ISR_HTIF5
-#define DMA1_IT_TE5                        DMA_ISR_TEIF5
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
-                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
-                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
-                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
-                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
-                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
-                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
-                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
-                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
-                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flags_definition 
-  * @{
-  */
-#define DMA1_FLAG_GL1                      DMA_ISR_GIF1
-#define DMA1_FLAG_TC1                      DMA_ISR_TCIF1
-#define DMA1_FLAG_HT1                      DMA_ISR_HTIF1
-#define DMA1_FLAG_TE1                      DMA_ISR_TEIF1
-#define DMA1_FLAG_GL2                      DMA_ISR_GIF2
-#define DMA1_FLAG_TC2                      DMA_ISR_TCIF2
-#define DMA1_FLAG_HT2                      DMA_ISR_HTIF2
-#define DMA1_FLAG_TE2                      DMA_ISR_TEIF2
-#define DMA1_FLAG_GL3                      DMA_ISR_GIF3
-#define DMA1_FLAG_TC3                      DMA_ISR_TCIF3
-#define DMA1_FLAG_HT3                      DMA_ISR_HTIF3
-#define DMA1_FLAG_TE3                      DMA_ISR_TEIF3
-#define DMA1_FLAG_GL4                      DMA_ISR_GIF4
-#define DMA1_FLAG_TC4                      DMA_ISR_TCIF4
-#define DMA1_FLAG_HT4                      DMA_ISR_HTIF4
-#define DMA1_FLAG_TE4                      DMA_ISR_TEIF4
-#define DMA1_FLAG_GL5                      DMA_ISR_GIF5
-#define DMA1_FLAG_TC5                      DMA_ISR_TCIF5
-#define DMA1_FLAG_HT5                      DMA_ISR_HTIF5
-#define DMA1_FLAG_TE5                      DMA_ISR_TEIF5
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
-                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
-                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
-                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
-                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
-                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
-                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
-                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
-                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
-                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Buffer_Size 
-  * @{
-  */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DMA configuration to the default reset state ******/
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-
-/* Data Counter functions******************************************************/ 
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Interrupts and flags management functions **********************************/
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-void DMA_ClearFlag(uint32_t DMA_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DMA_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h

@@ -1,194 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_exti.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the EXTI 
-  *          firmware library
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_EXTI_H
-#define __STM32F0XX_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup EXTI
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  EXTI mode enumeration  
-  */
-
-typedef enum
-{
-  EXTI_Mode_Interrupt = 0x00,
-  EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/** 
-  * @brief  EXTI Trigger enumeration  
-  */
-
-typedef enum
-{
-  EXTI_Trigger_Rising = 0x08,
-  EXTI_Trigger_Falling = 0x0C,
-  EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
-                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
-                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
-  * @brief  EXTI Init Structure definition
-  */
-
-typedef struct
-{
-  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
-                                         This parameter can be any combination of @ref EXTI_Lines */
-
-  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
-                                         This parameter can be a value of @ref EXTIMode_TypeDef */
-
-  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                         This parameter can be a value of @ref EXTIMode_TypeDef */
-
-  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
-                                         This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
-  * @{
-  */
-/** @defgroup EXTI_Lines 
-  * @{
-  */
-
-#define EXTI_Line0       ((uint32_t)0x00000001)  /*!< External interrupt line 0  */
-#define EXTI_Line1       ((uint32_t)0x00000002)  /*!< External interrupt line 1  */
-#define EXTI_Line2       ((uint32_t)0x00000004)  /*!< External interrupt line 2  */
-#define EXTI_Line3       ((uint32_t)0x00000008)  /*!< External interrupt line 3  */
-#define EXTI_Line4       ((uint32_t)0x00000010)  /*!< External interrupt line 4  */
-#define EXTI_Line5       ((uint32_t)0x00000020)  /*!< External interrupt line 5  */
-#define EXTI_Line6       ((uint32_t)0x00000040)  /*!< External interrupt line 6  */
-#define EXTI_Line7       ((uint32_t)0x00000080)  /*!< External interrupt line 7  */
-#define EXTI_Line8       ((uint32_t)0x00000100)  /*!< External interrupt line 8  */
-#define EXTI_Line9       ((uint32_t)0x00000200)  /*!< External interrupt line 9  */
-#define EXTI_Line10      ((uint32_t)0x00000400)  /*!< External interrupt line 10 */
-#define EXTI_Line11      ((uint32_t)0x00000800)  /*!< External interrupt line 11 */
-#define EXTI_Line12      ((uint32_t)0x00001000)  /*!< External interrupt line 12 */
-#define EXTI_Line13      ((uint32_t)0x00002000)  /*!< External interrupt line 13 */
-#define EXTI_Line14      ((uint32_t)0x00004000)  /*!< External interrupt line 14 */
-#define EXTI_Line15      ((uint32_t)0x00008000)  /*!< External interrupt line 15 */
-#define EXTI_Line16      ((uint32_t)0x00010000)  /*!< External interrupt line 16 
-                                                      Connected to the PVD Output */
-#define EXTI_Line17      ((uint32_t)0x00020000)  /*!< Internal interrupt line 17 
-                                                      Connected to the RTC Alarm 
-                                                      event */
-#define EXTI_Line19      ((uint32_t)0x00080000)  /*!< Internal interrupt line 19
-                                                      Connected to the RTC Tamper
-                                                      and Time Stamp events */
-#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< Internal interrupt line 21
-                                                      Connected to the Comparator 1
-                                                      event */
-#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< Internal interrupt line 22
-                                                      Connected to the Comparator 2
-                                                      event */
-#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< Internal interrupt line 23
-                                                      Connected to the I2C1 wakeup
-                                                      event */
-#define EXTI_Line25      ((uint32_t)0x02000000)  /*!< Internal interrupt line 25
-                                                      Connected to the USART1 wakeup
-                                                      event */
-#define EXTI_Line27      ((uint32_t)0x08000000)  /*!< Internal interrupt line 27
-                                                      Connected to the CEC wakeup
-                                                      event */
-
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF5140000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
-                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
-                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
-                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
-                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
-                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
-                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
-                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
-                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
-                                ((LINE) == EXTI_Line19) || ((LINE) == EXTI_Line21) || \
-                                ((LINE) == EXTI_Line22))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_EXTI_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h

@@ -1,320 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_flash.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the FLASH 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_FLASH_H
-#define __STM32F0XX_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  FLASH Status
-  */ 
-typedef enum
-{
-  FLASH_BUSY = 1,
-  FLASH_ERROR_WRP,
-  FLASH_ERROR_PROGRAM,
-  FLASH_COMPLETE,
-  FLASH_TIMEOUT
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-  
-/** @defgroup FLASH_Exported_Constants
-  * @{
-  */ 
-  
-/** @defgroup FLASH_Latency 
-  * @{
-  */ 
-#define FLASH_Latency_0                ((uint32_t)0x00000000)  /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1                FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
-                                   ((LATENCY) == FLASH_Latency_1))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Interrupts 
-  * @{
-  */
-   
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE  /*!< End of programming interrupt source */
-#define FLASH_IT_ERR                   FLASH_CR_ERRIE  /*!< Error interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Address 
-  * @{
-  */
-  
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_DATA_ADDRESS 
-  * @{
-  */  
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) 
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_Write_Protection 
-  * @{
-  */
-  
-
-#define OB_WRP_Pages0to3               ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
-#define OB_WRP_Pages4to7               ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
-#define OB_WRP_Pages8to11              ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
-#define OB_WRP_Pages12to15             ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
-#define OB_WRP_Pages16to19             ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
-#define OB_WRP_Pages20to23             ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
-#define OB_WRP_Pages24to27             ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
-#define OB_WRP_Pages28to31             ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
-#define OB_WRP_Pages32to35             ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
-#define OB_WRP_Pages36to39             ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
-#define OB_WRP_Pages40to43             ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
-#define OB_WRP_Pages44to47             ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
-#define OB_WRP_Pages48to51             ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
-#define OB_WRP_Pages52to55             ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
-#define OB_WRP_Pages56to59             ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
-#define OB_WRP_Pages60to63             ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
-
-#define OB_WRP_AllPages                ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection 
-  * @{
-  */ 
-
-/** 
-  * @brief  FLASH_Read Protection Level  
-  */ 
-#define OB_RDP_Level_0   ((uint8_t)0xAA)
-#define OB_RDP_Level_1   ((uint8_t)0xBB)
-/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 
-                                                it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
-                          ((LEVEL) == OB_RDP_Level_1))/*||\
-                          ((LEVEL) == OB_RDP_Level_2))*/
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog 
-  * @{
-  */
-
-#define OB_IWDG_SW                     ((uint8_t)0x01)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP 
-  * @{
-  */
-
-#define OB_STOP_NoRST                  ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
-  * @{
-  */
-
-#define OB_STDBY_NoRST                 ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_BOOT1
-  * @{
-  */
-
-#define OB_BOOT1_RESET                 ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET                   ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
-  * @{
-  */
-
-#define OB_VDDA_ANALOG_ON              ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF             ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source OFF */
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-/**
-  * @}
-  */    
-
-/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable 
-  * @{
-  */
-
-#define OB_SRAM_PARITY_SET              ((uint8_t)0x00) /*!< SRAM parity enable Set */
-#define OB_SRAM_PARITY_RESET            ((uint8_t)0x40) /*!< SRAM parity enable reset */
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup FLASH_Flags 
-  * @{
-  */ 
-
-#define FLASH_FLAG_BSY                 FLASH_SR_BSY     /*!< FLASH Busy flag */
-#define FLASH_FLAG_PGERR               FLASH_SR_PGERR   /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR  /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_EOP                 FLASH_SR_EOP     /*!< FLASH End of Programming flag */
- 
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC3) == 0x00000000) && ((FLAG) != 0x00000000))
-
-#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
-                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Timeout_definition 
-  * @{
-  */ 
-#define FLASH_ER_PRG_TIMEOUT         ((uint32_t)0x000B0000)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-  
-/** 
-  * @brief  FLASH memory functions that can be executed from FLASH.  
-  */  
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-FlagStatus FLASH_GetPrefetchBufferStatus(void);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-/* FLASH Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_Launch(void);
-FLASH_Status FLASH_OB_Erase(void);
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-uint8_t FLASH_OB_GetUser(void);
-uint32_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-
-/* FLASH Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_FLASH_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h

@@ -1,350 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_gpio.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the GPIO 
-  *          firmware library. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_GPIO_H
-#define __STM32F0XX_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
-                                    ((PERIPH) == GPIOB) || \
-                                    ((PERIPH) == GPIOC) || \
-                                    ((PERIPH) == GPIOD) || \
-                                    ((PERIPH) == GPIOF))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
-                                     ((PERIPH) == GPIOB))
-
-/** @defgroup Configuration_Mode_enumeration 
-  * @{
-  */
-typedef enum
-{
-  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode              */
-  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode             */
-  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
-  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog In/Out Mode      */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
-                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
-  * @}
-  */
-
-/** @defgroup Output_type_enumeration
-  * @{
-  */
-typedef enum
-{
-  GPIO_OType_PP = 0x00,
-  GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
-  * @}
-  */
-
-/** @defgroup Output_Maximum_frequency_enumeration 
-  * @{
-  */
-typedef enum
-{
-  GPIO_Speed_Level_1  = 0x01, /*!< Medium Speed */
-  GPIO_Speed_Level_2  = 0x02, /*!< Fast Speed   */
-  GPIO_Speed_Level_3  = 0x03  /*!< High Speed   */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
-                              ((SPEED) == GPIO_Speed_Level_3))
-/**
-  * @}
-  */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration 
-  * @{
-  */
-typedef enum
-{
-  GPIO_PuPd_NOPULL = 0x00,
-  GPIO_PuPd_UP     = 0x01,
-  GPIO_PuPd_DOWN   = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
-                            ((PUPD) == GPIO_PuPd_DOWN))
-/**
-  * @}
-  */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
-  * @{
-  */
-typedef enum
-{ 
-  Bit_RESET = 0,
-  Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
-  * @}
-  */
-
-/**
-  * @brief  GPIO Init structure definition  
-  */
-typedef struct
-{
-  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
-                                       This parameter can be any value of @ref GPIO_pins_define */
-                                       
-  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
-                                       This parameter can be a value of @ref GPIOMode_TypeDef   */
-
-  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
-                                       This parameter can be a value of @ref GPIOSpeed_TypeDef  */
-
-  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
-                                       This parameter can be a value of @ref GPIOOType_TypeDef  */
-
-  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                                       This parameter can be a value of @ref GPIOPuPd_TypeDef   */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
-  * @{
-  */
-
-/** @defgroup GPIO_pins_define 
-  * @{
-  */
-#define GPIO_Pin_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected    */
-#define GPIO_Pin_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected    */
-#define GPIO_Pin_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected    */
-#define GPIO_Pin_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected    */
-#define GPIO_Pin_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected    */
-#define GPIO_Pin_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected    */
-#define GPIO_Pin_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected    */
-#define GPIO_Pin_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected    */
-#define GPIO_Pin_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected    */
-#define GPIO_Pin_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected    */
-#define GPIO_Pin_10                ((uint16_t)0x0400)  /*!< Pin 10 selected   */
-#define GPIO_Pin_11                ((uint16_t)0x0800)  /*!< Pin 11 selected   */
-#define GPIO_Pin_12                ((uint16_t)0x1000)  /*!< Pin 12 selected   */
-#define GPIO_Pin_13                ((uint16_t)0x2000)  /*!< Pin 13 selected   */
-#define GPIO_Pin_14                ((uint16_t)0x4000)  /*!< Pin 14 selected   */
-#define GPIO_Pin_15                ((uint16_t)0x8000)  /*!< Pin 15 selected   */
-#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
-                              ((PIN) == GPIO_Pin_1) || \
-                              ((PIN) == GPIO_Pin_2) || \
-                              ((PIN) == GPIO_Pin_3) || \
-                              ((PIN) == GPIO_Pin_4) || \
-                              ((PIN) == GPIO_Pin_5) || \
-                              ((PIN) == GPIO_Pin_6) || \
-                              ((PIN) == GPIO_Pin_7) || \
-                              ((PIN) == GPIO_Pin_8) || \
-                              ((PIN) == GPIO_Pin_9) || \
-                              ((PIN) == GPIO_Pin_10) || \
-                              ((PIN) == GPIO_Pin_11) || \
-                              ((PIN) == GPIO_Pin_12) || \
-                              ((PIN) == GPIO_Pin_13) || \
-                              ((PIN) == GPIO_Pin_14) || \
-                              ((PIN) == GPIO_Pin_15))
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Pin_sources 
-  * @{
-  */
-#define GPIO_PinSource0            ((uint8_t)0x00)
-#define GPIO_PinSource1            ((uint8_t)0x01)
-#define GPIO_PinSource2            ((uint8_t)0x02)
-#define GPIO_PinSource3            ((uint8_t)0x03)
-#define GPIO_PinSource4            ((uint8_t)0x04)
-#define GPIO_PinSource5            ((uint8_t)0x05)
-#define GPIO_PinSource6            ((uint8_t)0x06)
-#define GPIO_PinSource7            ((uint8_t)0x07)
-#define GPIO_PinSource8            ((uint8_t)0x08)
-#define GPIO_PinSource9            ((uint8_t)0x09)
-#define GPIO_PinSource10           ((uint8_t)0x0A)
-#define GPIO_PinSource11           ((uint8_t)0x0B)
-#define GPIO_PinSource12           ((uint8_t)0x0C)
-#define GPIO_PinSource13           ((uint8_t)0x0D)
-#define GPIO_PinSource14           ((uint8_t)0x0E)
-#define GPIO_PinSource15           ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
-                                       ((PINSOURCE) == GPIO_PinSource1) || \
-                                       ((PINSOURCE) == GPIO_PinSource2) || \
-                                       ((PINSOURCE) == GPIO_PinSource3) || \
-                                       ((PINSOURCE) == GPIO_PinSource4) || \
-                                       ((PINSOURCE) == GPIO_PinSource5) || \
-                                       ((PINSOURCE) == GPIO_PinSource6) || \
-                                       ((PINSOURCE) == GPIO_PinSource7) || \
-                                       ((PINSOURCE) == GPIO_PinSource8) || \
-                                       ((PINSOURCE) == GPIO_PinSource9) || \
-                                       ((PINSOURCE) == GPIO_PinSource10) || \
-                                       ((PINSOURCE) == GPIO_PinSource11) || \
-                                       ((PINSOURCE) == GPIO_PinSource12) || \
-                                       ((PINSOURCE) == GPIO_PinSource13) || \
-                                       ((PINSOURCE) == GPIO_PinSource14) || \
-                                       ((PINSOURCE) == GPIO_PinSource15))
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Alternate_function_selection_define 
-  * @{
-  */
-
-/** 
-  * @brief  AF 0 selection
-  */
-#define GPIO_AF_0            ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
-                                                MCO, SWDAT, SWCLK, TIM14, BOOT,
-                                                USART1, CEC, IR_OUT, SPI2 */
-/** 
-  * @brief  AF 1 selection
-  */
-#define GPIO_AF_1            ((uint8_t)0x01) /* USART2, CEC, Tim3, USART1, USART2,
-                                                EVENTOUT, I2C1, I2C2, TIM15 */
-/** 
-  * @brief  AF 2 selection
-  */
-#define GPIO_AF_2            ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17 */
-/** 
-  * @brief  AF 3 selection
-  */
-#define GPIO_AF_3            ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
-
-/** 
-  * @brief  AF 4 selection
-  */
-#define GPIO_AF_4            ((uint8_t)0x04) /* TIM14 */
-/** 
-  * @brief  AF 5 selection
-  */
-#define GPIO_AF_5            ((uint8_t)0x05) /* TIM16, TIM17 */
-
-/** 
-  * @brief  AF 6 selection
-  */
-#define GPIO_AF_6            ((uint8_t)0x06) /* EVENTOUT */
-/** 
-  * @brief  AF 7 selection
-  */
-#define GPIO_AF_7            ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
-
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
-                          ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
-                          ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
-                          ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Speed_Legacy 
-  * @{
-  */
-
-#define GPIO_Speed_10MHz GPIO_Speed_Level_1   /*!< Fast Speed:10MHz   */
-#define GPIO_Speed_2MHz  GPIO_Speed_Level_2   /*!< Medium Speed:2MHz  */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3   /*!< High Speed:50MHz   */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_GPIO_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h

@@ -1,478 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_i2c.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the I2C firmware
-  *          library
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_I2C_H
-#define __STM32F0XX_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  I2C Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t I2C_Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                         This parameter must be set by referring to I2C_Timing_Config_Tool*/
-
-  uint32_t I2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
-                                         This parameter can be a value of @ref I2C_Analog_Filter*/
-
-  uint32_t I2C_DigitalFilter;       /*!< Configures the digital noise filter.
-                                         This parameter can be a number between 0x00 and 0x0F*/
-
-  uint32_t I2C_Mode;                /*!< Specifies the I2C mode.
-                                         This parameter can be a value of @ref I2C_mode*/
-
-  uint32_t I2C_OwnAddress1;         /*!< Specifies the device own address 1.
-                                         This parameter can be a 7-bit or 10-bit address*/
-
-  uint32_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
-                                         This parameter can be a value of @ref I2C_acknowledgement*/
-
-  uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
-                                         This parameter can be a value of @ref I2C_acknowledged_address*/
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
-  * @{
-  */
-
-#define IS_I2C_ALL_PERIPH(PERIPH)       (((PERIPH) == I2C1) || \
-                                         ((PERIPH) == I2C2))
-                                         
-#define IS_I2C_1_PERIPH(PERIPH)         ((PERIPH) == I2C1) 
-
-/** @defgroup I2C_Analog_Filter 
-  * @{
-  */
-
-#define I2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
-#define I2C_AnalogFilter_Disable        I2C_CR1_ANFOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_AnalogFilter_Enable) || \
-                                         ((FILTER) == I2C_AnalogFilter_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Digital_Filter
-  * @{
-  */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_mode 
-  * @{
-  */
-
-#define I2C_Mode_I2C                    ((uint32_t)0x00000000)
-#define I2C_Mode_SMBusDevice            I2C_CR1_SMBDEN
-#define I2C_Mode_SMBusHost              I2C_CR1_SMBHEN
-
-#define IS_I2C_MODE(MODE)               (((MODE) == I2C_Mode_I2C) || \
-                                         ((MODE) == I2C_Mode_SMBusDevice) || \
-                                         ((MODE) == I2C_Mode_SMBusHost))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_acknowledgement
-  * @{
-  */
-
-#define I2C_Ack_Enable                  ((uint32_t)0x00000000)
-#define I2C_Ack_Disable                 I2C_CR2_NACK
-
-#define IS_I2C_ACK(ACK)                 (((ACK) == I2C_Ack_Enable) || \
-                                         ((ACK) == I2C_Ack_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_acknowledged_address
-  * @{
-  */
-
-#define I2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
-#define I2C_AcknowledgedAddress_10bit   I2C_OAR1_OA1MODE
-
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
-                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_own_address1
-  * @{
-  */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_transfer_direction 
-  * @{
-  */
-
-#define I2C_Direction_Transmitter       ((uint16_t)0x0000)
-#define I2C_Direction_Receiver          ((uint16_t)0x0400)
-
-#define IS_I2C_DIRECTION(DIRECTION)     (((DIRECTION) == I2C_Direction_Transmitter) || \
-                                         ((DIRECTION) == I2C_Direction_Receiver))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_DMA_transfer_requests 
-  * @{
-  */
-
-#define I2C_DMAReq_Tx                   I2C_CR1_TXDMAEN
-#define I2C_DMAReq_Rx                   I2C_CR1_RXDMAEN
-
-#define IS_I2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_slave_address
-  * @{
-  */
-
-#define IS_I2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
-/**
-  * @}
-  */
-
-
-/** @defgroup I2C_own_address2
-  * @{
-  */
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_own_address2_mask
-  * @{
-  */
-
-#define I2C_OA2_NoMask                  ((uint8_t)0x00)
-#define I2C_OA2_Mask01                  ((uint8_t)0x01)                 
-#define I2C_OA2_Mask02                  ((uint8_t)0x02)
-#define I2C_OA2_Mask03                  ((uint8_t)0x03)
-#define I2C_OA2_Mask04                  ((uint8_t)0x04)
-#define I2C_OA2_Mask05                  ((uint8_t)0x05)
-#define I2C_OA2_Mask06                  ((uint8_t)0x06)
-#define I2C_OA2_Mask07                  ((uint8_t)0x07)
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NoMask) || \
-                                         ((MASK) == I2C_OA2_Mask01) || \
-                                         ((MASK) == I2C_OA2_Mask02) || \
-                                         ((MASK) == I2C_OA2_Mask03) || \
-                                         ((MASK) == I2C_OA2_Mask04) || \
-                                         ((MASK) == I2C_OA2_Mask05) || \
-                                         ((MASK) == I2C_OA2_Mask06) || \
-                                         ((MASK) == I2C_OA2_Mask07))  
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_timeout
-  * @{
-  */
-
-#define IS_I2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_registers 
-  * @{
-  */
-
-#define I2C_Register_CR1                ((uint8_t)0x00)
-#define I2C_Register_CR2                ((uint8_t)0x04)
-#define I2C_Register_OAR1               ((uint8_t)0x08)
-#define I2C_Register_OAR2               ((uint8_t)0x0C)
-#define I2C_Register_TIMINGR            ((uint8_t)0x10)
-#define I2C_Register_TIMEOUTR           ((uint8_t)0x14)
-#define I2C_Register_ISR                ((uint8_t)0x18)
-#define I2C_Register_ICR                ((uint8_t)0x1C)
-#define I2C_Register_PECR               ((uint8_t)0x20)
-#define I2C_Register_RXDR               ((uint8_t)0x24)
-#define I2C_Register_TXDR               ((uint8_t)0x28)
-
-#define IS_I2C_REGISTER(REGISTER)       (((REGISTER) == I2C_Register_CR1) || \
-                                         ((REGISTER) == I2C_Register_CR2) || \
-                                         ((REGISTER) == I2C_Register_OAR1) || \
-                                         ((REGISTER) == I2C_Register_OAR2) || \
-                                         ((REGISTER) == I2C_Register_TIMINGR) || \
-                                         ((REGISTER) == I2C_Register_TIMEOUTR) || \
-                                         ((REGISTER) == I2C_Register_ISR) || \
-                                         ((REGISTER) == I2C_Register_ICR) || \
-                                         ((REGISTER) == I2C_Register_PECR) || \
-                                         ((REGISTER) == I2C_Register_RXDR) || \
-                                         ((REGISTER) == I2C_Register_TXDR))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_interrupts_definition 
-  * @{
-  */
-
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE
-#define I2C_IT_TCI                      I2C_CR1_TCIE
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
-#define I2C_IT_RXI                      I2C_CR1_RXIE
-#define I2C_IT_TXI                      I2C_CR1_TXIE
-
-#define IS_I2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_flags_definition 
-  * @{
-  */
-
-#define  I2C_FLAG_TXE                   I2C_ISR_TXE
-#define  I2C_FLAG_TXIS                  I2C_ISR_TXIS
-#define  I2C_FLAG_RXNE                  I2C_ISR_RXNE
-#define  I2C_FLAG_ADDR                  I2C_ISR_ADDR
-#define  I2C_FLAG_NACKF                 I2C_ISR_NACKF
-#define  I2C_FLAG_STOPF                 I2C_ISR_STOPF
-#define  I2C_FLAG_TC                    I2C_ISR_TC
-#define  I2C_FLAG_TCR                   I2C_ISR_TCR
-#define  I2C_FLAG_BERR                  I2C_ISR_BERR
-#define  I2C_FLAG_ARLO                  I2C_ISR_ARLO
-#define  I2C_FLAG_OVR                   I2C_ISR_OVR
-#define  I2C_FLAG_PECERR                I2C_ISR_PECERR
-#define  I2C_FLAG_TIMEOUT               I2C_ISR_TIMEOUT
-#define  I2C_FLAG_ALERT                 I2C_ISR_ALERT
-#define  I2C_FLAG_BUSY                  I2C_ISR_BUSY
-
-#define IS_I2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_I2C_GET_FLAG(FLAG)           (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
-                                         ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
-                                         ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
-                                         ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
-                                         ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
-                                         ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
-                                         ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
-                                         ((FLAG) == I2C_FLAG_BUSY))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup I2C_interrupts_definition 
-  * @{
-  */
-
-#define  I2C_IT_TXIS                    I2C_ISR_TXIS
-#define  I2C_IT_RXNE                    I2C_ISR_RXNE
-#define  I2C_IT_ADDR                    I2C_ISR_ADDR
-#define  I2C_IT_NACKF                   I2C_ISR_NACKF
-#define  I2C_IT_STOPF                   I2C_ISR_STOPF
-#define  I2C_IT_TC                      I2C_ISR_TC
-#define  I2C_IT_TCR                     I2C_ISR_TCR
-#define  I2C_IT_BERR                    I2C_ISR_BERR
-#define  I2C_IT_ARLO                    I2C_ISR_ARLO
-#define  I2C_IT_OVR                     I2C_ISR_OVR
-#define  I2C_IT_PECERR                  I2C_ISR_PECERR
-#define  I2C_IT_TIMEOUT                 I2C_ISR_TIMEOUT
-#define  I2C_IT_ALERT                   I2C_ISR_ALERT
-
-#define IS_I2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-                               
-#define IS_I2C_GET_IT(IT)               (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
-                                         ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
-                                         ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
-                                         ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
-                                         ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
-                                         ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
-                                         ((IT) == I2C_IT_ALERT))
-                               
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ReloadEndMode_definition 
-  * @{
-  */
-
-#define  I2C_Reload_Mode                I2C_CR2_RELOAD
-#define  I2C_AutoEnd_Mode               I2C_CR2_AUTOEND
-#define  I2C_SoftEnd_Mode               ((uint32_t)0x00000000)
-
-                              
-#define IS_RELOAD_END_MODE(MODE)        (((MODE) == I2C_Reload_Mode) || \
-                                         ((MODE) == I2C_AutoEnd_Mode) || \
-                                         ((MODE) == I2C_SoftEnd_Mode))
-                               
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_StartStopMode_definition 
-  * @{
-  */
-
-#define  I2C_No_StartStop                 ((uint32_t)0x00000000)
-#define  I2C_Generate_Stop                I2C_CR2_STOP
-#define  I2C_Generate_Start_Read          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  I2C_Generate_Start_Write         I2C_CR2_START
-
-                              
-#define IS_START_STOP_MODE(MODE)        (((MODE) == I2C_Generate_Stop) || \
-                                         ((MODE) == I2C_Generate_Start_Read) || \
-                                         ((MODE) == I2C_Generate_Start_Write) || \
-                                         ((MODE) == I2C_No_StartStop))
-                               
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/*  SMBUS management functions ************************************************/
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* I2C registers management functions *****************************************/
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-
-/* Data transfers management functions ****************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_I2C_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h

@@ -1,140 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_iwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the IWDG 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_IWDG_H
-#define __STM32F0XX_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup IWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
-  * @{
-  */
-
-/** @defgroup IWDG_WriteAccess
-  * @{
-  */
-
-#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
-                                      ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_prescaler 
-  * @{
-  */
-
-#define IWDG_Prescaler_4            ((uint8_t)0x00)
-#define IWDG_Prescaler_8            ((uint8_t)0x01)
-#define IWDG_Prescaler_16           ((uint8_t)0x02)
-#define IWDG_Prescaler_32           ((uint8_t)0x03)
-#define IWDG_Prescaler_64           ((uint8_t)0x04)
-#define IWDG_Prescaler_128          ((uint8_t)0x05)
-#define IWDG_Prescaler_256          ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
-                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
-                                      ((PRESCALER) == IWDG_Prescaler_16) || \
-                                      ((PRESCALER) == IWDG_Prescaler_32) || \
-                                      ((PRESCALER) == IWDG_Prescaler_64) || \
-                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
-                                      ((PRESCALER) == IWDG_Prescaler_256))
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag 
-  * @{
-  */
-
-#define IWDG_FLAG_PVU               IWDG_SR_PVU
-#define IWDG_FLAG_RVU               IWDG_SR_RVU
-#define IWDG_FLAG_WVU               IWDG_SR_WVU
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)  || \
-                            ((FLAG) == IWDG_FLAG_WVU))
-
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
-#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-void IWDG_SetWindowValue(uint16_t WindowValue);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_IWDG_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h

@@ -1,143 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_misc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the miscellaneous
-  *          firmware library functions (add-on to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_MISC_H
-#define __STM32F0XX_MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  NVIC Init Structure definition  
-  */
-
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;             /*!< Specifies the IRQ channel to be enabled or disabled.
-                                            This parameter can be a value of @ref IRQn_Type 
-                                            (For the complete STM32 Devices IRQ Channels list, 
-                                            please refer to stm32f0xx.h file) */
-
-  uint8_t NVIC_IRQChannelPriority;     /*!< Specifies the priority level for the IRQ channel specified
-                                            in NVIC_IRQChannel. This parameter can be a value
-                                            between 0 and 3.  */
-
-  FunctionalState NVIC_IRQChannelCmd;  /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                            will be enabled or disabled. 
-                                            This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
-
-/**  
-  *
-@verbatim   
-
-@endverbatim
-*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup MISC_System_Low_Power 
-  * @{
-  */
-
-#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Preemption_Priority_Group 
-  * @{
-  */
-#define IS_NVIC_PRIORITY(PRIORITY)  ((PRIORITY) < 0x04)
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_SysTick_clock_source 
-  * @{
-  */
-
-#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
-                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */ 
-
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_MISC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h

@@ -1,186 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_pwr.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the PWR firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_PWR_H
-#define __STM32F0XX_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup PWR_PVD_detection_level 
-  * @{
-  */ 
-
-#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7 
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
-                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
-                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
-                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_WakeUp_Pins 
-  * @{
-  */
-
-#define PWR_WakeUpPin_1                 PWR_CSR_EWUP1
-#define PWR_WakeUpPin_2                 PWR_CSR_EWUP2
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
-                                ((PIN) == PWR_WakeUpPin_2))
-/**
-  * @}
-  */
-
- 
-/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode 
-  * @{
-  */
-
-#define PWR_Regulator_ON                ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower          PWR_CR_LPSDSR
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
-                                     ((REGULATOR) == PWR_Regulator_LowPower))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry 
-  * @{
-  */
-
-#define PWR_SLEEPEntry_WFI              ((uint8_t)0x01)
-#define PWR_SLEEPEntry_WFE              ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
- 
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry 
-  * @{
-  */
-
-#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
- 
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag 
-  * @{
-  */
-
-#define PWR_FLAG_WU                     PWR_CSR_WUF
-#define PWR_FLAG_SB                     PWR_CSR_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
-#define PWR_FLAG_VREFINTRDY             PWR_CSR_VREFINTRDYF
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
-                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_PVDCmd(FunctionalState NewState);
-
-/* WakeUp pins configuration functions ****************************************/
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_PWR_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h

@@ -1,523 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_rcc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the RCC 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RCC_H
-#define __STM32F0XX_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;
-  uint32_t HCLK_Frequency;
-  uint32_t PCLK_Frequency;
-  uint32_t ADCCLK_Frequency;
-  uint32_t CECCLK_Frequency;
-  uint32_t I2C1CLK_Frequency;
-  uint32_t USART1CLK_Frequency;
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup RCC_HSE_configuration 
-  * @{
-  */
-
-#define RCC_HSE_OFF                      ((uint8_t)0x00)
-#define RCC_HSE_ON                       ((uint8_t)0x01)
-#define RCC_HSE_Bypass                   ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_Bypass))
-
-/**
-  * @}
-  */ 
- 
-/** @defgroup RCC_PLL_Clock_Source 
-  * @{
-  */
-
-#define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
-#define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_PREDIV1
- 
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
-                                   ((SOURCE) == RCC_PLLSource_PREDIV1))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_PLL_Multiplication_Factor 
-  * @{
-  */
-
-#define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
-#define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
-#define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
-#define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
-#define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
-#define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
-#define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
-#define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
-#define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
-#define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
-#define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
-#define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
-#define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
-#define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
-#define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
-                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
-                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
-                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
-                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
-                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
-                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
-                             ((MUL) == RCC_PLLMul_16))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PREDIV1_division_factor
-  * @{
-  */
-#define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
-#define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
-#define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
-#define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
-#define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
-#define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
-#define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
-#define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
-#define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
-#define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
-#define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
-#define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
-#define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
-#define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
-#define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
-#define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
-
-#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
-                                 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-/**
-  * @}
-  */
- 
-/** @defgroup RCC_System_Clock_Source 
-  * @{
-  */
-
-#define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
-                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source
-  * @{
-  */
-
-#define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
-                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
-                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
-                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
-                           ((HCLK) == RCC_SYSCLK_Div512))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_APB_Clock_Source
-  * @{
-  */
-
-#define RCC_HCLK_Div1                    RCC_CFGR_PPRE_DIV1
-#define RCC_HCLK_Div2                    RCC_CFGR_PPRE_DIV2
-#define RCC_HCLK_Div4                    RCC_CFGR_PPRE_DIV4
-#define RCC_HCLK_Div8                    RCC_CFGR_PPRE_DIV8
-#define RCC_HCLK_Div16                   RCC_CFGR_PPRE_DIV16
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
-                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
-                           ((PCLK) == RCC_HCLK_Div16))
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_ADC_clock_source 
-  * @{
-  */
-
-#define RCC_ADCCLK_HSI14                 ((uint32_t)0x00000000)
-#define RCC_ADCCLK_PCLK_Div2             ((uint32_t)0x01000000)
-#define RCC_ADCCLK_PCLK_Div4             ((uint32_t)0x01004000)
-
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
-                               ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_CEC_clock_source 
-  * @{
-  */
-
-#define RCC_CECCLK_HSI_Div244            ((uint32_t)0x00000000)
-#define RCC_CECCLK_LSE                   RCC_CFGR3_CECSW
-
-#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_I2C_clock_source 
-  * @{
-  */
-
-#define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
-#define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
-
-#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_USART_clock_source 
-  * @{
-  */
-
-#define RCC_USART1CLK_PCLK                 ((uint32_t)0x00000000)
-#define RCC_USART1CLK_SYSCLK               RCC_CFGR3_USART1SW_0
-#define RCC_USART1CLK_LSE                  RCC_CFGR3_USART1SW_1
-#define RCC_USART1CLK_HSI                  RCC_CFGR3_USART1SW
-
-#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
-                                   ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI))
-
-/**
-  * @}
-  */
-       
-/** @defgroup RCC_Interrupt_Source 
-  * @{
-  */
-
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
-#define RCC_IT_HSI14RDY                  ((uint8_t)0x20)
-#define RCC_IT_CSS                       ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
-                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
-                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
-                           ((IT) == RCC_IT_CSS))
-
-#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
-
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_LSE_Configuration 
-  * @{
-  */
-
-#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
-#define RCC_LSE_ON                       RCC_BDCR_LSEON
-#define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_Bypass))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source
-  * @{
-  */
-
-#define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
-                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Drive_Configuration 
-  * @{
-  */
-
-#define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
-#define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
-#define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
-#define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
-                                 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_AHB_Peripherals 
-  * @{
-  */
-
-#define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
-#define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
-#define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
-#define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Peripherals 
-  * @{
-  */
-
-#define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_ADC1              RCC_APB2ENR_ADC1EN
-#define RCC_APB2Periph_TIM1              RCC_APB2ENR_TIM1EN
-#define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
-#define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
-#define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
-#define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
-#define RCC_APB2Periph_DBGMCU            RCC_APB2ENR_DBGMCUEN
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_APB1_Peripherals 
-  * @{
-  */
-
-#define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
-#define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM14             RCC_APB1ENR_TIM14EN
-#define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC               RCC_APB1ENR_DACEN
-#define RCC_APB1Periph_CEC               RCC_APB1ENR_CECEN
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Clock_Source
-  * @{
-  */
-
-#define RCC_MCOSource_NoClock            ((uint8_t)0x00)
-#define RCC_MCOSource_HSI14              ((uint8_t)0x01)
-#define RCC_MCOSource_LSI                ((uint8_t)0x02)
-#define RCC_MCOSource_LSE                ((uint8_t)0x03)
-#define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
-#define RCC_MCOSource_HSI                ((uint8_t)0x05)
-#define RCC_MCOSource_HSE                ((uint8_t)0x06)
-#define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
-                                   ((SOURCE) == RCC_MCOSource_SYSCLK)  || ((SOURCE) == RCC_MCOSource_HSI)  || \
-                                   ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
-                                   ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Flag 
-  * @{
-  */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
-#define RCC_FLAG_V18PWRRSTF              ((uint8_t)0x57)
-#define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
-#define RCC_FLAG_HSI14RDY                ((uint8_t)0x61)
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)  || ((FLAG) == RCC_FLAG_HSERDY) || \
-                           ((FLAG) == RCC_FLAG_PLLRDY)  || ((FLAG) == RCC_FLAG_LSERDY) || \
-                           ((FLAG) == RCC_FLAG_LSIRDY)  || ((FLAG) == RCC_FLAG_OBLRST) || \
-                           ((FLAG) == RCC_FLAG_PINRST)  || ((FLAG) == RCC_FLAG_PORRST) || \
-                           ((FLAG) == RCC_FLAG_SFTRST)  || ((FLAG) == RCC_FLAG_IWDGRST)|| \
-                           ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
-                           ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_V18PWRRSTF))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
-void RCC_HSI14Cmd(FunctionalState NewState);
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-void RCC_MCOConfig(uint8_t RCC_MCOSource);
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLKConfig(uint32_t RCC_HCLK);
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK);
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_RCC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h

@@ -1,772 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_rtc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the RTC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RTC_H
-#define __STM32F0XX_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  RTC Init structures definition  
-  */ 
-typedef struct
-{
-  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
-                             This parameter can be a value of @ref RTC_Hour_Formats */
-  
-  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
-                             This parameter must be set to a value lower than 0x7F */
-  
-  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
-                             This parameter must be set to a value lower than 0x1FFF */
-}RTC_InitTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
-                        This parameter must be set to a value in the 0-12 range
-                        if the RTC_HourFormat_12 is selected or 0-23 range if
-                        the RTC_HourFormat_24 is selected. */
-
-  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
-                        This parameter must be set to a value in the 0-59 range. */
-  
-  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
-                        This parameter must be set to a value in the 0-59 range. */
-
-  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
-                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef; 
-
-/** 
-  * @brief  RTC Date structure definition  
-  */
-typedef struct
-{
-  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
-                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
-  
-  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month.
-                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
-                        This parameter must be set to a value in the 1-31 range. */
-  
-  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
-                        This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  RTC Alarm structure definition  
-  */
-typedef struct
-{
-  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
-
-  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-  
-  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                     This parameter must be set to a value in the 1-31 range 
-                                     if the Alarm Date is selected.
-                                     This parameter can be a value of @ref RTC_WeekDay_Definitions 
-                                     if the Alarm WeekDay is selected. */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
-  * @{
-  */ 
-
-
-/** @defgroup RTC_Hour_Formats 
-  * @{
-  */ 
-#define RTC_HourFormat_24              ((uint32_t)0x00000000)
-#define RTC_HourFormat_12              ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
-                                        ((FORMAT) == RTC_HourFormat_24))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Asynchronous_Predivider 
-  * @{
-  */ 
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Synchronous_Predivider 
-  * @{
-  */ 
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Time_Definitions 
-  * @{
-  */ 
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AM_PM_Definitions 
-  * @{
-  */ 
-#define RTC_H12_AM                     ((uint8_t)0x00)
-#define RTC_H12_PM                     ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Year_Date_Definitions 
-  * @{
-  */ 
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Month_Date_Definitions 
-  * @{
-  */ 
-#define RTC_Month_January              ((uint8_t)0x01)
-#define RTC_Month_February             ((uint8_t)0x02)
-#define RTC_Month_March                ((uint8_t)0x03)
-#define RTC_Month_April                ((uint8_t)0x04)
-#define RTC_Month_May                  ((uint8_t)0x05)
-#define RTC_Month_June                 ((uint8_t)0x06)
-#define RTC_Month_July                 ((uint8_t)0x07)
-#define RTC_Month_August               ((uint8_t)0x08)
-#define RTC_Month_September            ((uint8_t)0x09)
-#define RTC_Month_October              ((uint8_t)0x10)
-#define RTC_Month_November             ((uint8_t)0x11)
-#define RTC_Month_December             ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_WeekDay_Definitions 
-  * @{
-  */ 
-  
-#define	RTC_Weekday_Monday             ((uint8_t)0x01)
-#define	RTC_Weekday_Tuesday            ((uint8_t)0x02)
-#define	RTC_Weekday_Wednesday          ((uint8_t)0x03)
-#define	RTC_Weekday_Thursday           ((uint8_t)0x04)
-#define	RTC_Weekday_Friday             ((uint8_t)0x05)
-#define	RTC_Weekday_Saturday           ((uint8_t)0x6)
-#define	RTC_Weekday_Sunday             ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Alarm_Definitions 
-  * @{
-  */ 
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions 
-  * @{
-  */ 
-#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)  
-#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)  
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
-                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmMask_Definitions 
-  * @{
-  */ 
-#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)  
-#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarms_Definitions 
-  * @{
-  */ 
-#define RTC_Alarm_A                       ((uint32_t)0x00000100)
-#define IS_RTC_ALARM(ALARM)      ((ALARM) == RTC_Alarm_A)
-#define IS_RTC_CMD_ALARM(ALARM)  (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
-  * @{
-  */ 
-#define RTC_AlarmSubSecondMask_All         ((uint8_t)0x00) /*!< All Alarm SS fields are masked. 
-                                                                There is no comparison on sub seconds 
-                                                                for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1      ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm 
-                                                                comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2      ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm 
-                                                                comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3      ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm 
-                                                                comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4      ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm 
-                                                                comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5      ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm 
-                                                                comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6      ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm 
-                                                                comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7      ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm 
-                                                                comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8      ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm 
-                                                                comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9      ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm 
-                                                                comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10     ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm 
-                                                                comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11     ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm 
-                                                                comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12     ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm 
-                                                                comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13     ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm 
-                                                                comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14        ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm 
-                                                                comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None        ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match 
-                                                                to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
-  * @{
-  */ 
-  
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions 
-  * @{
-  */ 
-#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
-                                     ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_selection_Definitions 
-  * @{
-  */ 
-#define RTC_Output_Disable             ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
- 
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
-                               ((OUTPUT) == RTC_Output_AlarmA))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Polarity_Definitions 
-  * @{
-  */ 
-#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
-                                ((POL) == RTC_OutputPolarity_Low))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Calib_Output_selection_Definitions 
-  * @{
-  */ 
-#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
-#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
-                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_period_Definitions 
-  * @{
-  */ 
-#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
-                                                             period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
-                                                             period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
-                                                             period is 8s, else 2exp18 RTCCLK seconds */
-#define  IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
-                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
-                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-                                          
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
-  * @{
-  */ 
-#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
-                                                                during a X -second window = Y - CALM[8:0]. 
-                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
-                                                                 during a 32-second window =   CALM[8:0]. */
-#define  IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
-                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
-  * @{
-  */ 
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_DayLightSaving_Definitions 
-  * @{
-  */ 
-#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
-                                        ((SAVING) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
-                                           ((OPERATION) == RTC_StoreOperation_Set))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Trigger_Definitions 
-  * @{
-  */ 
-#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Filter_Definitions 
-  * @{
-  */ 
-#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
-                                                          consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
-                                                          consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
-                                                          consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
-                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
-                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
-                                      ((FILTER) == RTC_TamperFilter_8Sample))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
-  * @{
-  */ 
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192  ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 8192  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096  ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 4096  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048  ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 2048  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024  ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 1024  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512   ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 512   */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256   ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
-                                                                      with a frequency =  RTCCLK / 256   */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-                                           
-/**
-  * @}
-  */
-
-  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
-  * @{
-  */ 
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Tamper_Pins_Definitions 
-  * @{
-  */ 
-#define RTC_Tamper_1            RTC_TAFCR_TAMP1E /*!< Tamper detection enable for 
-                                                 input tamper 1 */
-#define RTC_Tamper_2            RTC_TAFCR_TAMP2E /*!< Tamper detection enable for 
-                                                 input tamper 2 */
-#define RTC_Tamper_3            RTC_TAFCR_TAMP3E /*!< Tamper detection enable for 
-                                                 input tamper 3 */
-
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT 
-  * @{
-  */ 
-#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
-                                  ((TYPE) == RTC_OutputType_PushPull))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
-  * @{
-  */ 
-#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
-                                 ((SEL) == RTC_ShiftAdd1S_Set))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
-  * @{
-  */ 
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Backup_Registers_Definitions 
-  * @{
-  */
-
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
-                                           ((BKP) == RTC_BKP_DR1) || \
-                                           ((BKP) == RTC_BKP_DR2) || \
-                                           ((BKP) == RTC_BKP_DR3) || \
-                                           ((BKP) == RTC_BKP_DR4)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Input_parameter_format_definitions 
-  * @{
-  */ 
-#define RTC_Format_BIN                    ((uint32_t)0x000000000)
-#define RTC_Format_BCD                    ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Flags_Definitions 
-  * @{
-  */ 
-#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
-#define RTC_FLAG_TAMP3F                   ((uint32_t)0x00008000)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
-#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
-#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
-#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
-
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP3F) || \
-                               ((FLAG) == RTC_FLAG_TAMP2F)  || ((FLAG) == RTC_FLAG_TAMP1F) || \
-                               ((FLAG) == RTC_FLAG_TSOVF)   || ((FLAG) == RTC_FLAG_TSF)    || \
-                               ((FLAG) == RTC_FLAG_ALRAF)   || ((FLAG) == RTC_FLAG_INITF)  || \
-                               ((FLAG) == RTC_FLAG_RSF)     || ((FLAG) == RTC_FLAG_INITS)  || \
-                               ((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF06DF) == (uint32_t)RESET))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Interrupts_Definitions 
-  * @{
-  */ 
-#define RTC_IT_TS                         ((uint32_t)0x00008000)
-#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
-#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF6FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS)    || ((IT) == RTC_IT_ALRA)  || \
-                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
-                           ((IT) == RTC_IT_TAMP3))                           
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF16FFF) == (uint32_t)RESET))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/*  Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A) configuration functions  **********************************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions ********************************/
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
-                                  uint32_t RTC_SmoothCalibPlusPulses,
-                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* Output Type Config configuration functions *********************************/
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
- 
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_RTC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h

@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_spi.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the SPI 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SPI_H
-#define __STM32F0XX_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  SPI Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
-                                         This parameter can be a value of @ref SPI_data_direction */
-
-  uint16_t SPI_Mode;                /*!< Specifies the SPI mode (Master/Slave).
-                                         This parameter can be a value of @ref SPI_mode */
-  
-  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
-                                         This parameter can be a value of @ref SPI_data_size */
-
-  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
-                                         This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
-                                         This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                         hardware (NSS pin) or by software using the SSI bit.
-                                         This parameter can be a value of @ref SPI_Slave_Select_management */
- 
-  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                         used to configure the transmit and receive SCK clock.
-                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                         @note The communication clock is derived from the master
-                                               clock. The slave clock does not need to be set. */
-
-  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-
-/** 
-  * @brief  I2S Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
-                                  This parameter can be a value of @ref SPI_I2S_Mode */
-
-  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
-                                  This parameter can be a value of @ref SPI_I2S_Standard */
-
-  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
-                                  This parameter can be a value of @ref SPI_I2S_Data_Format */
-
-  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                  This parameter can be a value of @ref SPI_I2S_MCLK_Output */
-
-  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                                  This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
-
-  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
-                                  This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
-  * @{
-  */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
-                                   ((PERIPH) == SPI2))
-
-#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
-
-/** @defgroup SPI_data_direction 
-  * @{
-  */
-  
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
-                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
-                                     ((MODE) == SPI_Direction_1Line_Rx) || \
-                                     ((MODE) == SPI_Direction_1Line_Tx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_mode 
-  * @{
-  */
-
-#define SPI_Mode_Master                 ((uint16_t)0x0104)
-#define SPI_Mode_Slave                  ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
-                           ((MODE) == SPI_Mode_Slave))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_data_size
-  * @{
-  */
-
-#define SPI_DataSize_4b                 ((uint16_t)0x0300)
-#define SPI_DataSize_5b                 ((uint16_t)0x0400)
-#define SPI_DataSize_6b                 ((uint16_t)0x0500)
-#define SPI_DataSize_7b                 ((uint16_t)0x0600)
-#define SPI_DataSize_8b                 ((uint16_t)0x0700)
-#define SPI_DataSize_9b                 ((uint16_t)0x0800)
-#define SPI_DataSize_10b                ((uint16_t)0x0900)
-#define SPI_DataSize_11b                ((uint16_t)0x0A00)
-#define SPI_DataSize_12b                ((uint16_t)0x0B00)
-#define SPI_DataSize_13b                ((uint16_t)0x0C00)
-#define SPI_DataSize_14b                ((uint16_t)0x0D00)
-#define SPI_DataSize_15b                ((uint16_t)0x0E00)
-#define SPI_DataSize_16b                ((uint16_t)0x0F00)
-#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
-                                 ((SIZE) == SPI_DataSize_5b) || \
-                                 ((SIZE) == SPI_DataSize_6b) || \
-                                 ((SIZE) == SPI_DataSize_7b) || \
-                                 ((SIZE) == SPI_DataSize_8b) || \
-                                 ((SIZE) == SPI_DataSize_9b) || \
-                                 ((SIZE) == SPI_DataSize_10b) || \
-                                 ((SIZE) == SPI_DataSize_11b) || \
-                                 ((SIZE) == SPI_DataSize_12b) || \
-                                 ((SIZE) == SPI_DataSize_13b) || \
-                                 ((SIZE) == SPI_DataSize_14b) || \
-                                 ((SIZE) == SPI_DataSize_15b) || \
-                                 ((SIZE) == SPI_DataSize_16b))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_length
-  * @{
-  */
-
-#define SPI_CRCLength_8b                ((uint16_t)0x0000)
-#define SPI_CRCLength_16b               SPI_CR1_CRCL
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
-                                   ((LENGTH) == SPI_CRCLength_16b))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity 
-  * @{
-  */
-
-#define SPI_CPOL_Low                    ((uint16_t)0x0000)
-#define SPI_CPOL_High                   SPI_CR1_CPOL
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
-                           ((CPOL) == SPI_CPOL_High))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase 
-  * @{
-  */
-
-#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge                  SPI_CR1_CPHA
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
-                           ((CPHA) == SPI_CPHA_2Edge))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management 
-  * @{
-  */
-
-#define SPI_NSS_Soft                    SPI_CR1_SSM
-#define SPI_NSS_Hard                    ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
-                         ((NSS) == SPI_NSS_Hard))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler 
-  * @{
-  */
-
-#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
-                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission 
-  * @{
-  */
-
-#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB                SPI_CR1_LSBFIRST
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
-                               ((BIT) == SPI_FirstBit_LSB))
-/**
-  * @}
-  */
-  
-/** @defgroup SPI_I2S_Mode 
-  * @{
-  */
-
-#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
-                           ((MODE) == I2S_Mode_SlaveRx) || \
-                           ((MODE) == I2S_Mode_MasterTx)|| \
-                           ((MODE) == I2S_Mode_MasterRx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_Standard 
-  * @{
-  */
-
-#define I2S_Standard_Phillips           ((uint16_t)0x0000)
-#define I2S_Standard_MSB                ((uint16_t)0x0010)
-#define I2S_Standard_LSB                ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
-                                   ((STANDARD) == I2S_Standard_MSB) || \
-                                   ((STANDARD) == I2S_Standard_LSB) || \
-                                   ((STANDARD) == I2S_Standard_PCMShort) || \
-                                   ((STANDARD) == I2S_Standard_PCMLong))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_Data_Format 
-  * @{
-  */
-
-#define I2S_DataFormat_16b              ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
-#define I2S_DataFormat_24b              ((uint16_t)0x0003)
-#define I2S_DataFormat_32b              ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
-                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
-                                    ((FORMAT) == I2S_DataFormat_24b) || \
-                                    ((FORMAT) == I2S_DataFormat_32b))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_MCLK_Output 
-  * @{
-  */
-
-#define I2S_MCLKOutput_Enable           SPI_I2SPR_MCKOE
-#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
-                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_Audio_Frequency 
-  * @{
-  */
-
-#define I2S_AudioFreq_192k               ((uint32_t)192000)
-#define I2S_AudioFreq_96k                ((uint32_t)96000)
-#define I2S_AudioFreq_48k                ((uint32_t)48000)
-#define I2S_AudioFreq_44k                ((uint32_t)44100)
-#define I2S_AudioFreq_32k                ((uint32_t)32000)
-#define I2S_AudioFreq_22k                ((uint32_t)22050)
-#define I2S_AudioFreq_16k                ((uint32_t)16000)
-#define I2S_AudioFreq_11k                ((uint32_t)11025)
-#define I2S_AudioFreq_8k                 ((uint32_t)8000)
-#define I2S_AudioFreq_Default            ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
-                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
-                                 ((FREQ) == I2S_AudioFreq_Default))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_Clock_Polarity 
-  * @{
-  */
-
-#define I2S_CPOL_Low                    ((uint16_t)0x0000)
-#define I2S_CPOL_High                   SPI_I2SCFGR_CKPOL
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
-                           ((CPOL) == I2S_CPOL_High))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_FIFO_reception_threshold 
-  * @{
-  */
-
-#define SPI_RxFIFOThreshold_HF          ((uint16_t)0x0000)
-#define SPI_RxFIFOThreshold_QF          SPI_CR2_FRXTH
-#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
-                                             ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests 
-  * @{
-  */
-
-#define SPI_I2S_DMAReq_Tx               SPI_CR2_TXDMAEN
-#define SPI_I2S_DMAReq_Rx               SPI_CR2_RXDMAEN
-#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_last_DMA_transfers
-  * @{
-  */
-
-#define SPI_LastDMATransfer_TxEvenRxEven   ((uint16_t)0x0000)
-#define SPI_LastDMATransfer_TxOddRxEven    ((uint16_t)0x4000)
-#define SPI_LastDMATransfer_TxEvenRxOdd    ((uint16_t)0x2000)
-#define SPI_LastDMATransfer_TxOddRxOdd     ((uint16_t)0x6000)
-#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
-                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
-                                            ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
-                                            ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
-/**
-  * @}
-  */
-/** @defgroup SPI_NSS_internal_software_management 
-  * @{
-  */
-
-#define SPI_NSSInternalSoft_Set         SPI_CR1_SSI
-#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
-                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Transmit_Receive 
-  * @{
-  */
-
-#define SPI_CRC_Tx                      ((uint8_t)0x00)
-#define SPI_CRC_Rx                      ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_direction_transmit_receive 
-  * @{
-  */
-
-#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx                ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
-                                     ((DIRECTION) == SPI_Direction_Tx))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_I2S_interrupts_definition 
-  * @{
-  */
-
-#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
-                                  ((IT) == SPI_I2S_IT_RXNE) || \
-                                  ((IT) == SPI_I2S_IT_ERR))
-
-#define I2S_IT_UDR                      ((uint8_t)0x53)
-#define SPI_IT_MODF                     ((uint8_t)0x55)
-#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
-#define SPI_I2S_IT_FRE                  ((uint8_t)0x58)
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
-                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
-                               ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
-/**
-  * @}
-  */
-
-
-/** @defgroup SPI_transmission_fifo_status_level 
-  * @{
-  */ 
-
-#define SPI_TransmissionFIFOStatus_Empty           ((uint16_t)0x0000)
-#define SPI_TransmissionFIFOStatus_1QuarterFull    ((uint16_t)0x0800) 
-#define SPI_TransmissionFIFOStatus_HalfFull        ((uint16_t)0x1000) 
-#define SPI_TransmissionFIFOStatus_Full            ((uint16_t)0x1800)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_reception_fifo_status_level 
-  * @{
-  */ 
-#define SPI_ReceptionFIFOStatus_Empty           ((uint16_t)0x0000)
-#define SPI_ReceptionFIFOStatus_1QuarterFull    ((uint16_t)0x0200) 
-#define SPI_ReceptionFIFOStatus_HalfFull        ((uint16_t)0x0400) 
-#define SPI_ReceptionFIFOStatus_Full            ((uint16_t)0x0600)
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup SPI_I2S_flags_definition 
-  * @{
-  */
-
-#define SPI_I2S_FLAG_RXNE               SPI_SR_RXNE
-#define SPI_I2S_FLAG_TXE                SPI_SR_TXE
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
-#define SPI_FLAG_MODF                   SPI_SR_MODF
-#define SPI_I2S_FLAG_OVR                SPI_SR_OVR
-#define SPI_I2S_FLAG_BSY                SPI_SR_BSY
-#define SPI_I2S_FLAG_FRE                SPI_SR_FRE
-
-
-
-#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
-                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
-                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
-                                   ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
-                                   ((FLAG) == I2S_FLAG_UDR))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_polynomial 
-  * @{
-  */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SPI_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h

@@ -1,224 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_syscfg.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the SYSCFG firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/*!< Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SYSCFG_H
-#define __STM32F0XX_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup SYSCFG
-  * @{
-  */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Exported_Constants
-  * @{
-  */ 
-  
-/** @defgroup SYSCFG_EXTI_Port_Sources 
-  * @{
-  */ 
-#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
-#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
-                                         ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
-                                         ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
-                                         ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
-                                         ((PORTSOURCE) == EXTI_PortSourceGPIOF)) 
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_EXTI_Pin_sources 
-  * @{
-  */ 
-#define EXTI_PinSource0            ((uint8_t)0x00)
-#define EXTI_PinSource1            ((uint8_t)0x01)
-#define EXTI_PinSource2            ((uint8_t)0x02)
-#define EXTI_PinSource3            ((uint8_t)0x03)
-#define EXTI_PinSource4            ((uint8_t)0x04)
-#define EXTI_PinSource5            ((uint8_t)0x05)
-#define EXTI_PinSource6            ((uint8_t)0x06)
-#define EXTI_PinSource7            ((uint8_t)0x07)
-#define EXTI_PinSource8            ((uint8_t)0x08)
-#define EXTI_PinSource9            ((uint8_t)0x09)
-#define EXTI_PinSource10           ((uint8_t)0x0A)
-#define EXTI_PinSource11           ((uint8_t)0x0B)
-#define EXTI_PinSource12           ((uint8_t)0x0C)
-#define EXTI_PinSource13           ((uint8_t)0x0D)
-#define EXTI_PinSource14           ((uint8_t)0x0E)
-#define EXTI_PinSource15           ((uint8_t)0x0F)
-
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
-                                       ((PINSOURCE) == EXTI_PinSource1) || \
-                                       ((PINSOURCE) == EXTI_PinSource2) || \
-                                       ((PINSOURCE) == EXTI_PinSource3) || \
-                                       ((PINSOURCE) == EXTI_PinSource4) || \
-                                       ((PINSOURCE) == EXTI_PinSource5) || \
-                                       ((PINSOURCE) == EXTI_PinSource6) || \
-                                       ((PINSOURCE) == EXTI_PinSource7) || \
-                                       ((PINSOURCE) == EXTI_PinSource8) || \
-                                       ((PINSOURCE) == EXTI_PinSource9) || \
-                                       ((PINSOURCE) == EXTI_PinSource10) || \
-                                       ((PINSOURCE) == EXTI_PinSource11) || \
-                                       ((PINSOURCE) == EXTI_PinSource12) || \
-                                       ((PINSOURCE) == EXTI_PinSource13) || \
-                                       ((PINSOURCE) == EXTI_PinSource14) || \
-                                       ((PINSOURCE) == EXTI_PinSource15))
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Memory_Remap_Config 
-  * @{
-  */ 
-#define SYSCFG_MemoryRemap_Flash                ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemMemory         ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM                 ((uint8_t)0x03)
-
-
-#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
-                                       ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
-                                       ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_DMA_Remap_Config 
-  * @{
-  */ 
-#define SYSCFG_DMARemap_TIM17       SYSCFG_CFGR1_TIM17_DMA_RMP    /* Remap TIM17 DMA requests from channel1 to channel2 */
-#define SYSCFG_DMARemap_TIM16       SYSCFG_CFGR1_TIM16_DMA_RMP    /* Remap TIM16 DMA requests from channel3 to channel4 */
-#define SYSCFG_DMARemap_USART1Rx    SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
-#define SYSCFG_DMARemap_USART1Tx    SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
-#define SYSCFG_DMARemap_ADC1        SYSCFG_CFGR1_ADC_DMA_RMP      /* Remap ADC1 DMA requests from channel1 to channel2 */
-  
-#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
-                                    ((REMAP) == SYSCFG_DMARemap_TIM16) || \
-                                    ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
-                                    ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
-                                    ((REMAP) == SYSCFG_DMARemap_ADC1))
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_I2C_FastModePlus_Config 
-  * @{
-  */ 
-#define SYSCFG_I2CFastModePlus_PB6       SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
-#define SYSCFG_I2CFastModePlus_PB7       SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
-#define SYSCFG_I2CFastModePlus_PB8       SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
-#define SYSCFG_I2CFastModePlus_PB9       SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
-
-#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
-                                ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
-                                ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
-                                ((PIN) == SYSCFG_I2CFastModePlus_PB9))
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Lock_Config 
-  * @{
-  */ 
-#define SYSCFG_Break_PVD                     SYSCFG_CFGR2_PVD_LOCK       /*!< Connects the PVD event to the Break Input of TIM1 */
-#define SYSCFG_Break_SRAMParity              SYSCFG_CFGR2_SRAM_PARITY_LOCK  /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
-#define SYSCFG_Break_Lockup                  SYSCFG_CFGR2_LOCKUP_LOCK       /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
-
-#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD)        || \
-                                       ((CONFIG) == SYSCFG_Break_SRAMParity) || \
-                                       ((CONFIG) == SYSCFG_Break_Lockup))
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_flags_definition 
-  * @{
-  */
-
-#define SYSCFG_FLAG_PE               SYSCFG_CFGR2_SRAM_PE
-
-#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the SYSCFG configuration to the default reset state **/
-void SYSCFG_DeInit(void);
-
-/* SYSCFG configuration functions *********************************************/ 
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SYSCFG_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h

@@ -1,1182 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_tim.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the TIM 
-  *          firmware library. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_TIM_H
-#define __STM32F0XX_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  TIM Time Base Init structure definition
-  * @note   This sturcture is used with all TIMx.
-  */
-
-typedef struct
-{
-  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                       This parameter can be a number between 0x0000 and 0xFFFF */
-
-  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
-                                       This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
-                                       Auto-Reload Register at the next update event.
-                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
-
-  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
-                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
-  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                       reaches zero, an update event is generated and counting restarts
-                                       from the RCR value (N).
-                                       This means in PWM mode that (N+1) corresponds to:
-                                          - the number of PWM periods in edge-aligned mode
-                                          - the number of half PWM period in center-aligned mode
-                                       This parameter must be a number between 0x00 and 0xFF. 
-                                       @note This parameter is valid only for TIM1. */
-} TIM_TimeBaseInitTypeDef;       
-
-/** 
-  * @brief  TIM Output Compare Init structure definition  
-  */
-
-typedef struct
-{
-  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
-                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_state */
-
-  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_state
-                                   @note This parameter is valid only for TIM1. */
-
-  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
-                                   This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF 
-                                   for TIM2) */
-
-  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
-                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
-                                   @note This parameter is valid only for TIM1. */
-
-  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                                   @note This parameter is valid only for TIM1. */
-
-  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
-                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
-                                   @note This parameter is valid only for TIM1. */
-} TIM_OCInitTypeDef;
-
-/** 
-  * @brief  TIM Input Capture Init structure definition  
-  */
-
-typedef struct
-{
-
-  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
-                                  This parameter can be a value of @ref TIM_Channel */
-
-  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint16_t TIM_ICSelection;  /*!< Specifies the input.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
-                                  This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/** 
-  * @brief  TIM_BDTR structure definition 
-  * @note   This sturcture is used only with TIM1.    
-  */
-
-typedef struct
-{
-
-  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
-                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
-  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
-                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
-  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
-                                      This parameter can be a value of @ref TIM_Lock_level */ 
-
-  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
-                                      switching-on of the outputs.
-                                      This parameter can be a number between 0x00 and 0xFF  */
-
-  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
-                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
-  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
-                                      This parameter can be a value of @ref TIM_Break_Polarity */
-
-  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
-                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/** 
-  * @brief  TIM Input Capture Init structure definition  
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-  
-/** @defgroup TIM_Exported_constants 
-  * @{
-  */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                   ((PERIPH) == TIM2) || \
-                                   ((PERIPH) == TIM3) || \
-                                   ((PERIPH) == TIM6) || \
-                                   ((PERIPH) == TIM14)|| \
-                                   ((PERIPH) == TIM15)|| \
-                                   ((PERIPH) == TIM16)|| \
-                                   ((PERIPH) == TIM17))
-
-/* LIST1: TIM 1 */
-#define IS_TIM_LIST1_PERIPH(PERIPH)  ((PERIPH) == TIM1)
-
-/* LIST2: TIM 1, 15, 16 and 17 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17)) 
-
-/* LIST3: TIM 1, 2 and 3 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3)) 
-
-/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM14) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17))
-
-/* LIST4: TIM 1, 2, 3, 15, 16 and 17 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17))
-
-/* LIST5: TIM 1, 2, 3 and 15 */
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM15)) 
-
-/* LIST7: TIM 1, 2, 3, 6 and 14 */
-#define IS_TIM_LIST7_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM6) || \
-                                      ((PERIPH) == TIM14))
-                                      
-/* LIST8: TIM 1, 2, 3 and 14 */
-#define IS_TIM_LIST8_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM14))
-
-/* LIST9: TIM 1, 2, 3, 6 and 15 */
-#define IS_TIM_LIST9_PERIPH(PERIPH)  (((PERIPH) == TIM1) || \
-                                      ((PERIPH) == TIM2) || \
-                                      ((PERIPH) == TIM3) || \
-                                      ((PERIPH) == TIM6) || \
-                                      ((PERIPH) == TIM15))
-
-/* LIST10: TIM 1, 2, 3, 6, 15, 16 and 17 */
-#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
-                                     ((PERIPH) == TIM2) || \
-                                     ((PERIPH) == TIM3) || \
-                                     ((PERIPH) == TIM6) || \
-                                     ((PERIPH) == TIM15)|| \
-                                     ((PERIPH) == TIM16)|| \
-                                     ((PERIPH) == TIM17))
-
-/* LIST1: TIM 11 */
-#define IS_TIM_LIST11_PERIPH(PERIPH)  ((PERIPH) == TIM14)
-                                     
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes 
-  * @{
-  */
-
-#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
-#define TIM_OCMode_Active                  ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
-                              ((MODE) == TIM_OCMode_Active) || \
-                              ((MODE) == TIM_OCMode_Inactive) || \
-                              ((MODE) == TIM_OCMode_Toggle)|| \
-                              ((MODE) == TIM_OCMode_PWM1) || \
-                              ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
-                          ((MODE) == TIM_OCMode_Active) || \
-                          ((MODE) == TIM_OCMode_Inactive) || \
-                          ((MODE) == TIM_OCMode_Toggle)|| \
-                          ((MODE) == TIM_OCMode_PWM1) || \
-                          ((MODE) == TIM_OCMode_PWM2) ||	\
-                          ((MODE) == TIM_ForcedAction_Active) || \
-                          ((MODE) == TIM_ForcedAction_InActive))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode 
-  * @{
-  */
-
-#define TIM_OPMode_Single                  ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
-                               ((MODE) == TIM_OPMode_Repetitive))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Channel 
-  * @{
-  */
-
-#define TIM_Channel_1                      ((uint16_t)0x0000)
-#define TIM_Channel_2                      ((uint16_t)0x0004)
-#define TIM_Channel_3                      ((uint16_t)0x0008)
-#define TIM_Channel_4                      ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                 ((CHANNEL) == TIM_Channel_2) || \
-                                 ((CHANNEL) == TIM_Channel_3) || \
-                                 ((CHANNEL) == TIM_Channel_4))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                               ((CHANNEL) == TIM_Channel_2) || \
-                                               ((CHANNEL) == TIM_Channel_3))
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
-                                      ((CHANNEL) == TIM_Channel_2))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Clock_Division_CKD 
-  * @{
-  */
-
-#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
-#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
-#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
-                             ((DIV) == TIM_CKD_DIV2) || \
-                             ((DIV) == TIM_CKD_DIV4))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode 
-  * @{
-  */
-
-#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
-#define TIM_CounterMode_Down               ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
-                                   ((MODE) == TIM_CounterMode_Down) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
-                                   ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Polarity 
-  * @{
-  */
-
-#define TIM_OCPolarity_High                ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
-                                      ((POLARITY) == TIM_OCPolarity_Low))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_N_Polarity 
-  * @{
-  */
-  
-#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
-                                       ((POLARITY) == TIM_OCNPolarity_Low))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_state
-  * @{
-  */
-
-#define TIM_OutputState_Disable            ((uint16_t)0x0000)
-#define TIM_OutputState_Enable             ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
-                                    ((STATE) == TIM_OutputState_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_N_state 
-  * @{
-  */
-
-#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
-                                     ((STATE) == TIM_OutputNState_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Capture_Compare_state 
-  * @{
-  */
-
-#define TIM_CCx_Enable                      ((uint16_t)0x0001)
-#define TIM_CCx_Disable                     ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
-                         ((CCX) == TIM_CCx_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Capture_Compare_N_state 
-  * @{
-  */
-
-#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
-#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
-                           ((CCXN) == TIM_CCxN_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Break_Input_enable_disable 
-  * @{
-  */
-
-#define TIM_Break_Enable                   ((uint16_t)0x1000)
-#define TIM_Break_Disable                  ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
-                                   ((STATE) == TIM_Break_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Break_Polarity 
-  * @{
-  */
-
-#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
-                                         ((POLARITY) == TIM_BreakPolarity_High))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_AOE_Bit_Set_Reset 
-  * @{
-  */
-
-#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
-                                              ((STATE) == TIM_AutomaticOutput_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Lock_level 
-  * @{
-  */
-
-#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLevel_1) || \
-                                  ((LEVEL) == TIM_LOCKLevel_2) || \
-                                  ((LEVEL) == TIM_LOCKLevel_3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
-  * @{
-  */
-
-#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
-                                  ((STATE) == TIM_OSSIState_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 
-  * @{
-  */
-
-#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
-                                  ((STATE) == TIM_OSSRState_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Idle_State 
-  * @{
-  */
-
-#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
-                                    ((STATE) == TIM_OCIdleState_Reset))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_N_Idle_State 
-  * @{
-  */
-
-#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
-                                     ((STATE) == TIM_OCNIdleState_Reset))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Polarity 
-  * @{
-  */
-
-#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
-#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
-#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
-                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
-                                      ((POLARITY) == TIM_ICPolarity_BothEdge)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Selection 
-  * @{
-  */
-
-#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
-                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
-                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
-                                        ((SELECTION) == TIM_ICSelection_TRC))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Input_Capture_Prescaler 
-  * @{
-  */
-
-#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_interrupt_sources 
-  * @{
-  */
-
-#define TIM_IT_Update                      ((uint16_t)0x0001)
-#define TIM_IT_CC1                         ((uint16_t)0x0002)
-#define TIM_IT_CC2                         ((uint16_t)0x0004)
-#define TIM_IT_CC3                         ((uint16_t)0x0008)
-#define TIM_IT_CC4                         ((uint16_t)0x0010)
-#define TIM_IT_COM                         ((uint16_t)0x0020)
-#define TIM_IT_Trigger                     ((uint16_t)0x0040)
-#define TIM_IT_Break                       ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
-                           ((IT) == TIM_IT_CC1) || \
-                           ((IT) == TIM_IT_CC2) || \
-                           ((IT) == TIM_IT_CC3) || \
-                           ((IT) == TIM_IT_CC4) || \
-                           ((IT) == TIM_IT_COM) || \
-                           ((IT) == TIM_IT_Trigger) || \
-                           ((IT) == TIM_IT_Break))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_Base_address 
-  * @{
-  */
-
-#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
-#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
-#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
-#define TIM_DMABase_SR                     ((uint16_t)0x0004)
-#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
-#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
-#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
-#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
-#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
-#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
-#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
-#define TIM_DMABase_OR                     ((uint16_t)0x0013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
-                               ((BASE) == TIM_DMABase_CR2) || \
-                               ((BASE) == TIM_DMABase_SMCR) || \
-                               ((BASE) == TIM_DMABase_DIER) || \
-                               ((BASE) == TIM_DMABase_SR) || \
-                               ((BASE) == TIM_DMABase_EGR) || \
-                               ((BASE) == TIM_DMABase_CCMR1) || \
-                               ((BASE) == TIM_DMABase_CCMR2) || \
-                               ((BASE) == TIM_DMABase_CCER) || \
-                               ((BASE) == TIM_DMABase_CNT) || \
-                               ((BASE) == TIM_DMABase_PSC) || \
-                               ((BASE) == TIM_DMABase_ARR) || \
-                               ((BASE) == TIM_DMABase_RCR) || \
-                               ((BASE) == TIM_DMABase_CCR1) || \
-                               ((BASE) == TIM_DMABase_CCR2) || \
-                               ((BASE) == TIM_DMABase_CCR3) || \
-                               ((BASE) == TIM_DMABase_CCR4) || \
-                               ((BASE) == TIM_DMABase_BDTR) || \
-							   ((BASE) == TIM_DMABase_DCR) || \
-                               ((BASE) == TIM_DMABase_OR))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup TIM_DMA_Burst_Length 
-  * @{
-  */
-
-#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
-                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_DMA_sources 
-  * @{
-  */
-
-#define TIM_DMA_Update                     ((uint16_t)0x0100)
-#define TIM_DMA_CC1                        ((uint16_t)0x0200)
-#define TIM_DMA_CC2                        ((uint16_t)0x0400)
-#define TIM_DMA_CC3                        ((uint16_t)0x0800)
-#define TIM_DMA_CC4                        ((uint16_t)0x1000)
-#define TIM_DMA_COM                        ((uint16_t)0x2000)
-#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Prescaler 
-  * @{
-  */
-
-#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
-                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Internal_Trigger_Selection 
-  * @{
-  */
-
-#define TIM_TS_ITR0                        ((uint16_t)0x0000)
-#define TIM_TS_ITR1                        ((uint16_t)0x0010)
-#define TIM_TS_ITR2                        ((uint16_t)0x0020)
-#define TIM_TS_ITR3                        ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
-#define TIM_TS_ETRF                        ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                             ((SELECTION) == TIM_TS_ITR1) || \
-                                             ((SELECTION) == TIM_TS_ITR2) || \
-                                             ((SELECTION) == TIM_TS_ITR3) || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1) || \
-                                             ((SELECTION) == TIM_TS_TI2FP2) || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                      ((SELECTION) == TIM_TS_ITR1) || \
-                                                      ((SELECTION) == TIM_TS_ITR2) || \
-                                                      ((SELECTION) == TIM_TS_ITR3))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_TIx_External_Clock_Source 
-  * @{
-  */
-
-#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Polarity 
-  * @{
-  */ 
-#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
-                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Prescaler_Reload_Mode 
-  * @{
-  */
-
-#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
-                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Forced_Action 
-  * @{
-  */
-
-#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
-                                      ((ACTION) == TIM_ForcedAction_InActive))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Encoder_Mode 
-  * @{
-  */
-
-#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
-                                   ((MODE) == TIM_EncoderMode_TI2) || \
-                                   ((MODE) == TIM_EncoderMode_TI12))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup TIM_Event_Source 
-  * @{
-  */
-
-#define TIM_EventSource_Update             ((uint16_t)0x0001)
-#define TIM_EventSource_CC1                ((uint16_t)0x0002)
-#define TIM_EventSource_CC2                ((uint16_t)0x0004)
-#define TIM_EventSource_CC3                ((uint16_t)0x0008)
-#define TIM_EventSource_CC4                ((uint16_t)0x0010)
-#define TIM_EventSource_COM                ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
-#define TIM_EventSource_Break              ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Update_Source 
-  * @{
-  */
-
-#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
-                                                                   or the setting of UG bit, or an update generation
-                                                                   through the slave mode controller. */
-#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
-                                      ((SOURCE) == TIM_UpdateSource_Regular))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Preload_State 
-  * @{
-  */
-
-#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
-                                       ((STATE) == TIM_OCPreload_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Fast_State 
-  * @{
-  */
-
-#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
-#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
-                                    ((STATE) == TIM_OCFast_Disable))
-                                     
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Output_Compare_Clear_State 
-  * @{
-  */
-
-#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
-#define TIM_OCClear_Disable                ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
-                                     ((STATE) == TIM_OCClear_Disable))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Trigger_Output_Source 
-  * @{
-  */
-
-#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
-                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
-                                    ((SOURCE) == TIM_TRGOSource_Update) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
-                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Slave_Mode 
-  * @{
-  */
-
-#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
-                                 ((MODE) == TIM_SlaveMode_Gated) || \
-                                 ((MODE) == TIM_SlaveMode_Trigger) || \
-                                 ((MODE) == TIM_SlaveMode_External1))
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_Master_Slave_Mode 
-  * @{
-  */
-
-#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
-                                 ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
-  * @}
-  */ 
-  
-/** @defgroup TIM_Flags 
-  * @{
-  */
-
-#define TIM_FLAG_Update                    ((uint16_t)0x0001)
-#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
-#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
-#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
-#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
-#define TIM_FLAG_COM                       ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
-#define TIM_FLAG_Break                     ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
-                               ((FLAG) == TIM_FLAG_CC1) || \
-                               ((FLAG) == TIM_FLAG_CC2) || \
-                               ((FLAG) == TIM_FLAG_CC3) || \
-                               ((FLAG) == TIM_FLAG_CC4) || \
-                               ((FLAG) == TIM_FLAG_COM) || \
-                               ((FLAG) == TIM_FLAG_Trigger) || \
-                               ((FLAG) == TIM_FLAG_Break) || \
-                               ((FLAG) == TIM_FLAG_CC1OF) || \
-                               ((FLAG) == TIM_FLAG_CC2OF) || \
-                               ((FLAG) == TIM_FLAG_CC3OF) || \
-                               ((FLAG) == TIM_FLAG_CC4OF))
-                               
-                               
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup TIM_Input_Capture_Filer_Value 
-  * @{
-  */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
-/**
-  * @}
-  */ 
-
-/** @defgroup TIM_External_Trigger_Filter 
-  * @{
-  */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OCReferenceClear 
-  * @{
-  */
-#define TIM_OCReferenceClear_ETRF          ((uint16_t)0x0008)
-#define TIM_OCReferenceClear_OCREFCLR      ((uint16_t)0x0000)
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
-                                              ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Remap 
-  * @{
-  */
-#define TIM14_GPIO                      ((uint16_t)0x0000)
-#define TIM14_RTC_CLK                   ((uint16_t)0x0001)
-#define TIM14_HSEDiv32                  ((uint16_t)0x0002)
-#define TIM14_MCO                       ((uint16_t)0x0003)
-
-#define IS_TIM_REMAP(TIM_REMAP)  (((TIM_REMAP) == TIM14_GPIO)|| \
-                                  ((TIM_REMAP) == TIM14_RTC_CLK) || \
-                                  ((TIM_REMAP) == TIM14_HSEDiv32) || \
-                                  ((TIM_REMAP) == TIM14_MCO))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Legacy 
-  * @{
-  */
-
-#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */ 
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Advanced-control timers (TIM1) specific features*******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
-                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                             uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
-                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                   uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/                   
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
-                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_TIM_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h

@@ -1,593 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_usart.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the USART 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_USART_H
-#define __STM32F0XX_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-   
-   
-/** 
-  * @brief  USART Init Structure definition  
-  */ 
-
-typedef struct
-{
-  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                            - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
-                                            - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
-  uint32_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint32_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint32_t USART_Parity;              /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref USART_Hardware_Flow_Control*/
-} USART_InitTypeDef;
-
-/** 
-  * @brief  USART Clock Init Structure definition
-  */ 
-
-typedef struct
-{
-  uint32_t USART_Clock;             /*!< Specifies whether the USART clock is enabled or disabled.
-                                         This parameter can be a value of @ref USART_Clock */
-
-  uint32_t USART_CPOL;              /*!< Specifies the steady state of the serial clock.
-                                         This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint32_t USART_CPHA;              /*!< Specifies the clock transition on which the bit capture is made.
-                                         This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint32_t USART_LastBit;           /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                         data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                         This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
-  * @{
-  */ 
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
-                                     ((PERIPH) == USART2))
-
-#define IS_USART_1_PERIPH(PERIPH) (((PERIPH) == USART1))
-
-/** @defgroup USART_Word_Length 
-  * @{
-  */ 
-
-#define USART_WordLength_8b                  ((uint32_t)0x00000000)
-#define USART_WordLength_9b                  USART_CR1_M
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
-                                      ((LENGTH) == USART_WordLength_9b))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Stop_Bits 
-  * @{
-  */ 
-
-#define USART_StopBits_1                     ((uint32_t)0x00000000)
-#define USART_StopBits_2                     ((uint32_t)USART_CR2_STOP_1)
-#define USART_StopBits_1_5                   ((uint32_t)USART_CR2_STOP_0 | USART_CR2_STOP_1)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
-                                     ((STOPBITS) == USART_StopBits_2) || \
-                                     ((STOPBITS) == USART_StopBits_1_5))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Parity 
-  * @{
-  */ 
-
-#define USART_Parity_No                      ((uint32_t)0x00000000)
-#define USART_Parity_Even                    ((uint32_t)USART_CR1_PCE)
-#define USART_Parity_Odd                     ((uint32_t)USART_CR1_PCE | USART_CR1_PS) 
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
-                                 ((PARITY) == USART_Parity_Even) || \
-                                 ((PARITY) == USART_Parity_Odd))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Mode 
-  * @{
-  */ 
-
-#define USART_Mode_Rx                        USART_CR1_RE
-#define USART_Mode_Tx                        USART_CR1_TE
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
-                              ((MODE) != (uint32_t)0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Hardware_Flow_Control 
-  * @{
-  */ 
-
-#define USART_HardwareFlowControl_None       ((uint32_t)0x00000000)
-#define USART_HardwareFlowControl_RTS        ((uint32_t)USART_CR3_RTSE)
-#define USART_HardwareFlowControl_CTS        ((uint32_t)USART_CR3_CTSE)
-#define USART_HardwareFlowControl_RTS_CTS    ((uint32_t)USART_CR3_RTSE | USART_CR3_CTSE)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == USART_HardwareFlowControl_None) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
-                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock 
-  * @{
-  */ 
-  
-#define USART_Clock_Disable                  ((uint32_t)0x00000000)
-#define USART_Clock_Enable                   USART_CR2_CLKEN
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
-                               ((CLOCK) == USART_Clock_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Polarity 
-  * @{
-  */
-  
-#define USART_CPOL_Low                       ((uint32_t)0x00000000)
-#define USART_CPOL_High                      USART_CR2_CPOL
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Phase
-  * @{
-  */
-
-#define USART_CPHA_1Edge                     ((uint32_t)0x00000000)
-#define USART_CPHA_2Edge                     USART_CR2_CPHA
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit
-  * @{
-  */
-
-#define USART_LastBit_Disable                ((uint32_t)0x00000000)
-#define USART_LastBit_Enable                 USART_CR2_LBCL
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
-                                   ((LASTBIT) == USART_LastBit_Enable))
-/**
-  * @}
-  */
-  
-/** @defgroup USART_DMA_Requests 
-  * @{
-  */
-
-#define USART_DMAReq_Tx                      USART_CR3_DMAT
-#define USART_DMAReq_Rx                      USART_CR3_DMAR
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
-                                  ((DMAREQ) != (uint32_t)0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_DMA_Recception_Error
-  * @{
-  */
-
-#define USART_DMAOnError_Enable              ((uint32_t)0x00000000)
-#define USART_DMAOnError_Disable             USART_CR3_DDRE
-#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
-                                       ((DMAERROR) == USART_DMAOnError_Enable))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_MuteMode_WakeUp_methods
-  * @{
-  */
-
-#define USART_WakeUp_IdleLine                ((uint32_t)0x00000000)
-#define USART_WakeUp_AddressMark             USART_CR1_WAKE
-#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
-                                          ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Address_Detection
-  * @{
-  */ 
-
-#define USART_AddressLength_4b               ((uint32_t)0x00000000)
-#define USART_AddressLength_7b               USART_CR2_ADDM7
-#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
-                                             ((ADDRESS) == USART_AddressLength_7b))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_StopMode_WakeUp_methods 
-  * @{
-  */ 
-
-#define USART_WakeUpSource_AddressMatch      ((uint32_t)0x00000000)
-#define USART_WakeUpSource_StartBit          ((uint32_t)USART_CR3_WUS_1)
-#define USART_WakeUpSource_RXNE              ((uint32_t)USART_CR3_WUS_0 | USART_CR3_WUS_1)
-#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
-                                                ((SOURCE) == USART_WakeUpSource_StartBit) || \
-                                                ((SOURCE) == USART_WakeUpSource_RXNE))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_LIN_Break_Detection_Length 
-  * @{
-  */
-  
-#define USART_LINBreakDetectLength_10b       ((uint32_t)0x00000000)
-#define USART_LINBreakDetectLength_11b       USART_CR2_LBDL
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
-                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
-                                ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
-  * @}
-  */
-
-/** @defgroup USART_IrDA_Low_Power 
-  * @{
-  */
-
-#define USART_IrDAMode_LowPower              USART_CR3_IRLP
-#define USART_IrDAMode_Normal                ((uint32_t)0x00000000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
-                                  ((MODE) == USART_IrDAMode_Normal))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_DE_Polarity 
-  * @{
-  */
-
-#define USART_DEPolarity_High                ((uint32_t)0x00000000)
-#define USART_DEPolarity_Low                 USART_CR3_DEP
-#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
-                                        ((POLARITY) == USART_DEPolarity_High))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Inversion_Pins 
-  * @{
-  */
-
-#define USART_InvPin_Tx                      USART_CR2_TXINV
-#define USART_InvPin_Rx                      USART_CR2_RXINV
-#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
-                                       ((PIN) != (uint32_t)0x00))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_AutoBaudRate_Mode 
-  * @{
-  */
-
-#define USART_AutoBaudRate_StartBit          ((uint32_t)0x00000000)
-#define USART_AutoBaudRate_FallingEdge       USART_CR2_ABRMODE_0
-#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
-                                          ((MODE) == USART_AutoBaudRate_FallingEdge))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_OVR_DETECTION
-  * @{
-  */
-
-#define USART_OVRDetection_Enable            ((uint32_t)0x00000000)
-#define USART_OVRDetection_Disable           USART_CR3_OVRDIS
-#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
-                                    ((OVR) == USART_OVRDetection_Disable))
-/**
-  * @}
-  */ 
-/** @defgroup USART_Request 
-  * @{
-  */
-
-#define USART_Request_ABRRQ                  USART_RQR_ABRRQ
-#define USART_Request_SBKRQ                  USART_RQR_SBKRQ
-#define USART_Request_MMRQ                   USART_RQR_MMRQ
-#define USART_Request_RXFRQ                  USART_RQR_RXFRQ
-#define USART_Request_TXFRQ                  USART_RQR_TXFRQ
-
-#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
-                                   ((REQUEST) == USART_Request_RXFRQ) || \
-                                   ((REQUEST) == USART_Request_MMRQ) || \
-                                   ((REQUEST) == USART_Request_SBKRQ) || \
-                                   ((REQUEST) == USART_Request_ABRRQ))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Flags 
-  * @{
-  */
-#define USART_FLAG_REACK                     USART_ISR_REACK
-#define USART_FLAG_TEACK                     USART_ISR_TEACK
-#define USART_FLAG_WU                        USART_ISR_WUF
-#define USART_FLAG_RWU                       USART_ISR_RWU
-#define USART_FLAG_SBK                       USART_ISR_SBKF
-#define USART_FLAG_CM                        USART_ISR_CMF
-#define USART_FLAG_BUSY                      USART_ISR_BUSY
-#define USART_FLAG_ABRF                      USART_ISR_ABRF
-#define USART_FLAG_ABRE                      USART_ISR_ABRE
-#define USART_FLAG_EOB                       USART_ISR_EOBF
-#define USART_FLAG_RTO                       USART_ISR_RTOF
-#define USART_FLAG_nCTSS                     USART_ISR_CTS 
-#define USART_FLAG_CTS                       USART_ISR_CTSIF
-#define USART_FLAG_LBD                       USART_ISR_LBD
-#define USART_FLAG_TXE                       USART_ISR_TXE
-#define USART_FLAG_TC                        USART_ISR_TC
-#define USART_FLAG_RXNE                      USART_ISR_RXNE
-#define USART_FLAG_IDLE                      USART_ISR_IDLE
-#define USART_FLAG_ORE                       USART_ISR_ORE
-#define USART_FLAG_NE                        USART_ISR_NE
-#define USART_FLAG_FE                        USART_ISR_FE
-#define USART_FLAG_PE                        USART_ISR_PE
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
-                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
-                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
-                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
-                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
-                             ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
-                             ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
-                             ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
-                             ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
-                             ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
-                             ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
-
-#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
-                                   ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
-                                   ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
-                                   ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
-                                   ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
-                                   ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Interrupt_definition 
-  * @brief USART Interrupt definition
-  * USART_IT possible values
-  * Elements values convention: 0xZZZZYYXX
-  *   XX: Position of the corresponding Interrupt
-  *   YY: Register index
-  *   ZZZZ: Flag position
-  * @{
-  */
-
-#define USART_IT_WU                          ((uint32_t)0x00140316)
-#define USART_IT_CM                          ((uint32_t)0x0011010E)
-#define USART_IT_EOB                         ((uint32_t)0x000C011B)
-#define USART_IT_RTO                         ((uint32_t)0x000B011A)
-#define USART_IT_PE                          ((uint32_t)0x00000108)
-#define USART_IT_TXE                         ((uint32_t)0x00070107)
-#define USART_IT_TC                          ((uint32_t)0x00060106)
-#define USART_IT_RXNE                        ((uint32_t)0x00050105)
-#define USART_IT_IDLE                        ((uint32_t)0x00040104)
-#define USART_IT_LBD                         ((uint32_t)0x00080206)
-#define USART_IT_CTS                         ((uint32_t)0x0009030A) 
-#define USART_IT_ERR                         ((uint32_t)0x00000300)
-#define USART_IT_ORE                         ((uint32_t)0x00030300)
-#define USART_IT_NE                          ((uint32_t)0x00020300)
-#define USART_IT_FE                          ((uint32_t)0x00010300)
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
-                                ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
-                                ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
-                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
-                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
-                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
-                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
-                             ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
-                             ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
-                               ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
-                               ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
-                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
-                               ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
-                               ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Global_definition 
-  * @{
-  */
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
-#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
-#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
-#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
-
-/* STOP Mode functions ********************************************************/
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
-
-/* AutoBaudRate functions *****************************************************/
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
-void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* RS485 mode functions *******************************************************/
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_USART_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h

@@ -1,109 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_wwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file contains all the functions prototypes for the WWDG 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_WWDG_H
-#define __STM32F0XX_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup WWDG
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
-  * @{
-  */ 
-  
-/** @defgroup WWDG_Prescaler 
-  * @{
-  */ 
-  
-#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
-                                      ((PRESCALER) == WWDG_Prescaler_2) || \
-                                      ((PRESCALER) == WWDG_Prescaler_4) || \
-                                      ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/*  Function used to set the WWDG configuration to the default reset state ****/  
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation functions **************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_WWDG_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c

@@ -1,1218 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_adc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
-  *           + Initialization and Configuration
-  *           + Power saving
-  *           + Analog Watchdog configuration
-  *           + Temperature Sensor, Vrefint (Internal Reference Voltage) and 
-  *             Vbat (Voltage battery) management 
-  *           + ADC Channels Configuration
-  *           + ADC Channels DMA Configuration
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
-================================================================================
-                      ##### How to use this driver #####
-================================================================================
-    [..]
-    (#) Enable the ADC interface clock using 
-        RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); 
-    (#) ADC pins configuration
-       (++) Enable the clock for the ADC GPIOs using the following function:
-            RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);   
-       (++) Configure these ADC pins in analog mode using GPIO_Init();  
-    (#) Configure the ADC conversion resolution, data alignment, external
-        trigger and edge, scan direction and Enable/Disable the continuous mode
-        using the ADC_Init() function.
-    (#) Activate the ADC peripheral using ADC_Cmd() function.
-
-    *** ADC channels group configuration ***
-    ============================================
-    [..] 
-    (+) To configure the ADC channels features, use ADC_Init() and 
-        ADC_ChannelConfig() functions.
-    (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
-        function.
-    (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions. 
-    (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
-    (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions.
-    (+) To read the ADC converted values, use the ADC_GetConversionValue()
-        function.
-
-    *** DMA for ADC channels features configuration ***
-    =============================================================
-    [..] 
-    (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
-    (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function.
-
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_adc.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup ADC 
-  * @brief ADC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ADC CFGR mask */
-#define CFGR1_CLEAR_MASK           ((uint32_t)0xFFFFD203)
-
-/* Calibration time out */
-#define CALIBRATION_TIMEOUT       ((uint32_t)0x0000F000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
-  * @{
-  */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-          ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..] This section provides functions allowing to:
-        (+) Initialize and configure the ADC Prescaler
-        (+) ADC Conversion Resolution (12bit..6bit)
-        (+) ADC Continuous Conversion Mode (Continuous or Single conversion)
-        (+) External trigger Edge and source 
-        (+) Converted data alignment (left or right)
-        (+) The direction in which the channels will be scanned in the sequence
-        (+) Enable or disable the ADC peripheral
-   
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes ADC1 peripheral registers to their default reset values.
-  * @param  ADCx: where x can be 1 to select the ADC peripheral.
-  * @retval None
-  */
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
-  if(ADCx == ADC1)
-  {
-    /* Enable ADC1 reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
-
-    /* Release ADC1 from reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the ADCx peripheral according to the specified parameters
-  *         in the ADC_InitStruct.
-  * @note   This function is used to configure the global features of the ADC ( 
-  *         Resolution, Data Alignment, continuous mode activation, External 
-  *         trigger source and edge, Sequence Scan Direction).   
-  * @param  ADCx: where x can be 1 to select the ADC peripheral.
-  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains 
-  *         the configuration information for the specified ADC peripheral.
-  * @retval None
-  */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
-  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
-  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
-  assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
-  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
-  assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection)); 
-
-  /* Get the ADCx CFGR value */
-  tmpreg = ADCx->CFGR1;
-
-  /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
-  tmpreg &= CFGR1_CLEAR_MASK;
-
-  /*---------------------------- ADCx CFGR Configuration ---------------------*/
-
-  /* Set RES[1:0] bits according to ADC_Resolution value */
-  /* Set CONT bit according to ADC_ContinuousConvMode value */
-  /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
-  /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
-  /* Set ALIGN bit according to ADC_DataAlign value */
-  /* Set SCANDIR bit according to ADC_ScanDirection value */
- 
-  tmpreg  |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
-             ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
-             ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
-
-  /* Write to ADCx CFGR */
-  ADCx->CFGR1 = tmpreg;
-}
-
-/**
-  * @brief  Fills each ADC_InitStruct member with its default value.
-  * @note   This function is used to initialize the global features of the ADC ( 
-  *         Resolution, Data Alignment, continuous mode activation, External 
-  *         trigger source and edge, Sequence Scan Direction).
-  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
-  /* Reset ADC init structure parameters values */
-  /* Initialize the ADC_Resolution member */
-  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
-   /* Initialize the ADC_ContinuousConvMode member */
-  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
-  /* Initialize the ADC_ExternalTrigConvEdge member */
-  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
-  /* Initialize the ADC_ExternalTrigConv member */
-  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
-
-  /* Initialize the ADC_DataAlign member */
-  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
-  /* Initialize the ADC_ScanDirection member */
-  ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
-}
-
-/**
-  * @brief  Enables or disables the specified ADC peripheral.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the ADCx peripheral. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Set the ADEN bit to Enable the ADC peripheral */
-    ADCx->CR |= (uint32_t)ADC_CR_ADEN;
-  }
-  else
-  {
-    /* Set the ADDIS to Disable the ADC peripheral */
-    ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
-  }
-}
-
-/**
-  * @brief  Enables or disables the jitter when the ADC is clocked by PCLK div2
-  *         or div4
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_JitterOff: This parameter can be :
-  *     @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2
-  *     @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4
-  * @param  NewState: new state of the ADCx jitter. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Disable Jitter */
-    ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
-  }
-  else
-  {
-    /* Enable Jitter */
-    ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group2 Power saving functions
- *  @brief   Power saving functions 
- *
-@verbatim
- ===============================================================================
-          ##### Power saving functions #####
- ===============================================================================
-    [..] This section provides functions allowing to reduce power consumption.
-    [..] The two function must be combined to get the maximal benefits:
-         When the ADC frequency is higher than the CPU one, it is recommended to 
-         (#) Enable the Auto Delayed Conversion mode : 
-             ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-         (#) Enable the power off in Delay phases :
-             ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the ADC Power Off.
-  * @note   ADC power-on and power-off can be managed by hardware to cut the 
-  *         consumption when the ADC is not converting. 
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @note   The ADC can be powered down: 
-  *         - During the Auto delay phase 
-  *           => The ADC is powered on again at the end of the delay (until the 
-  *              previous data is read from the ADC data register). 
-  *         - During the ADC is waiting for a trigger event 
-  *           => The ADC is powered up at the next trigger event (when the 
-  *              conversion is started).
-  * @param  NewState: new state of the ADCx power Off. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the ADC Automatic Power-Off */
-    ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
-  }
-  else
-  {
-    /* Disable the ADC Automatic Power-Off */
-    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
-  }
-}
-
-/**
-  * @brief  Enables or disables the Wait conversion mode.
-  * @note   When the CPU clock is not fast enough to manage the data rate, a 
-  *         Hardware delay can be introduced between ADC conversions to reduce 
-  *         this data rate. 
-  * @note   The Hardware delay is inserted after :
-  *         - after each conversions and until the previous data is read from the 
-  *           ADC data register
-  * @note   This is a way to automatically adapt the speed of the ADC to the speed 
-  *         of the system which will read the data.
-  * @note   Any hardware triggers wich occur while a conversion is on going or 
-  *         while the automatic Delay is applied are ignored 
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the ADCx Auto-Delay.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the ADC Automatic Delayed conversion */
-    ADCx->CFGR1 |= ADC_CFGR1_WAIT;
-  }
-  else
-  {
-    /* Disable the ADC Automatic Delayed conversion */
-    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group3 Analog Watchdog configuration functions
- *  @brief   Analog Watchdog configuration functions 
- *
-@verbatim
- ===============================================================================
-                   ##### Analog Watchdog configuration functions #####
- ===============================================================================  
-    [..] This section provides functions allowing to configure the Analog Watchdog
-         (AWD) feature in the ADC.
-    [..] A typical configuration Analog Watchdog is done following these steps :
-         (#) the ADC guarded channel(s) is (are) selected using the 
-             ADC_AnalogWatchdogSingleChannelConfig() function.
-         (#) The Analog watchdog lower and higher threshold are configured using the  
-             ADC_AnalogWatchdogThresholdsConfig() function.
-         (#) The Analog watchdog is enabled and configured to enable the check, on one
-             or more channels, using the  ADC_AnalogWatchdogCmd() function.
-         (#) Enable the analog watchdog on the selected channel using
-             ADC_AnalogWatchdogSingleChannelCmd() function
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the analog watchdog 
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the ADCx Analog Watchdog.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the ADC Analog Watchdog */
-    ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
-  }
-  else
-  {
-    /* Disable the ADC Analog Watchdog */
-    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
-  }
-}
-
-/**
-  * @brief  Configures the high and low thresholds of the analog watchdog. 
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  HighThreshold: the ADC analog watchdog High threshold value.
-  *         This parameter must be a 12bit value.
-  * @param  LowThreshold: the ADC analog watchdog Low threshold value.
-  *         This parameter must be a 12bit value.
-  * @retval None
-  */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
-                                        uint16_t LowThreshold)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_THRESHOLD(HighThreshold));
-  assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
-  /* Set the ADCx high and low threshold */
-  ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
-
-}
-
-/**
-  * @brief  Configures the analog watchdog guarded single channel
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.
-  *   This parameter can be one of the following values:
-  *     @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected
-  *     @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected
-  *     @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected
-  *     @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected
-  *     @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected
-  *     @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected
-  *     @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected
-  *     @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected
-  *     @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected
-  *     @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected
-  *     @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected
-  *     @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected
-  *     @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected
-  *     @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected
-  *     @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected
-  *     @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected
-  *     @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected
-  *     @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected
-  *     @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected
-  * @note   The channel selected on the AWDCH must be also set into the CHSELR 
-  *         register 
-  * @retval None
-  */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));
-
-  /* Get the old register value */
-  tmpreg = ADCx->CFGR1;
-
-  /* Clear the Analog watchdog channel select bits */
-  tmpreg &= ~ADC_CFGR1_AWDCH;
-
-  /* Set the Analog watchdog channel */
-  tmpreg |= ADC_AnalogWatchdog_Channel;
-
-  /* Store the new register value */
-  ADCx->CFGR1 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the ADC Analog Watchdog Single Channel.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the ADC Analog Watchdog Single Channel */
-    ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
-  }
-  else
-  {
-    /* Disable the ADC Analog Watchdog Single Channel */
-    ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group4 Temperature Sensor, Vrefint  and Vbat management functions
- *  @brief   Temperature Sensor, Vrefint  and Vbat management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint  and Vbat management function #####
- ===============================================================================
-    [..] This section provides a function allowing to enable/disable the internal 
-         connections between the ADC and the Temperature Sensor, the Vrefint and
-         Vbat source.
-     
-    [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels 
-         voltages is done following these steps :
-         (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources 
-             with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd()
-             functions. 
-         (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint)
-             or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function 
-         (#) Get the voltage values, using ADC_GetConversionValue() function
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the temperature sensor channel.
-  * @param  NewState: new state of the temperature sensor input channel.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_TempSensorCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the temperature sensor channel*/
-    ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
-  }
-  else
-  {
-    /* Disable the temperature sensor channel*/
-    ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
-  }
-}
-
-/**
-  * @brief  Enables or disables the Vrefint channel.
-  * @param  NewState: new state of the Vref input channel.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_VrefintCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the Vrefint channel*/
-    ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
-  }
-  else
-  {
-    /* Disable the Vrefint channel*/
-    ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
-  }
-}
-
-/**
-  * @brief  Enables or disables the Vbat channel.
-  * @param  NewState: new state of the Vbat input channel.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_VbatCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the Vbat channel*/
-    ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
-  }
-  else
-  {
-    /* Disable the Vbat channel*/
-    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group5 Channels Configuration functions
- *  @brief    Channels Configuration functions 
- *
-@verbatim
- ===============================================================================
-            ##### Channels Configuration functions #####
- ===============================================================================
-    [..] This section provides functions allowing to manage the ADC channels,
-         it is composed of 3 sub sections :
-         (#) Configuration and management functions for ADC channels: This subsection 
-             provides functions allowing to configure the ADC channels :    
-             (++) Select the ADC channels
-             (++) Activate ADC Calibration
-             (++) Activate the Overrun Mode.
-             (++) Activate the Discontinuous Mode 
-             (++) Activate the Continuous Mode.
-             (++) Configure the sampling time for each channel
-             (++) Select the conversion Trigger and Edge for ADC channels
-             (++) Select the scan direction.
-             -@@- Please Note that the following features for ADC channels are configurated
-                  using the ADC_Init() function : 
-                  (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd().
-                  (+@@) Select the conversion Trigger and Edge for ADC channels
-                  (+@@) Select the scan direction.
-         (#) Control the ADC peripheral : This subsection permits to command the ADC:
-             (++) Stop or discard an on-going conversion (ADSTP command)
-             (++) Start the ADC conversion .
-         (#) Get the conversion data: This subsection provides an important function in 
-             the ADC peripheral since it returns the converted data of the current 
-             ADC channel. When the Conversion value is read, the EOC Flag is 
-             automatically cleared.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures for the selected ADC and its sampling time.
-  * @param  ADCx: where x can be 1 to select the ADC peripheral.
-  * @param  ADC_Channel: the ADC channel to configure. 
-  *   This parameter can be any combination of the following values:
-  *     @arg ADC_Channel_0: ADC Channel0 selected
-  *     @arg ADC_Channel_1: ADC Channel1 selected
-  *     @arg ADC_Channel_2: ADC Channel2 selected
-  *     @arg ADC_Channel_3: ADC Channel3 selected
-  *     @arg ADC_Channel_4: ADC Channel4 selected
-  *     @arg ADC_Channel_5: ADC Channel5 selected
-  *     @arg ADC_Channel_6: ADC Channel6 selected
-  *     @arg ADC_Channel_7: ADC Channel7 selected
-  *     @arg ADC_Channel_8: ADC Channel8 selected
-  *     @arg ADC_Channel_9: ADC Channel9 selected
-  *     @arg ADC_Channel_10: ADC Channel10 selected
-  *     @arg ADC_Channel_11: ADC Channel11 selected
-  *     @arg ADC_Channel_12: ADC Channel12 selected
-  *     @arg ADC_Channel_13: ADC Channel13 selected
-  *     @arg ADC_Channel_14: ADC Channel14 selected
-  *     @arg ADC_Channel_15: ADC Channel15 selected
-  *     @arg ADC_Channel_16: ADC Channel16 selected
-  *     @arg ADC_Channel_17: ADC Channel17 selected
-  *     @arg ADC_Channel_18: ADC Channel18 selected    
-  * @param  ADC_SampleTime: The sample time value to be set for the selected 
-  *         channel. 
-  *   This parameter can be one of the following values:
-  *     @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles  
-  *     @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles
-  *     @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles
-  *     @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles
-  *     @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles
-  *     @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles
-  *     @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
-  *     @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
-  * @retval None
-  */
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_CHANNEL(ADC_Channel));
-  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
-  /* Configure the ADC Channel */
-  ADCx->CHSELR |= (uint32_t)ADC_Channel;
-
-  /* Clear the Sampling time Selection bits */
-  tmpreg &= ~ADC_SMPR1_SMPR;
-
-  /* Set the ADC Sampling Time register */
-  tmpreg |= (uint32_t)ADC_SampleTime;
-
-  /* Configure the ADC Sample time register */
-  ADCx->SMPR = tmpreg ;
-}
-
-/**
-  * @brief  Enable the Continuous mode for the selected ADCx channels.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the Continuous mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   It is not possible to have both discontinuous mode and continuous mode
-  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
-  *         as if continuous mode was disabled
-  * @retval None
-  */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-    if (NewState != DISABLE)
-  {
-    /* Enable the Continuous mode*/
-    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
-  }
-  else
-  {
-    /* Disable the Continuous mode */
-    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
-  }
-}
-
-/**
-  * @brief  Enable the discontinuous mode for the selected ADC channels.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the discontinuous mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   It is not possible to have both discontinuous mode and continuous mode
-  *         enabled. In this case (If DISCEN and CONT are Set), the ADC behaves 
-  *         as if continuous mode was disabled
-  * @retval None
-  */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-    if (NewState != DISABLE)
-  {
-    /* Enable the Discontinuous mode */
-    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
-  }
-  else
-  {
-    /* Disable the Discontinuous mode */
-    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
-  }
-}
-
-/**
-  * @brief  Enable the Overrun mode for the selected ADC channels.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the Overrun mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-    if (NewState != DISABLE)
-  {
-    /* Enable the Overrun mode */
-    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
-  }
-  else
-  {
-    /* Disable the Overrun mode */
-    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
-  }
-}
-
-/**
-  * @brief  Active the Calibration operation for the selected ADC.
-  * @note   The Calibration can be initiated only when ADC is still in the 
-  *         reset configuration (ADEN must be equal to 0).
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @retval ADC Calibration factor 
-  */
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
-{
-  uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  
-  /* Set the ADC calibartion */
-  ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
-  
-  /* Wait until no ADC calibration is completed */
-  do
-  {
-    calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
-    calibrationcounter++;  
-  } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
-    
-  if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
-  {
-    /*Get the calibration factor from the ADC data register */
-    tmpreg = ADCx->DR;
-  }
-  else
-  {
-    /* Error factor */
-    tmpreg = 0x00000000;
-  }
-  return tmpreg;
-}
-
-/**
-  * @brief  Stop the on going conversions for the selected ADC.
-  * @note   When ADSTP is set, any on going conversion is aborted, and the ADC 
-  *         data register is not updated with current conversion. 
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @retval None
-  */
-void ADC_StopOfConversion(ADC_TypeDef* ADCx)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  
-  ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
-}
-
-/**
-  * @brief  Start Conversion for the selected ADC channels.
-  * @note   In continuous mode, ADSTART is not cleared by hardware with the 
-  *         assertion of EOSEQ because the sequence is automatic relaunched
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @retval None
-  */
-void ADC_StartOfConversion(ADC_TypeDef* ADCx)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  
-  ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
-}
-
-/**
-  * @brief  Returns the last ADCx conversion result data for ADC channel.  
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @retval The Data conversion value.
-  */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
-  /* Return the selected ADC conversion value */
-  return (uint16_t) ADCx->DR;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group6 DMA Configuration functions
- *  @brief   Regular Channels DMA Configuration functions 
- *
-@verbatim
- ===============================================================================
-          ##### DMA Configuration functions #####
- ===============================================================================
-    [..] This section provides functions allowing to configure the DMA for ADC hannels.
-         Since converted channel values are stored into a unique data register, 
-         it is useful to use DMA for conversion of more than one channel. This 
-         avoids the loss of the data already stored in the ADC Data register. 
-         When the DMA mode is enabled (using the ADC_DMACmd() function), after each
-         conversion of a channel, a DMA request is generated.
-  
-    [..] Depending on the "DMA disable selection" configuration (using the 
-         ADC_DMARequestModeConfig() function), at the end of the last DMA 
-         transfer, two possibilities are allowed:
-         (+) No new DMA request is issued to the DMA controller (One Shot Mode) 
-         (+) Requests can continue to be generated (Circular Mode).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified ADC DMA request.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  NewState: new state of the selected ADC DMA transfer.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected ADC DMA request */
-    ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
-  }
-  else
-  {
-    /* Disable the selected ADC DMA request */
-    ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
-  }
-}
-
-/**
-  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_DMARequestMode: the ADC channel to configure. 
-  *   This parameter can be one of the following values:
-  *     @arg ADC_DMAMode_OneShot  : DMA One Shot Mode 
-  *     @arg ADC_DMAMode_Circular : DMA Circular Mode  
-  *  @retval None
-  */
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
-  ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
-  ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions.
- *
-@verbatim   
- ===============================================================================
-            ##### Interrupts and flags management functions #####
- ===============================================================================
-    [..] This section provides functions allowing to configure the ADC Interrupts 
-         and get the status and clear flags and Interrupts pending bits.
-  
-    [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into 
-         3 groups:
-
-  *** Flags for ADC status ***
-  ======================================================
-    [..]
-        (+)Flags :
-           (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1)
-               and when the ADC reaches a state where it is ready to accept conversion requests
-           (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC.
-                The ADC will be effectively ready to operate once the ADRDY flag has been set.
-           (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively
-                disabled.
-           (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of
-                ADC_StopOfConversion() function, at the same time as the ADSTP bit is
-                cleared by hardware
-           (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion
-                is effectively discarded and the ADC is ready to accept a new start conversion
-           (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete.
-
-        (+)Interrupts 
-           (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event.
-
-  *** Flags and Interrupts for ADC channel conversion ***
-  =====================================================
-    [..]
-        (+)Flags :
-           (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion
-                of a channel when a new data result is available in the data register
-           (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion
-                of a sequence of channels selected by ADC_ChannelConfig() function.
-           (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase.
-           (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs,
-                meaning that a new conversion has complete while the EOC flag was already set.
-
-        (+)Interrupts :
-           (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event.
-           (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event.
-           (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event.
-           (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection 
-                event.
-
-  *** Flags and Interrupts for the Analog Watchdog ***
-  ================================================
-    [..]
-        (+)Flags :
-           (##) ADC_FLAG_AWD: This flag is set by hardware when the converted
-                voltage crosses the values programmed thrsholds
-
-        (+)Interrupts :
-           (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog 
-                event.
-  
-    [..] The user should identify which mode will be used in his application to 
-         manage the ADC controller events: Polling mode or Interrupt mode.
-  
-    [..] In the Polling Mode it is advised to use the following functions:
-         (+) ADC_GetFlagStatus() : to check if flags events occur.
-         (+) ADC_ClearFlag()     : to clear the flags events.
-  
-    [..] In the Interrupt Mode it is advised to use the following functions:
-         (+) ADC_ITConfig()       : to enable or disable the interrupt source.
-         (+) ADC_GetITStatus()    : to check if Interrupt occurs.
-         (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
-             (corresponding Flag).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified ADC interrupts.
-  * @param  ADCx: where x can be 1 to select the ADC peripheral.
-  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:
-  *     @arg ADC_IT_ADRDY: ADC ready interrupt 
-  *     @arg ADC_IT_EOSMP: End of sampling interrupt
-  *     @arg ADC_IT_EOC: End of conversion interrupt 
-  *     @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
-  *     @arg ADC_IT_OVR: overrun interrupt
-  *     @arg ADC_IT_AWD: Analog watchdog interrupt
-  * @param  NewState: new state of the specified ADC interrupts.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_ADC_CONFIG_IT(ADC_IT)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected ADC interrupts */
-    ADCx->IER |= ADC_IT;
-  }
-  else
-  {
-    /* Disable the selected ADC interrupts */
-    ADCx->IER &= (~(uint32_t)ADC_IT);
-  }
-}
-
-/**
-  * @brief  Checks whether the specified ADC flag is set or not.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_FLAG: specifies the flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg ADC_FLAG_AWD: Analog watchdog flag
-  *     @arg ADC_FLAG_OVR: Overrun flag 
-  *     @arg ADC_FLAG_EOSEQ: End of Sequence flag
-  *     @arg ADC_FLAG_EOC: End of conversion flag
-  *     @arg ADC_FLAG_EOSMP: End of sampling flag
-  *     @arg ADC_FLAG_ADRDY: ADC Ready flag
-  *     @arg ADC_FLAG_ADEN: ADC enable flag 
-  *     @arg ADC_FLAG_ADDIS: ADC disable flag 
-  *     @arg ADC_FLAG_ADSTART: ADC start flag 
-  *     @arg ADC_FLAG_ADSTP: ADC stop flag
-  *     @arg ADC_FLAG_ADCAL: ADC Calibration flag
-  * @retval The new state of ADC_FLAG (SET or RESET).
-  */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
-  if((uint32_t)(ADC_FLAG & 0x01000000))
-  {
-    tmpreg = ADCx->CR & 0xFEFFFFFF;
-  }
-  else
-  {
-    tmpreg = ADCx->ISR;
-  }
-  
-  /* Check the status of the specified ADC flag */
-  if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
-  {
-    /* ADC_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* ADC_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the ADC_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the ADCx's pending flags.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg ADC_FLAG_AWD: Analog watchdog flag
-  *     @arg ADC_FLAG_EOC: End of conversion flag
-  *     @arg ADC_FLAG_ADRDY: ADC Ready flag
-  *     @arg ADC_FLAG_EOSMP: End of sampling flag
-  *     @arg ADC_FLAG_EOSEQ: End of Sequence flag
-  *     @arg ADC_FLAG_OVR: Overrun flag 
-  * @retval None
-  */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
-  /* Clear the selected ADC flags */
-  ADCx->ISR = (uint32_t)ADC_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified ADC interrupt has occurred or not.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral
-  * @param  ADC_IT: specifies the ADC interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg ADC_IT_ADRDY: ADC ready interrupt 
-  *     @arg ADC_IT_EOSMP: End of sampling interrupt
-  *     @arg ADC_IT_EOC: End of conversion interrupt 
-  *     @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
-  *     @arg ADC_IT_OVR: overrun interrupt
-  *     @arg ADC_IT_AWD: Analog watchdog interrupt
-  * @retval The new state of ADC_IT (SET or RESET).
-  */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_GET_IT(ADC_IT));
-
-  /* Get the ADC_IT enable bit status */
-  enablestatus = (uint32_t)(ADCx->IER & ADC_IT); 
-
-  /* Check the status of the specified ADC interrupt */
-  if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
-  {
-    /* ADC_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* ADC_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the ADC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the ADCx's interrupt pending bits.
-  * @param  ADCx: where x can be 1 to select the ADC1 peripheral.
-  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
-  *   This parameter can be one of the following values:
-  *     @arg ADC_IT_ADRDY: ADC ready interrupt
-  *     @arg ADC_IT_EOSMP: End of sampling interrupt
-  *     @arg ADC_IT_EOC: End of conversion interrupt
-  *     @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
-  *     @arg ADC_IT_OVR: overrun interrupt
-  *     @arg ADC_IT_AWD: Analog watchdog interrupt
-  * @retval None
-  */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_PERIPH(ADCx));
-  assert_param(IS_ADC_CLEAR_IT(ADC_IT));
-
-  /* Clear the selected ADC interrupt pending bits */
-  ADCx->ISR = (uint32_t)ADC_IT; 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c

@@ -1,606 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_cec.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Consumer Electronics Control (CEC) peripheral:
-  *            + Initialization and Configuration
-  *            + Data transfers functions
-  *            + Interrupts and flags management
-  *               
-  *  @verbatim
-  ==============================================================================
-                            ##### CEC features #####
-  ==============================================================================
-      [..] This device provides some features:
-           (#) Supports HDMI-CEC specification 1.4.
-           (#) Supports two source clocks(HSI/244 or LSE).
-           (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
-               It can genarate an interrupt in the CEC clock domain that the CPU 
-               wakes up from the low power mode.
-           (#) Configurable Signal Free Time before of transmission start. The 
-               number of nominal data bit periods waited before transmission can be
-               ruled by Hardware or Software.
-           (#) Configurable Peripheral Address (multi-addressing configuration).
-           (#) Supports listen mode.The CEC Messages addressed to different destination
-               can be received without interfering with CEC bus when Listen mode option is enabled.
-           (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
-           (#) Error detection with configurable error bit generation.
-           (#) Arbitration lost error in the case of two CEC devices starting at the same time.
-
-                            ##### How to use this driver ##### 
-  ==============================================================================
-      [..] This driver provides functions to configure and program the CEC device,
-       follow steps below:
-           (#) The source clock can be configured using:
-               (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default) 
-               (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
-           (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
-           (#) Peripherals alternate function.
-               (++) Connect the pin to the desired peripherals' Alternate Function (AF) using 
-               GPIO_PinAFConfig() function.
-               (++) Configure the desired pin in alternate function by:
-               GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
-               (++) Select the type open-drain and output speed via GPIO_OType 
-               and GPIO_Speed members.
-               (++) Call GPIO_Init() function.
-           (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation 
-               and Bit error generation using the CEC_Init() function.
-               The function CEC_Init() must be called when the CEC peripheral is disabled.
-           (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
-           (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
-           (#) Enable the NVIC and the corresponding interrupt using the function 
-               CEC_ITConfig() if you need to use interrupt mode.
-               CEC_ITConfig() must be called before enabling the CEC peripheral.
-           (#) Enable the CEC using the CEC_Cmd() function.
-           (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
-           (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage() 
-           (#) Transmit single data through the CEC peripheral using CEC_SendDataByte() 
-               and Receive the last transmitted byte using CEC_ReceiveDataByte().
-           (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
-      [..]
-           (@) If the listen mode is enabled, Stop reception generation and Bit error generation 
-               must be in reset state.
-           (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
-               must be called before CEC_StartOfMessage().
-  
-   @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_cec.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CEC 
-  * @brief CEC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BROADCAST_ADDRESS      ((uint32_t)0x0000F)
-#define CFGR_CLEAR_MASK        ((uint32_t)0x7000FE00)   /* CFGR register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Private_Functions 
-  * @{
-  */
-
-/** @defgroup CEC_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions
- *
-@verbatim  
- ===============================================================================
-                            ##### Initialization and Configuration functions #####
- ===============================================================================
-      [..] This section provides functions allowing to initialize:
-            (+) CEC own addresses
-            (+) CEC Signal Free Time
-            (+) CEC Rx Tolerance
-            (+) CEC Stop Reception
-            (+) CEC Bit Rising Error
-            (+) CEC Long Bit Period Error
-      [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
-           Messages addressed to different destination can be received when Listen mode is 
-           enabled without interfering with CEC bus.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the CEC peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void CEC_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
-}
-
-/**
-  * @brief  Initializes the CEC peripheral according to the specified parameters
-  *         in the CEC_InitStruct.
-  * @note   The CEC parameters must be configured before enabling the CEC peripheral.
-  * @param  CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
-  *         the configuration information for the specified CEC peripheral.
-  * @retval None
-  */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
-  assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
-  assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
-  assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
-  assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
-  assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
-  assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
-
-  /* Get the CEC CFGR value */
-  tmpreg = CEC->CFGR;
-
-  /* Clear CFGR bits */
-  tmpreg &= CFGR_CLEAR_MASK;
-
-  /* Configure the CEC peripheral */
-  tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
-             CEC_InitStruct->CEC_StopReception  | CEC_InitStruct->CEC_BitRisingError |
-             CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
-             CEC_InitStruct->CEC_SFTOption);
-
-  /* Write to CEC CFGR  register */
-  CEC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Fills each CEC_InitStruct member with its default value.
-  * @param  CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
-{
-  CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
-  CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
-  CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
-  CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
-  CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
-  CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
-  CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
-}
-
-/**
-  * @brief  Enables or disables the CEC peripheral.
-  * @param  NewState: new state of the CEC peripheral.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_Cmd(FunctionalState NewState)
-{
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the CEC peripheral */
-    CEC->CR |= CEC_CR_CECEN;
-  }
-  else
-  {
-    /* Disable the CEC peripheral */
-    CEC->CR &= ~CEC_CR_CECEN;
-  }
-}
-
-/**
-  * @brief  Enables or disables the CEC Listen Mode.
-  * @param  NewState: new state of the Listen Mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_ListenModeCmd(FunctionalState NewState)
-{
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the Listen Mode */
-    CEC->CFGR |= CEC_CFGR_LSTN;
-  }
-  else
-  {
-    /* Disable the Listen Mode */
-    CEC->CFGR &= ~CEC_CFGR_LSTN;
-  }
-}
-
-/**
-  * @brief  Defines the Own Address of the CEC device.
-  * @param  CEC_OwnAddress: The CEC own address.
-  * @retval None
-  */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
-  uint32_t tmp =0x00;
-  /* Check the parameters */
-  assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
-  tmp = 1 <<(CEC_OwnAddress + 16);
-  /* Set the CEC own address */
-  CEC->CFGR |= tmp;
-}
-
-/**
-  * @brief  Clears the Own Address of the CEC device.
-  * @param  CEC_OwnAddress: The CEC own address.
-  * @retval None
-  */
-void CEC_OwnAddressClear(void)
-{
-  /* Set the CEC own address */
-  CEC->CFGR = 0x0;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Group2 Data transfers functions
- *  @brief    Data transfers functions
- *
-@verbatim
- ===============================================================================
-                            ##### Data transfers functions #####
- ===============================================================================
-    [..] This section provides functions allowing the CEC data transfers.The read 
-         access of the CEC_RXDR register can be done using the CEC_ReceiveData()function 
-         and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be 
-         done using CEC_SendData() function.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits single data through the CEC peripheral.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void CEC_SendData(uint8_t Data)
-{
-  /* Transmit Data */
-  CEC->TXDR = Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the CEC peripheral.
-  * @param  None
-  * @retval The received data.
-  */
-uint8_t CEC_ReceiveData(void)
-{
-  /* Receive Data */
-  return (uint8_t)(CEC->RXDR);
-}
-
-/**
-  * @brief  Starts a new message.
-  * @param  None
-  * @retval None
-  */
-void CEC_StartOfMessage(void)
-{
-  /* Starts of new message */
-  CEC->CR |= CEC_CR_TXSOM; 
-}
-
-/**
-  * @brief  Transmits message with an EOM bit.
-  * @param  None.
-  * @retval None
-  */
-void CEC_EndOfMessage(void)
-{
-  /* The data byte will be transmitted with an EOM bit */
-  CEC->CR |= CEC_CR_TXEOM;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Group3 Interrupts and flags management functions
- *  @brief    Interrupts and flags management functions
-*
-@verbatim
- ===============================================================================
-                            ##### Interrupts and flags management functions ##### 
- ===============================================================================
-    [..] This section provides functions allowing to configure the CEC Interrupts
-         sources and check or clear the flags or pending bits status.
-    [..] The user should identify which mode will be used in his application to manage
-         the communication: Polling mode or Interrupt mode.
-  
-    [..] In polling mode, the CEC can be managed by the following flags:
-            (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
-            (+) CEC_FLAG_TXERR  : to indicate an error occurs during transmission mode.
-                                  The initiator detects low impedance in the CEC line.
-            (+) CEC_FLAG_TXUDR  : to indicate if an underrun error occurs in transmission mode.
-                                  The transmission is enabled while the software has not yet 
-                                  loaded any value into the TXDR register.
-            (+) CEC_FLAG_TXEND  : to indicate the end of successful transmission.
-            (+) CEC_FLAG_TXBR   : to indicate the next transmission data has to be written to TXDR.
-            (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
-                                  starting at the same time.
-            (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
-            (+) CEC_FLAG_LBPE   : to indicate a long bit period error generated during receive mode.
-            (+) CEC_FLAG_SBPE   : to indicate a short bit period error generated during receive mode.
-            (+) CEC_FLAG_BRE    : to indicate a bit rising error generated during receive mode.
-            (+) CEC_FLAG_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
-                                  A byte is not yet received while a new byte is stored in the RXDR register.
-            (+) CEC_FLAG_RXEND  : to indicate the end Of reception
-            (+) CEC_FLAG_RXBR   : to indicate a new byte has been received from the CEC line and 
-                                  stored into the RXDR buffer.
-    [..]
-           (@)In this Mode, it is advised to use the following functions:
-              FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-              void CEC_ClearFlag(uint16_t CEC_FLAG);
-
-    [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
-           (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge 
-           (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
-           (+) CEC_IT_TXERR  : to indicate an error occurs during transmission mode.
-                               The initiator detects low impedance in the CEC line.
-           (+) CEC_IT_TXUDR  : to indicate if an underrun error occurs in transmission mode.
-                               The transmission is enabled while the software has not yet 
-                               loaded any value into the TXDR register.
-           (+) CEC_IT_TXEND  : to indicate the end of successful transmission.
-           (+) CEC_IT_TXBR   : to indicate the next transmission data has to be written to TXDR register.
-           (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
-                                starting at the same time.
-           (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
-           (+) CEC_IT_LBPE   : to indicate a long bit period error generated during receive mode.
-           (+) CEC_IT_SBPE   : to indicate a short bit period error generated during receive mode.
-           (+) CEC_IT_BRE    : to indicate a bit rising error generated during receive mode.
-           (+) CEC_IT_RXOVR  : to indicate if an overrun error occur while receiving a CEC message.
-                               A byte is not yet received while a new byte is stored in the RXDR register.
-           (+) CEC_IT_RXEND  : to indicate the end Of reception
-           (+) CEC_IT_RXBR   : to indicate a new byte has been received from the CEC line and 
-                                stored into the RXDR buffer.
-    [..]
-           (@)In this Mode it is advised to use the following functions:
-              void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
-              ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-              void CEC_ClearITPendingBit(uint16_t CEC_IT);
-              
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the selected CEC interrupts.
-  * @param  CEC_IT: specifies the CEC interrupt source to be enabled.
-  *         This parameter can be any combination of the following values:
-  *     @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
-  *     @arg CEC_IT_TXERR: Tx Error.
-  *     @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
-  *     @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
-  *     @arg CEC_IT_TXBR: Tx-Byte Request.
-  *     @arg CEC_IT_ARBLST: Arbitration Lost
-  *     @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
-  *     @arg CEC_IT_LBPE: Rx Long period Error
-  *     @arg CEC_IT_SBPE: Rx Short period Error
-  *     @arg CEC_IT_BRE: Rx Bit Rising Error
-  *     @arg CEC_IT_RXOVR: Rx Overrun.
-  *     @arg CEC_IT_RXEND: End Of Reception
-  *     @arg CEC_IT_RXBR: Rx-Byte Received
-  * @param  NewState: new state of the selected CEC interrupts.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
-{
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_CEC_IT(CEC_IT));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected CEC interrupt */
-    CEC->IER |= CEC_IT;
-  }
-  else
-  {
-    CEC_IT =~CEC_IT;
-    /* Disable the selected CEC interrupt */
-    CEC->IER &= CEC_IT;
-  }
-}
-
-/**
-  * @brief  Gets the CEC flag status.
-  * @param  CEC_FLAG: specifies the CEC flag to check.
-  *     This parameter can be one of the following values:
-  *     @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
-  *     @arg CEC_FLAG_TXERR: Tx Error.
-  *     @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
-  *     @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
-  *     @arg CEC_FLAG_TXBR: Tx-Byte Request.
-  *     @arg CEC_FLAG_ARBLST: Arbitration Lost
-  *     @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 
-  *     @arg CEC_FLAG_LBPE: Rx Long period Error
-  *     @arg CEC_FLAG_SBPE: Rx Short period Error
-  *     @arg CEC_FLAG_BRE: Rx Bit Rissing Error
-  *     @arg CEC_FLAG_RXOVR: Rx Overrun.
-  *     @arg CEC_FLAG_RXEND: End Of Reception.
-  *     @arg CEC_FLAG_RXBR: Rx-Byte Received.
-  * @retval The new state of CEC_FLAG (SET or RESET)
-  */
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG) 
-{
-  FlagStatus bitstatus = RESET;
-  
-  assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
-  
-  /* Check the status of the specified CEC flag */
-  if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
-  {
-    /* CEC flag is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC flag is reset */
-    bitstatus = RESET;
-  }
-
-  /* Return the CEC flag status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's pending flags.
-  * @param  CEC_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
-  *     @arg CEC_FLAG_TXERR: Tx Error
-  *     @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
-  *     @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
-  *     @arg CEC_FLAG_TXBR: Tx-Byte Request
-  *     @arg CEC_FLAG_ARBLST: Arbitration Lost
-  *     @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge 
-  *     @arg CEC_FLAG_LBPE: Rx Long period Error
-  *     @arg CEC_FLAG_SBPE: Rx Short period Error
-  *     @arg CEC_FLAG_BRE: Rx Bit Rising Error
-  *     @arg CEC_FLAG_RXOVR: Rx Overrun
-  *     @arg CEC_FLAG_RXEND: End Of Reception
-  *     @arg CEC_FLAG_RXBR: Rx-Byte Received
-  * @retval None
-  */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{
-  assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
-  /* Clear the selected CEC flag */
-  CEC->ISR = CEC_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified CEC interrupt has occurred or not.
-  * @param  CEC_IT: specifies the CEC interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
-  *     @arg CEC_IT_TXERR: Tx Error.
-  *     @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
-  *     @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
-  *     @arg CEC_IT_TXBR: Tx-Byte Request.
-  *     @arg CEC_IT_ARBLST: Arbitration Lost.
-  *     @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
-  *     @arg CEC_IT_LBPE: Rx Long period Error.
-  *     @arg CEC_IT_SBPE: Rx Short period Error.
-  *     @arg CEC_IT_BRE: Rx Bit Rising Error.
-  *     @arg CEC_IT_RXOVR: Rx Overrun.
-  *     @arg CEC_IT_RXEND: End Of Reception.
-  *     @arg CEC_IT_RXBR: Rx-Byte Received 
-  * @retval The new state of CEC_IT (SET or RESET).
-  */
-ITStatus CEC_GetITStatus(uint16_t CEC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_CEC_GET_IT(CEC_IT));
-
-  /* Get the CEC IT enable bit status */
-  enablestatus = (CEC->IER & CEC_IT);
-
-  /* Check the status of the specified CEC interrupt */
-  if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
-  {
-    /* CEC interrupt is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* CEC interrupt is reset */
-    bitstatus = RESET;
-  }
-
-  /* Return the CEC interrupt status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the CEC's interrupt pending bits.
-  * @param  CEC_IT: specifies the CEC interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
-  *     @arg CEC_IT_TXERR: Tx Error
-  *     @arg CEC_IT_TXUDR: Tx-Buffer Underrun
-  *     @arg CEC_IT_TXEND: End of Transmission
-  *     @arg CEC_IT_TXBR: Tx-Byte Request
-  *     @arg CEC_IT_ARBLST: Arbitration Lost
-  *     @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
-  *     @arg CEC_IT_LBPE: Rx Long period Error
-  *     @arg CEC_IT_SBPE: Rx Short period Error
-  *     @arg CEC_IT_BRE: Rx Bit Rising Error
-  *     @arg CEC_IT_RXOVR: Rx Overrun
-  *     @arg CEC_IT_RXEND: End Of Reception
-  *     @arg CEC_IT_RXBR: Rx-Byte Received
-  * @retval None
-  */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
-  assert_param(IS_CEC_IT(CEC_IT));
-
-  /* Clear the selected CEC interrupt pending bits */
-  CEC->ISR = CEC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c

@@ -1,409 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_comp.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the comparators (COMP1 and COMP2) peripheral: 
-  *           + Comparators configuration
-  *           + Window mode control
-  *
-  *  @verbatim
-  *
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]           
-   
-         The device integrates two analog comparators COMP1 and COMP2:
-         (+) The non inverting input is set to PA1 for COMP1 and to PA3
-             for COMP2.
-  
-         (+) The inverting input can be selected among: DAC_OUT1, 
-             1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
-             I/O (PA0 for COMP1 and PA2 for COMP2)
-  
-         (+) The COMP output is internally is available using COMP_GetOutputLevel()
-             and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
-             and PA2, PA7, PA12 for COMP2
-  
-         (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
-             and TIM3)
-  
-         (+) The two comparators COMP1 and COMP2 can be combined in window
-             mode and only COMP1 non inverting (PA1) can be used as non-
-             inverting input.
-  
-         (+) The two comparators COMP1 and COMP2 have interrupt capability 
-             with wake-up from Sleep and Stop modes (through the EXTI controller).
-             COMP1 and COMP2 outputs are internally connected to EXTI Line 21
-             and EXTI Line 22 respectively.
-                   
-
-                     ##### How to configure the comparator #####
- ===============================================================================
-    [..] 
-           This driver provides functions to configure and program the Comparators 
-           of all STM32F0xx devices.
-             
-    [..]   To use the comparator, perform the following steps:
-  
-         (#) Enable the SYSCFG APB clock to get write access to comparator
-             register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-  
-         (#) Configure the comparator input in analog mode using GPIO_Init()
-  
-         (#) Configure the comparator output in alternate function mode
-             using GPIO_Init() and use GPIO_PinAFConfig() function to map the
-             comparator output to the GPIO pin
-  
-         (#) Configure the comparator using COMP_Init() function:
-                 (++)  Select the inverting input
-                 (++)  Select the output polarity  
-                 (++)  Select the output redirection
-                 (++)  Select the hysteresis level
-                 (++)  Select the power mode
-    
-         (#) Enable the comparator using COMP_Cmd() function
-  
-         (#) If required enable the COMP interrupt by configuring and enabling
-             EXTI line in Interrupt mode and selecting the desired sensitivity
-             level using EXTI_Init() function. After that enable the comparator
-             interrupt vector using NVIC_Init() function.
-  
-     @endverbatim
-  *    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_comp.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup COMP 
-  * @brief COMP driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CSR register Mask */
-#define COMP_CSR_CLEAR_MASK              ((uint32_t)0x00003FFE)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Functions
-  * @{
-  */
-
-/** @defgroup COMP_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
- ===============================================================================
-               ##### Initialization and Configuration functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-   
-/**
-  * @brief  Deinitializes COMP peripheral registers to their default reset values.
-  * @note   Deinitialization can't be performed if the COMP configuration is locked.
-  *         To unlock the configuration, perform a system reset.
-  * @param  None
-  * @retval None
-  */
-void COMP_DeInit(void)
-{
-  COMP->CSR = ((uint32_t)0x00000000);    /*!< Set COMP_CSR register to reset value */
-}
-
-/**
-  * @brief  Initializes the COMP peripheral according to the specified parameters
-  *         in COMP_InitStruct
-  * @note   If the selected comparator is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @note   By default, PA1 is selected as COMP1 non inverting input.
-  *         To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
-  * @param  COMP_Selection: the selected comparator. 
-  *   This parameter can be one of the following values:
-  *     @arg COMP_Selection_COMP1: COMP1 selected
-  *     @arg COMP_Selection_COMP2: COMP2 selected
-  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains 
-  *         the configuration information for the specified COMP peripheral.
-  *
-  * @retval None
-  */
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-  assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
-  assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
-  assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
-  assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
-  assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
-
-  /*!< Get the COMP_CSR register value */
-  tmpreg = COMP->CSR;
-
-  /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */ 
-  tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
-
-  /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
-  /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
-  /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
-  /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
-  /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
-  /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */   
-  tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
-                       COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
-                       COMP_InitStruct->COMP_Mode)<<COMP_Selection);
-
-  /*!< Write to COMP_CSR register */
-  COMP->CSR = tmpreg;  
-}
-
-/**
-  * @brief  Fills each COMP_InitStruct member with its default value.
-  * @param  COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
-{
-  COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
-  COMP_InitStruct->COMP_Output = COMP_Output_None;
-  COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
-  COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
-  COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
-}
-
-/**
-  * @brief  Enable or disable the COMP peripheral.
-  * @note   If the selected comparator is locked, enable/disable can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @param  COMP_Selection: the selected comparator.
-  *   This parameter can be one of the following values:
-  *     @arg COMP_Selection_COMP1: COMP1 selected
-  *     @arg COMP_Selection_COMP2: COMP2 selected
-  * @param  NewState: new state of the COMP peripheral.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When enabled, the comparator compares the non inverting input with 
-  *                       the inverting input and the comparison result is available
-  *                       on comparator output.
-  * @note   When disabled, the comparator doesn't perform comparison and the 
-  *                        output level is low.
-  * @retval None
-  */
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected COMP peripheral */
-    COMP->CSR |= (uint32_t) (1<<COMP_Selection);
-  }
-  else
-  {
-    /* Disable the selected COMP peripheral  */
-    COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
-  }
-}
-
-/**
-  * @brief  Close or Open the SW1 switch.
-  * @note   This switch is solely intended to redirect signals onto high
-  *         impedance input, such as COMP1 non-inverting input (highly resistive switch)
-  * @param  NewState: New state of the analog switch.
-  *   This parameter can be: ENABLE or DISABLE. 
-  * @note   When enabled, the SW1 is closed; PA1 is connected to PA4
-  * @note   When disabled, the SW1 switch is open; PA1 is disconnected from PA4
-  * @retval None
-  */
-void COMP_SwitchCmd(FunctionalState NewState)
-{
-  /* Check the parameter */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Close SW1 switch */
-    COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
-  }
-  else
-  {
-    /* Open SW1 switch */
-    COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
-  }
-}
-
-/**
-  * @brief  Return the output level (high or low) of the selected comparator. 
-  * @note   The output level depends on the selected polarity.
-  *         If the polarity is not inverted:
-  * @note     -Comparator output is low when the non-inverting input is at a lower
-  *            voltage than the inverting input
-  * @note     -Comparator output is high when the non-inverting input is at a higher
-  *            voltage than the inverting input
-  * @note   If the polarity is inverted:
-  * @note     -Comparator output is high when the non-inverting input is at a lower
-  *            voltage than the inverting input
-  * @note     -Comparator output is low when the non-inverting input is at a higher
-  *            voltage than the inverting input
-  * @param  COMP_Selection: the selected comparator. 
-  *   This parameter can be one of the following values:
-  *     @arg COMP_Selection_COMP1: COMP1 selected
-  *     @arg COMP_Selection_COMP2: COMP2 selected  
-  * @retval Returns the selected comparator output level: low or high.
-  *       
-  */
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
-{
-  uint32_t compout = 0x0;
-
-  /* Check the parameters */
-  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
-  /* Check if selected comparator output is high */
-  if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
-  {
-    compout = COMP_OutputLevel_High;
-  }
-  else
-  {
-    compout = COMP_OutputLevel_Low;
-  }
-
-  /* Return the comparator output level */
-  return (uint32_t)(compout);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Group2 Window mode control function
- *  @brief   Window mode control function 
- *
-@verbatim   
- ===============================================================================
-                     ##### Window mode control function #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the window mode.
-  *         In window mode, COMP1 and COMP2 non inverting inputs are connected
-  *         together and only COMP1 non inverting input (PA1) can be used.
-  * param   NewState: new state of the window mode.
-  *   This parameter can be :
-  *           @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
-  *           @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
-  * @retval None
-  */
-void COMP_WindowCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the window mode */
-    COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
-  }
-  else
-  {
-    /* Disable the window mode */
-    COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Group3 COMP configuration locking function
- *  @brief   COMP1 and COMP2 configuration locking function
- *           COMP1 and COMP2 configuration can be locked each separately.
- *           Unlocking is performed by system reset.
- *
-@verbatim   
- ===============================================================================
-                     ##### Configuration Lock function #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected comparator (COMP1/COMP2) configuration.
-  * @note   Locking the configuration means that all control bits are read-only.
-  *         To unlock the comparator configuration, perform a system reset.
-  * @param  COMP_Selection: selects the comparator to be locked 
-  *   This parameter can be a value of the following values:
-  *     @arg COMP_Selection_COMP1: COMP1 configuration is locked.
-  *     @arg COMP_Selection_COMP2: COMP2 configuration is locked.  
-  * @retval None
-  */
-void COMP_LockConfig(uint32_t COMP_Selection)
-{
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
-  /* Set the lock bit corresponding to selected comparator */
-  COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c

@@ -1,288 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_crc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of CRC computation unit peripheral:
-  *            + Configuration of the CRC computation unit
-  *            + CRC computation of one/many 32-bit data
-  *            + CRC Independent register (IDR) access
-  *
-  *  @verbatim
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]
-    
-         (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
-             function
-         (+) If required, select the reverse operation on input data 
-             using CRC_ReverseInputDataSelect()  
-         (+) If required, enable the reverse operation on output data
-             using CRC_ReverseOutputDataCmd(Enable)
-         (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
-             or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit 
-             data buffer
-            (@) To compute the CRC of a new data use CRC_ResetDR() to reset
-                 the CRC computation unit before starting the computation
-                 otherwise you can get wrong CRC values.
-      
-     @endverbatim
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_crc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup CRC 
-  * @brief CRC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
-  * @{
-  */
-
-/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
- *  @brief   Configuration of the CRC computation unit functions 
- *
-@verbatim
- ===============================================================================
-                     ##### CRC configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes CRC peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void CRC_DeInit(void)
-{
-  /* Set DR register to reset value */
-  CRC->DR = 0xFFFFFFFF;
-  /* Reset IDR register */
-  CRC->IDR = 0x00;
-  /* Set INIT register to reset value */
-  CRC->INIT = 0xFFFFFFFF;
-  /* Reset the CRC calculation unit */
-  CRC->CR = CRC_CR_RESET;
-}
-
-/**
-  * @brief  Resets the CRC calculation unit and sets INIT register content in DR register.
-  * @param  None
-  * @retval None
-  */
-void CRC_ResetDR(void)
-{
-  /* Reset CRC generator */
-  CRC->CR = CRC_CR_RESET;
-}
-
-/**
-  * @brief  Selects the reverse operation to be performed on input data.
-  * @param  CRC_ReverseInputData: Specifies the reverse operation on input data.
-  *         This parameter can be:
-  *      @arg CRC_ReverseInputData_No: No reverse operation is performed
-  *      @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
-  *      @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
-  *      @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
-  * @retval None
-  */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
-{
-  uint32_t tmpcr = 0;
-
-  /* Check the parameter */
-  assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
-
-  /* Get CR register value */
-  tmpcr = CRC->CR;
-
-  /* Reset REV_IN bits */
-  tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
-  /* Set the reverse operation */
-  tmpcr |= (uint32_t)CRC_ReverseInputData;
-
-  /* Write to CR register */
-  CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
-  * @brief  Enables or disable the reverse operation on output data.
-  *         The reverse operation on output data is performed on 32-bit.
-  * @param  NewState: new state of the reverse operation on output data.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void CRC_ReverseOutputDataCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable reverse operation on output data */
-    CRC->CR |= CRC_CR_REV_OUT;
-  }
-  else
-  {
-    /* Disable reverse operation on output data */
-    CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
-  }
-}
-
-/**
-  * @brief  Initializes the INIT register.
-  * @note   After resetting CRC calculation unit, CRC_InitValue is stored in DR register
-  * @param  CRC_InitValue: Programmable initial CRC value
-  * @retval None
-  */
-void CRC_SetInitRegister(uint32_t CRC_InitValue)
-{
-  CRC->INIT = CRC_InitValue;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
- *  @brief   CRC computation of one/many 32-bit data functions
- *
-@verbatim
- ===============================================================================
-                     ##### CRC computation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
-  * @param  CRC_Data: data word(32-bit) to compute its CRC
-  * @retval 32-bit CRC
-  */
-uint32_t CRC_CalcCRC(uint32_t CRC_Data)
-{
-  CRC->DR = CRC_Data;
-  
-  return (CRC->DR);
-}
-
-/**
-  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
-  * @param  pBuffer: pointer to the buffer containing the data to be computed
-  * @param  BufferLength: length of the buffer to be computed
-  * @retval 32-bit CRC
-  */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index = 0;
-  
-  for(index = 0; index < BufferLength; index++)
-  {
-    CRC->DR = pBuffer[index];
-  }
-  return (CRC->DR);
-}
-
-/**
-  * @brief  Returns the current CRC value.
-  * @param  None
-  * @retval 32-bit CRC
-  */
-uint32_t CRC_GetCRC(void)
-{
-  return (CRC->DR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
- *  @brief   CRC Independent Register (IDR) access (write/read) functions
- *
-@verbatim
- ===============================================================================
-           ##### CRC Independent Register (IDR) access functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Stores an 8-bit data in the Independent Data(ID) register.
-  * @param  CRC_IDValue: 8-bit value to be stored in the ID register 					
-  * @retval None
-  */
-void CRC_SetIDRegister(uint8_t CRC_IDValue)
-{
-  CRC->IDR = CRC_IDValue;
-}
-
-/**
-  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
-  * @param  None
-  * @retval 8-bit value of the ID register 
-  */
-uint8_t CRC_GetIDRegister(void)
-{
-  return (CRC->IDR);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c

@@ -1,537 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dac.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral:
-  *           + DAC channel configuration: trigger, output buffer, data format
-  *           + DMA management
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
-  *
- ===============================================================================
-                        ##### DAC Peripheral features #####
- ===============================================================================
-    [..] The device integrates one 12-bit Digital Analog Converters refered as
-         DAC channel1 with DAC_OUT1 (PA4) as output
-  
-    [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
-         and DAC_OUT1 is available once writing to DHRx register using 
-         DAC_SetChannel1Data().
-  
-    [..] Digital to Analog conversion can be triggered by:
-         (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
-             The used pin (GPIOx_Pin9) must be configured in input mode.
-  
-         (#) Timers TRGO: TIM2, TIM3, TIM6 and TIM15 
-             (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
-             The timer TRGO event should be selected using TIM_SelectOutputTrigger()
-  
-         (#) Software using DAC_Trigger_Software
-  
-    [..] The DAC channel 1 integrates an output buffer that can be used to 
-         reduce the output impedance, and to drive external loads directly
-         without having to add an external operational amplifier.
-         To enable the output buffer use  
-         DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-  
-    [..] Refer to the device datasheet for more details about output impedance
-         value with and without output buffer.
-  
-    [..] The DAC data format can be:
-         (#) 8-bit right alignment using DAC_Align_8b_R
-         (#) 12-bit left alignment using DAC_Align_12b_L
-         (#) 12-bit right alignment using DAC_Align_12b_R
-  
-    [..] The analog output voltage on each DAC channel pin is determined
-         by the following equation: DAC_OUTx = VREF+ * DOR / 4095
-         with  DOR is the Data Output Register
-         VEF+ is the input voltage reference (refer to the device datasheet)
-         e.g. To set DAC_OUT1 to 0.7V, use
-         DAC_SetChannel1Data(DAC_Align_12b_R, 868);
-         Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-    [..] A DMA1 request can be generated when an external trigger (but not
-         a software trigger) occurs if DMA1 requests are enabled using
-         DAC_DMACmd()
-         DMA1 requests are mapped as following:
-         (+) DAC channel1 is mapped on DMA1 channel3 which must be already 
-             configured
-    
-                      ##### How to use this driver #####
- ===============================================================================
-    [..]
-         (+) Enable DAC APB1 clock to get write access to DAC registers
-             using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
-              
-         (+) Configure DAC_OUT1 (DAC_OUT1: PA4) in analog mode
-             using GPIO_Init() function  
-              
-         (+) Configure the DAC channel using DAC_Init()
-              
-         (+) Enable the DAC channel using DAC_Cmd()
-  
-    @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dac.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DAC 
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CR register Mask */
-#define CR_CLEAR_MASK              ((uint32_t)0x0000003E)
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
-
-/* DOR register offset */
-#define DOR_OFFSET                 ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
-  * @{
-  */ 
-
-/** @defgroup DAC_Group1 DAC channels configuration
- *  @brief   DAC channels configuration: trigger, output buffer, data format 
- *
-@verbatim
- ===============================================================================
-  ##### DAC channels configuration: trigger, output buffer, data format #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void DAC_DeInit(void)
-{
-  /* Enable DAC reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
-  /* Release DAC from reset state */
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
-  * @brief  Initializes the DAC peripheral according to the specified 
-  *         parameters in the DAC_InitStruct.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
-  *         contains the configuration information for the specified DAC channel.
-  *
-  * @retval None
-  */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-  /*---------------------------- DAC CR Configuration ------------------------*/
-  /* Get the DAC CR value */
-  tmpreg1 = DAC->CR;
-
-  /* Clear BOFFx, TENx, TSELx bits */
-  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
-
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */   
-  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_OutputBuffer);
-
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << DAC_Channel;
-
-  /* Write to DAC CR */
-  DAC->CR = tmpreg1;
-}
-
-/**
-  * @brief  Fills each DAC_InitStruct member with its default value.
-  * @param  DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
-  /* Initialize the DAC_Trigger member */
-  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
-  /* Initialize the DAC_OutputBuffer member */
-  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
-  * @brief  Enables or disables the specified DAC channel.
-  * @param  DAC_Channel: The selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  NewState: new state of the DAC channel. 
-  *      This parameter can be: ENABLE or DISABLE.
-  * @note When the DAC channel is enabled the trigger source can no more
-  *       be modified.
-  * @retval None
-  */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC channel */
-    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC channel */
-    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
-  }
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel software trigger.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  NewState: new state of the selected DAC channel software trigger.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable software trigger for the selected DAC channel */
-    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
-  }
-  else
-  {
-    /* Disable software trigger for the selected DAC channel */
-    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
-  }
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel1.
-  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Align_8b_R: 8bit right data alignment selected
-  *     @arg DAC_Align_12b_L: 12bit left data alignment selected
-  *     @arg DAC_Align_12b_R: 12bit right data alignment selected
-  * @param  Data : Data to be loaded in the selected data holding register.
-  * @retval None
-  */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{  
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(DAC_Align));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)DAC_BASE; 
-  tmp += DHR12R1_OFFSET + DAC_Align;
-
-  /* Set the DAC channel1 selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  
-  tmp = (uint32_t) DAC_BASE ;
-  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-  
-  /* Returns the DAC channel data output register value */
-  return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Group2 DMA management functions
- *  @brief   DMA management functions
- *
-@verbatim   
- ===============================================================================
-                    ##### DMA management functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified DAC channel DMA request.
-  *         When enabled DMA1 is generated when an external trigger (EXTI Line9,
-  *         TIM2, TIM3, TIM6 or TIM15  but not a software trigger) occurs
-  * @param  DAC_Channel: the selected DAC channel.
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  NewState: new state of the selected DAC channel DMA request.
-  *   This parameter can be: ENABLE or DISABLE.
-  *  The DAC channel1 is mapped on DMA1 channel3 which must be already configured. 
-  * @retval None
-  */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC channel DMA request */
-    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC channel DMA request */
-    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions
- *
-@verbatim   
- ===============================================================================
-            ##### Interrupts and flags management functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified DAC interrupts.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
-  *   This parameter can be the following values:
-  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
-  * @note The DMA underrun occurs when a second external trigger arrives before
-  *       the acknowledgement for the first external trigger is received (first request).
-  * @param  NewState: new state of the specified DAC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */ 
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_DAC_IT(DAC_IT)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DAC interrupts */
-    DAC->CR |=  (DAC_IT << DAC_Channel);
-  }
-  else
-  {
-    /* Disable the selected DAC interrupts */
-    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
-  }
-}
-
-/**
-  * @brief  Checks whether the specified DAC flag is set or not.
-  * @param  DAC_Channel: thee selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_FLAG: specifies the flag to check. 
-  *   This parameter can be only of the following value:
-  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
-  * @note The DMA underrun occurs when a second external trigger arrives before
-  *       the acknowledgement for the first external trigger is received (first request).
-  * @retval The new state of DAC_FLAG (SET or RESET).
-  */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_FLAG(DAC_FLAG));
-
-  /* Check the status of the specified DAC flag */
-  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
-  {
-    /* DAC_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DAC_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DAC_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DAC channel's pending flags.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_FLAG: specifies the flag to clear. 
-  *   This parameter can be of the following value:
-  *     @arg DAC_FLAG_DMAUDR: DMA underrun flag
-  * @retval None
-  */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_FLAG(DAC_FLAG));
-
-  /* Clear the selected DAC flags */
-  DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
-  * @brief  Checks whether the specified DAC interrupt has occurred or not.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_IT: specifies the DAC interrupt source to check. 
-  *   This parameter can be the following values:
-  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
-  * @note The DMA underrun occurs when a second external trigger arrives before
-  *       the acknowledgement for the first external trigger is received (first request).
-  * @retval The new state of DAC_IT (SET or RESET).
-  */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_IT(DAC_IT));
-
-  /* Get the DAC_IT enable bit status */
-  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-  
-  /* Check the status of the specified DAC interrupt */
-  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
-  {
-    /* DAC_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DAC_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DAC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DAC channel's interrupt pending bits.
-  * @param  DAC_Channel: the selected DAC channel. 
-  *   This parameter can be one of the following values:
-  *     @arg DAC_Channel_1: DAC Channel1 selected
-  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
-  *   This parameter can be the following values:
-  *     @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
-  * @retval None
-  */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(DAC_Channel));
-  assert_param(IS_DAC_IT(DAC_IT)); 
-
-  /* Clear the selected DAC interrupt pending bits */
-  DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c

@@ -1,213 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dbgmcu.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Debug MCU (DBGMCU) peripheral:
-  *           + Device and Revision ID management
-  *           + Peripherals Configuration
-  *  @verbatim
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dbgmcu.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DBGMCU 
-  * @brief DBGMCU driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions 
-  * @{
-  */
-  
-
-/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
- *  @brief   Device and Revision ID management functions
- *
-@verbatim
-  ==============================================================================
-            ##### Device and Revision ID management functions #####
-  ==============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @param  None
-  * @retval Device revision identifier
-  */
-uint32_t DBGMCU_GetREVID(void)
-{
-   return(DBGMCU->IDCODE >> 16);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @param  None
-  * @retval Device identifier
-  */
-uint32_t DBGMCU_GetDEVID(void)
-{
-   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
- *  @brief   Peripherals Configuration
- *
-@verbatim
-  ==============================================================================
-               ##### Peripherals Configuration functions #####
-  ==============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
-  * @param  DBGMCU_Periph: specifies the low power mode.
-  *         This parameter can be any combination of the following values:
-  *             @arg DBGMCU_STOP: Keep debugger connection during STOP mode
-  *             @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
-  * @param  NewState: new state of the specified low power mode in Debug mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    DBGMCU->CR |= DBGMCU_Periph;
-  }
-  else
-  {
-    DBGMCU->CR &= ~DBGMCU_Periph;
-  }
-}
-
-
-/**
-  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
-  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
-  *         This parameter can be any combination of the following values:
-  *             @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
-  *             @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped 
-  *                  when Core is halted.
-  *             @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
-  *             @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
-  *             @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped 
-  *                  when Core is halted
-  * @param  NewState: new state of the specified APB1 peripheral in Debug mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    DBGMCU->APB1FZ |= DBGMCU_Periph;
-  }
-  else
-  {
-    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
-  }
-}
-
-/**
-  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
-  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
-  *         This parameter can be any combination of the following values:
-  *             @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
-  *             @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
-  * @param  NewState: new state of the specified APB2 peripheral in Debug mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    DBGMCU->APB2FZ |= DBGMCU_Periph;
-  }
-  else
-  {
-    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
-  }
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c

@@ -1,660 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_dma.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Direct Memory Access controller (DMA):
-  *           + Initialization and Configuration
-  *           + Data Counter
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    (#) Enable The DMA controller clock using 
-        RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
-    (#) Enable and configure the peripheral to be connected to the DMA channel
-       (except for internal SRAM / FLASH memories: no initialization is necessary).
-    (#) For a given Channel, program the Source and Destination addresses, 
-        the transfer Direction, the Buffer Size, the Peripheral and Memory 
-        Incrementation mode and Data Size, the Circular or Normal mode, 
-        the channel transfer Priority and the Memory-to-Memory transfer 
-        mode (if needed) using the DMA_Init() function.
-    (#) Enable the NVIC and the corresponding interrupt(s) using the function 
-        DMA_ITConfig() if you need to use DMA interrupts.
-    (#) Enable the DMA channel using the DMA_Cmd() function.
-    (#) Activate the needed channel Request using PPP_DMACmd() function for 
-        any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) 
-        The function allowing this operation is provided in each PPP peripheral 
-        driver (ie. SPI_DMACmd for SPI peripheral).
-    (#) Optionally, you can configure the number of data to be transferred
-        when the channel is disabled (ie. after each Transfer Complete event
-        or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
-        And you can get the number of remaining data to be transferred using 
-        the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
-        enabled and running).
-    (#) To control DMA events you can use one of the following two methods:
-        (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
-        (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
-             phase and DMA_GetITStatus() function into interrupt routines in
-             communication phase.
-             After checking on a flag you should clear it using DMA_ClearFlag()
-             function. And after checking on an interrupt event you should 
-             clear it using DMA_ClearITPendingBit() function.
-    @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dma.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup DMA 
-  * @brief DMA driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CCR_CLEAR_MASK   ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_CHANNEL1_IT_MASK    ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_CHANNEL2_IT_MASK    ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_CHANNEL3_IT_MASK    ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_CHANNEL4_IT_MASK    ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_CHANNEL5_IT_MASK    ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Private_Functions 
-  * @{
-  */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions
- *
-@verbatim   
- ===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..] This subsection provides functions allowing to initialize the DMA channel 
-         source and destination addresses, incrementation and data sizes, transfer 
-         direction, buffer size, circular/normal mode selection, memory-to-memory 
-         mode selection and channel priority value.
-    [..] The DMA_Init() function follows the DMA configuration procedures as described 
-         in reference manual (RM0091).
-@endverbatim
-  * @{
-  */
-    
-/**
-  * @brief  Deinitializes the DMAy Channelx registers to their default reset
-  *         values.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and 
-  *         x can be 1 to 5 for DMA1 to select the DMA Channel.
-  * @retval None
-  */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-  /* Disable the selected DMAy Channelx */
-  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
-
-  /* Reset DMAy Channelx control register */
-  DMAy_Channelx->CCR  = 0;
-
-  /* Reset DMAy Channelx remaining bytes register */
-  DMAy_Channelx->CNDTR = 0;
-
-  /* Reset DMAy Channelx peripheral address register */
-  DMAy_Channelx->CPAR  = 0;
-
-  /* Reset DMAy Channelx memory address register */
-  DMAy_Channelx->CMAR = 0;
-
-  if (DMAy_Channelx == DMA1_Channel1)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel1 */
-    DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
-  }
-  else if (DMAy_Channelx == DMA1_Channel2)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel2 */
-    DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
-  }
-  else if (DMAy_Channelx == DMA1_Channel3)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel3 */
-    DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
-  }
-  else if (DMAy_Channelx == DMA1_Channel4)
-  {
-    /* Reset interrupt pending bits for DMA1 Channel4 */
-    DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
-  }
-  else
-  {
-    if (DMAy_Channelx == DMA1_Channel5) 
-    {
-      /* Reset interrupt pending bits for DMA1 Channel5 */
-      DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the DMAy Channelx according to the specified parameters 
-  *         in the DMA_InitStruct.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 5
-  *         for DMA1 to select the DMA Channel.
-  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
-  *         the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
-  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
-  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
-  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
-  assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
-  /* Get the DMAy_Channelx CCR value */
-  tmpreg = DMAy_Channelx->CCR;
-
-  /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
-  tmpreg &= CCR_CLEAR_MASK;
-
-  /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
-  /* Set DIR bit according to DMA_DIR value */
-  /* Set CIRC bit according to DMA_Mode value */
-  /* Set PINC bit according to DMA_PeripheralInc value */
-  /* Set MINC bit according to DMA_MemoryInc value */
-  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
-  /* Set MSIZE bits according to DMA_MemoryDataSize value */
-  /* Set PL bits according to DMA_Priority value */
-  /* Set the MEM2MEM bit according to DMA_M2M value */
-  tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
-            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
-            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
-            DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
-  /* Write to DMAy Channelx CCR */
-  DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
-  /* Write to DMAy Channelx CPAR */
-  DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
-  /* Write to DMAy Channelx CMAR */
-  DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
-  * @brief  Fills each DMA_InitStruct member with its default value.
-  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
-  /* Initialize the DMA_PeripheralBaseAddr member */
-  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
-  /* Initialize the DMA_MemoryBaseAddr member */
-  DMA_InitStruct->DMA_MemoryBaseAddr = 0;
-  /* Initialize the DMA_DIR member */
-  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
-  /* Initialize the DMA_BufferSize member */
-  DMA_InitStruct->DMA_BufferSize = 0;
-  /* Initialize the DMA_PeripheralInc member */
-  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
-  /* Initialize the DMA_MemoryInc member */
-  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
-  /* Initialize the DMA_PeripheralDataSize member */
-  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
-  /* Initialize the DMA_MemoryDataSize member */
-  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
-  /* Initialize the DMA_Mode member */
-  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
-  /* Initialize the DMA_Priority member */
-  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
-  /* Initialize the DMA_M2M member */
-  DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and
-  *         x can be 1 to 5 for DMA1 to select the DMA Channel.
-  * @param  NewState: new state of the DMAy Channelx. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMAy Channelx */
-    DMAy_Channelx->CCR |= DMA_CCR_EN;
-  }
-  else
-  {
-    /* Disable the selected DMAy Channelx */
-    DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Group2 Data Counter functions
- *  @brief   Data Counter functions 
- *
-@verbatim
- ===============================================================================
-                      ##### Data Counter functions #####
- ===============================================================================
-    [..] This subsection provides function allowing to configure and read the buffer 
-         size (number of data to be transferred).The DMA data counter can be written 
-         only when the DMA channel is disabled (ie. after transfer complete event).
-    [..] The following function can be used to write the Channel data counter value:
-         (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t 
-             DataNumber).
-    -@- It is advised to use this function rather than DMA_Init() in situations 
-        where only the Data buffer needs to be reloaded.
-    [..] The DMA data counter can be read to indicate the number of remaining transfers 
-         for the relative DMA channel. This counter is decremented at the end of each 
-         data transfer and when the transfer is complete: 
-         (+) If Normal mode is selected: the counter is set to 0.
-         (+) If Circular mode is selected: the counter is reloaded with the initial 
-         value(configured before enabling the DMA channel).
-    [..] The following function can be used to read the Channel data counter value:
-         (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the number of data units in the current DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and x can be 
-  *         1 to 5 for DMA1 to select the DMA Channel.
-  * @param  DataNumber: The number of data units in the current DMAy Channelx
-  *         transfer.
-  * @note   This function can only be used when the DMAy_Channelx is disabled.
-  * @retval None.
-  */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
-  /* Write to DMAy Channelx CNDTR */
-  DMAy_Channelx->CNDTR = DataNumber;
-}
-
-/**
-  * @brief  Returns the number of remaining data units in the current
-  *         DMAy Channelx transfer.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and
-  *         x can be 1 to 5 for DMA1 to select the DMA Channel.
-  * @retval The number of remaining data units in the current DMAy Channelx
-  *         transfer.
-  */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  /* Return the number of remaining data units for DMAy Channelx */
-  return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Group3 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions 
- *
-@verbatim
- ===============================================================================
-          ##### Interrupts and flags management functions #####
- ===============================================================================
-    [..] This subsection provides functions allowing to configure the DMA Interrupts 
-         sources and check or clear the flags or pending bits status.
-         The user should identify which mode will be used in his application to manage 
-         the DMA controller events: Polling mode or Interrupt mode. 
-  *** Polling Mode ***
-  ====================
-    [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller 
-         number  x : DMA channel number ).
-         (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
-         (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
-         (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
-         (#) DMAy_FLAG_GLx : to indicate that at least one of the events described 
-             above occurred.
-    -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the 
-        same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
-    [..]In this Mode it is advised to use the following functions:
-        (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-        (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
-
-  *** Interrupt Mode ***
-  ======================
-    [..] Each DMA channel can be managed through 4 Interrupts:
-    (+) Interrupt Source
-       (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete 
-            event.
-       (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete 
-            event.
-       (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
-       (##) DMA_IT_GL : to indicate that at least one of the interrupts described 
-            above occurred.
-    -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of 
-        the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
-    [..]In this Mode it is advised to use the following functions:
-        (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, 
-            FunctionalState NewState);
-        (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-        (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified DMAy Channelx interrupts.
-  * @param  DMAy_Channelx: where y can be 1 to select the DMA and
-  *         x can be 1 to 5 for DMA1 to select the DMA Channel.
-  * @param  DMA_IT: specifies the DMA interrupts sources to be enabled
-  *         or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg DMA_IT_TC: Transfer complete interrupt mask
-  *     @arg DMA_IT_HT: Half transfer interrupt mask
-  *     @arg DMA_IT_TE: Transfer error interrupt mask
-  * @param  NewState: new state of the specified DMA interrupts.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected DMA interrupts */
-    DMAy_Channelx->CCR |= DMA_IT;
-  }
-  else
-  {
-    /* Disable the selected DMA interrupts */
-    DMAy_Channelx->CCR &= ~DMA_IT;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx flag is set or not.
-  * @param  DMA_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *     
-  * @note
-  *    The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags 
-  *    relative to the same channel is set (Transfer Complete, Half-transfer 
-  *    Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or 
-  *    DMAy_FLAG_TEx). 
-  *      
-  * @retval The new state of DMA_FLAG (SET or RESET).
-  */
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
-  /* Check the status of the specified DMA flag */
-  if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)
-  {
-    /* DMA_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMA_FLAG is reset */
-    bitstatus = RESET;
-  }
-
-  /* Return the DMA_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's pending flags.
-  * @param  DMA_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
-  *     @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
-  *     @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
-  *     @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
-  *     @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
-  *     @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
-  *     @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
-  *     @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
-  *     @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
-  *     @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
-  *     @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
-  *     @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
-  *     @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
-  *     @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
-  *     @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
-  *     @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
-  *     @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
-  *     @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
-  *     @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
-  *     @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
-  *
-  * @note
-  *    Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
-  *    relative to the same channel (Transfer Complete, Half-transfer Complete and
-  *    Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
-  *
-  * @retval None
-  */
-void DMA_ClearFlag(uint32_t DMA_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
-  /* Clear the selected DMA flags */
-  DMA1->IFCR = DMA_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified DMAy Channelx interrupt has occurred or not.
-  * @param  DMA_IT: specifies the DMA interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     
-  * @note
-  *    The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other 
-  *    interrupts relative to the same channel is set (Transfer Complete, 
-  *    Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, 
-  *    DMAy_IT_HTx or DMAy_IT_TEx). 
-  *      
-  * @retval The new state of DMA_IT (SET or RESET).
-  */
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)
-{
-  ITStatus bitstatus = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_DMA_GET_IT(DMA_IT));
-
-  /* Check the status of the specified DMA interrupt */
-  if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)
-  {
-    /* DMA_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* DMA_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the DMA_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the DMAy Channelx's interrupt pending bits.
-  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
-  *   This parameter can be any combination (for the same DMA) of the following values:
-  *     @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
-  *     @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
-  *     @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
-  *     @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
-  *     @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
-  *     @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
-  *     @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
-  *     @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
-  *     @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
-  *     @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
-  *     @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
-  *     @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
-  *     @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
-  *     @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
-  *     @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
-  *     @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
-  *     @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
-  *     @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
-  *     @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
-  *     @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
-  *     
-  * @note
-  *    Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other 
-  *    interrupts relative to the same channel (Transfer Complete, Half-transfer 
-  *    Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and 
-  *    DMAy_IT_TEx).  
-  *        
-  * @retval None
-  */
-void DMA_ClearITPendingBit(uint32_t DMA_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
-  /* Clear the selected DMA interrupt pending bits */
-  DMA1->IFCR = DMA_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c

@@ -1,319 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_exti.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the EXTI peripheral:
-  *           + Initialization and Configuration
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
-  ==============================================================================
-                            ##### EXTI features ##### 
-  ==============================================================================
-    [..] External interrupt/event lines are mapped as following:
-         (#) All available GPIO pins are connected to the 16 external 
-             interrupt/event lines from EXTI0 to EXTI15.
-         (#) EXTI line 16 is connected to the PVD output.
-         (#) EXTI line 17 is connected to the RTC Alarm event.
-         (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
-         (#) EXTI line 21 is connected to the Comparator 1 wakeup event 
-         (#) EXTI line 22 is connected to the Comparator 2 wakeup event
-         (#) EXTI line 23 is connected to the I2C1 wakeup event
-         (#) EXTI line 25 is connected to the USART1 wakeup event
-         (#) EXTI line 27 is connected to the CEC wakeup event
-
-                       ##### How to use this driver ##### 
-  ==============================================================================
-    [..] In order to use an I/O pin as an external interrupt source, follow
-         steps below:
-    (#) Configure the I/O in input mode using GPIO_Init()
-    (#) Select the input source pin for the EXTI line using 
-        SYSCFG_EXTILineConfig().
-    (#) Select the mode(interrupt, event) and configure the trigger selection 
-       (Rising, falling or both) using EXTI_Init(). For the internal interrupt,
-       the trigger selection is not needed( the active edge is always the rising one).
-    (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
-    (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
-    [..]
-    (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
-      registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-    @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_exti.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup EXTI 
-  * @brief EXTI driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define EXTI_LINENONE     ((uint32_t)0x00000)        /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
-  * @{
-  */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Initialization and Configuration functions #####
-  ==============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the EXTI peripheral registers to their default reset 
-  *         values.
-  * @param  None
-  * @retval None
-  */
-void EXTI_DeInit(void)
-{
-  EXTI->IMR = 0x0F940000;
-  EXTI->EMR = 0x00000000;
-  EXTI->RTSR = 0x00000000;
-  EXTI->FTSR = 0x00000000;
-  EXTI->PR = 0x006BFFFF;
-}
-
-/**
-  * @brief  Initializes the EXTI peripheral according to the specified
-  *         parameters in the EXTI_InitStruct.
-  *    EXTI_Line specifies the EXTI line (EXTI0....EXTI27).
-  *    EXTI_Mode specifies which EXTI line is used as interrupt or an event.
-  *    EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
-  *                 pending bit will be set.
-  *    EXTI_LineCmd controls (Enable/Disable) the EXTI line.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 
-  *         contains the configuration information for the EXTI peripheral.
-  * @retval None
-  */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
-  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
-  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
-  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
-  tmp = (uint32_t)EXTI_BASE;
-
-  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
-  {
-    /* Clear EXTI line configuration */
-    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
-    /* Clear Rising Falling edge configuration */
-    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
-    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
-    /* Select the trigger for the selected interrupts */
-    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
-    {
-      /* Rising Falling edge */
-      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
-      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
-    }
-    else
-    {
-      tmp = (uint32_t)EXTI_BASE;
-      tmp += EXTI_InitStruct->EXTI_Trigger;
-
-      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-    }
-  }
-  else
-  {
-    tmp += EXTI_InitStruct->EXTI_Mode;
-
-    /* Disable the selected external lines */
-    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
-  }
-}
-
-/**
-  * @brief  Fills each EXTI_InitStruct member with its reset value.
-  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
-  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
-  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
-  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
-  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
-  *         will be generated.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19)
-  * @retval None
-  */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-
-  EXTI->SWIER |= EXTI_Line;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- *  @brief    Interrupts and flags management functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### Interrupts and flags management functions #####
-  ==============================================================================
-  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  EXTI_Line: specifies the EXTI line flag to check.
-  *   This parameter can be:
-  *   EXTI_Linex: External interrupt line x where x(0..19).
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
-   FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
-  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19)
-  * @retval None
-  */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  EXTI_Line: specifies the EXTI line to check.
-  *   This parameter can be:
-  *   EXTI_Linex: External interrupt line x where x(0..19).
-  * @retval The new state of EXTI_Line (SET or RESET).
-  */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t enablestatus = 0;
-  /* Check the parameters */
-  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
-  enablestatus =  EXTI->IMR & EXTI_Line;
-  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-  
-}
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  EXTI_Line: specifies the EXTI lines to clear.
-  *   This parameter can be any combination of EXTI_Linex where x can be (0..19).
-  * @retval None
-  */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(EXTI_Line));
-
-  EXTI->PR = EXTI_Line;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c

@@ -1,1170 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_flash.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the FLASH peripheral:
-  *            - FLASH Interface configuration
-  *            - FLASH Memory Programming
-  *            - Option Bytes Programming
-  *            - Interrupts and flags management
-  *
-  *  @verbatim
- ===============================================================================
-                    ##### How to use this driver #####
- ===============================================================================
-    [..] This driver provides functions to configure and program the Flash 
-         memory of all STM32F0xx devices. These functions are split in 4 groups
-         (#) FLASH Interface configuration functions: this group includes the 
-             management of following features:
-             (++) Set the latency
-             (++) Enable/Disable the prefetch buffer
-
-         (#) FLASH Memory Programming functions: this group includes all needed 
-             functions to erase and program the main memory:
-             (++) Lock and Unlock the Flash interface.
-             (++) Erase function: Erase Page, erase all pages.
-             (++) Program functions: Half Word and Word write.
-
-         (#) FLASH Option Bytes Programming functions: this group includes all 
-             needed functions to:
-             (++) Lock and Unlock the Flash Option bytes.
-             (++) Launch the Option Bytes loader
-             (++) Erase the Option Bytes
-             (++)Set/Reset the write protection
-             (++) Set the Read protection Level
-             (++) Program the user option Bytes
-             (++) Set/Reset the BOOT1 bit
-             (++) Enable/Disable the VDDA Analog Monitoring
-             (++) Get the user option bytes
-             (++) Get the Write protection
-             (++) Get the read protection status
-
-         (#) FLASH Interrupts and flag management functions: this group includes 
-             all needed functions to:
-             (++) Enable/Disable the flash interrupt sources
-             (++) Get flags status
-             (++) Clear flags
-             (++) Get Flash operation status
-             (++) Wait for last flash operation
-
- @endverbatim
-  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_flash.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup FLASH 
-  * @brief FLASH driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-  /* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
- 
-/** @defgroup FLASH_Private_Functions
-  * @{
-  */ 
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
-  *  @brief   FLASH Interface configuration functions 
- *
-@verbatim   
- ===============================================================================
-               ##### FLASH Interface configuration functions #####
- ===============================================================================
-
-    [..] FLASH_Interface configuration_Functions, includes the following functions:
-       (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
-    [..] To correctly read data from Flash memory, the number of wait states (LATENCY) 
-     must be correctly programmed according to the frequency of the CPU clock (HCLK) 
-    [..]
-        +--------------------------------------------- +
-        |  Wait states  |   HCLK clock frequency (MHz) |
-        |---------------|------------------------------|
-        |0WS(1CPU cycle)|       0 < HCLK <= 24         |
-        |---------------|------------------------------|
-        |1WS(2CPU cycle)|       24 < HCLK <= 48        |
-        +----------------------------------------------+
-    [..]
-       (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-    [..]
-     All these functions don't need the unlock sequence.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the code latency value.
-  * @param  FLASH_Latency: specifies the FLASH Latency value.
-  *   This parameter can be one of the following values:
-  *     @arg FLASH_Latency_0: FLASH Zero Latency cycle
-  *     @arg FLASH_Latency_1: FLASH One Latency cycle
-  * @retval None
-  */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
-   uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
-  /* Read the ACR register */
-  tmpreg = FLASH->ACR;  
-
-  /* Sets the Latency value */
-  tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
-  tmpreg |= FLASH_Latency;
-
-  /* Write the ACR register */
-  FLASH->ACR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Prefetch Buffer.
-  * @param  NewState: new state of the FLASH prefetch buffer.
-  *         This parameter can be: ENABLE or DISABLE. 
-  * @retval None
-  */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if(NewState != DISABLE)
-  {
-    FLASH->ACR |= FLASH_ACR_PRFTBE;
-  }
-  else
-  {
-    FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
-  }
-}
-
-/**
-  * @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
-  * @param  None
-  * @retval FLASH Prefetch Buffer Status (SET or RESET).
-  */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
-  FlagStatus bitstatus = RESET;
-
-  if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
-  return bitstatus; 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- *  @brief   FLASH Memory Programming functions
- *
-@verbatim   
- ===============================================================================
-                ##### FLASH Memory Programming functions #####
- ===============================================================================
-
-    [..] The FLASH Memory Programming functions, includes the following functions:
-       (+) void FLASH_Unlock(void);
-       (+) void FLASH_Lock(void);
-       (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-       (+) FLASH_Status FLASH_EraseAllPages(void);
-       (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-       (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-    [..] Any operation of erase or program should follow these steps:
-       
-       (#) Call the FLASH_Unlock() function to enable the flash control register and 
-           program memory access
-       (#) Call the desired function to erase page or program data
-       (#) Call the FLASH_Lock() to disable the flash program memory access 
-      (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlocks the FLASH control register and program memory access.
-  * @param  None
-  * @retval None
-  */
-void FLASH_Unlock(void)
-{
-  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
-  {
-    /* Unlocking the program memory access */
-    FLASH->KEYR = FLASH_FKEY1;
-    FLASH->KEYR = FLASH_FKEY2;
-  }
-}
-
-/**
-  * @brief  Locks the Program memory access.
-  * @param  None
-  * @retval None
-  */
-void FLASH_Lock(void)
-{
-  /* Set the LOCK Bit to lock the FLASH control register and program memory access */
-  FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
-  * @brief  Erases a specified page in program memory.
-  * @note    To correctly run this function, the FLASH_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_Lock() to disable the flash memory access 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  Page_Address: The page address in program memory to be erased.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of 1024 bytes).
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
- 
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  { 
-    /* If the previous operation is completed, proceed to erase the page */
-    FLASH->CR |= FLASH_CR_PER;
-    FLASH->AR  = Page_Address;
-    FLASH->CR |= FLASH_CR_STRT;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    
-    /* Disable the PER Bit */
-    FLASH->CR &= ~FLASH_CR_PER;
-  }
-    
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Erases all FLASH pages.
-  * @note    To correctly run this function, the FLASH_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_Lock() to disable the flash memory access 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_EraseAllPages(void)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* if the previous operation is completed, proceed to erase all pages */
-     FLASH->CR |= FLASH_CR_MER;
-     FLASH->CR |= FLASH_CR_STRT;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    /* Disable the MER Bit */
-    FLASH->CR &= ~FLASH_CR_MER;
-  }
-
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address.
-  * @note    To correctly run this function, the FLASH_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_Lock() to disable the flash memory access 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* If the previous operation is completed, proceed to program the new first 
-    half word */
-    FLASH->CR |= FLASH_CR_PG;
-  
-    *(__IO uint16_t*)Address = (uint16_t)Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- 
-    if(status == FLASH_COMPLETE)
-    {
-      /* If the previous operation is completed, proceed to program the new second 
-      half word */
-      tmp = Address + 2;
-
-      *(__IO uint16_t*) tmp = Data >> 16;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-        
-      /* Disable the PG Bit */
-      FLASH->CR &= ~FLASH_CR_PG;
-    }
-    else
-    {
-      /* Disable the PG Bit */
-      FLASH->CR &= ~FLASH_CR_PG;
-    }
-  }
-   
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a half word at a specified address.
-  * @note    To correctly run this function, the FLASH_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_Lock() to disable the flash memory access 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  Address: specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. 
-  */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* If the previous operation is completed, proceed to program the new data */
-    FLASH->CR |= FLASH_CR_PG;
-  
-    *(__IO uint16_t*)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    
-    /* Disable the PG Bit */
-    FLASH->CR &= ~FLASH_CR_PG;
-  } 
-  
-  /* Return the Program Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- *  @brief   Option Bytes Programming functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Option Bytes Programming functions #####
- ===============================================================================
-
-    [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
-       (+) void FLASH_OB_Unlock(void);
-       (+) void FLASH_OB_Lock(void);
-       (+) void FLASH_OB_Launch(void);
-       (+) FLASH_Status FLASH_OB_Erase(void);
-       (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
-       (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-       (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-       (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-       (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-       (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-	   (+) FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
-       (+) uint8_t FLASH_OB_GetUser(void);
-       (+) uint32_t FLASH_OB_GetWRP(void);
-       (+) FlagStatus FLASH_OB_GetRDP(void);
-
-    [..] Any operation of erase or program should follow these steps:
-
-   (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access
-
-   (#) Call one or several functions to program the desired option bytes 
-      (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
-      (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) 
-           => to Enable/Disable the desired sector write protection
-      (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) 
-           => to configure the user option Bytes: IWDG, STOP and the Standby.
-      (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
-           => to set or reset BOOT1 
-      (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG) 
-           => to enable or disable the VDDA Analog Monitoring 			 
-      (++) You can write all User Options bytes at once using a single function
-           by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
-	  (++) FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) to program the 
-	       two half word in the option bytes
-
-   (#) Once all needed option bytes to be programmed are correctly written, call the
-      FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-
-   (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended
-      to protect the option Bytes against possible unwanted operations)
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlocks the option bytes block access.
-  * @param  None
-  * @retval None
-  */
-void FLASH_OB_Unlock(void)
-{
-  if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
-  { 
-    /* Unlocking the option bytes block access */
-    FLASH->OPTKEYR = FLASH_OPTKEY1;
-    FLASH->OPTKEYR = FLASH_OPTKEY2;
-  }
-}
-
-/**
-  * @brief  Locks the option bytes block access.
-  * @param  None
-  * @retval None
-  */
-void FLASH_OB_Lock(void)
-{
-  /* Set the OPTWREN Bit to lock the option bytes block access */
-  FLASH->CR &= ~FLASH_CR_OPTWRE;
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @param  None
-  * @retval None
-  */
-void FLASH_OB_Launch(void)
-{
-  /* Set the OBL_Launch bit to launch the option byte loading */
-  FLASH->CR |= FLASH_CR_OBL_LAUNCH;
-}
-
-/**
-  * @brief  Erases the FLASH option bytes.
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @note   This functions erases all option bytes except the Read protection (RDP).
-  * @param  None
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_OB_Erase(void)
-{
-  uint16_t rdptmp = OB_RDP_Level_0;
-
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Get the actual read protection Option Byte value */ 
-  if(FLASH_OB_GetRDP() != RESET)
-  {
-    rdptmp = 0x00;  
-  }
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-  if(status == FLASH_COMPLETE)
-  {   
-    /* If the previous operation is completed, proceed to erase the option bytes */
-    FLASH->CR |= FLASH_CR_OPTER;
-    FLASH->CR |= FLASH_CR_STRT;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    
-    if(status == FLASH_COMPLETE)
-    {
-      /* If the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= ~FLASH_CR_OPTER;
-       
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= FLASH_CR_OPTPG;
-
-      /* Restore the last read protection Option Byte value */
-      OB->RDP = (uint16_t)rdptmp; 
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- 
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= ~FLASH_CR_OPTPG;
-      }
-    }
-    else
-    {
-      if (status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTPG Bit */
-        FLASH->CR &= ~FLASH_CR_OPTPG;
-      }
-    }  
-  }
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Write protects the desired pages
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  OB_WRP: specifies the address of the pages to be write protected.
-  *         This parameter can be:
-  *             @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
-  *             @arg OB_WRP_AllPages
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
-{
-  uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
-
-  FLASH_Status status = FLASH_COMPLETE;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP(OB_WRP));
-
-  OB_WRP = (uint32_t)(~OB_WRP);
-  WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
-  WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-  if(status == FLASH_COMPLETE)
-  {
-    FLASH->CR |= FLASH_CR_OPTPG;
-
-    if(WRP0_Data != 0xFF)
-    {
-      OB->WRP0 = WRP0_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    }
-    if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
-    {
-      OB->WRP1 = WRP1_Data;
-      
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    }
-          
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  } 
-  /* Return the write protection operation Status */
-  return status;
-}
-
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  FLASH_ReadProtection_Level: specifies the read protection level. 
-  *   This parameter can be:
-  *     @arg OB_RDP_Level_0: No protection
-  *     @arg OB_RDP_Level_1: Read protection of the memory
-  *     @arg OB_RDP_Level_2: Chip protection
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_RDP(OB_RDP));
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    FLASH->CR |= FLASH_CR_OPTER;
-    FLASH->CR |= FLASH_CR_STRT;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    
-    if(status == FLASH_COMPLETE)
-    {
-      /* If the erase operation is completed, disable the OPTER Bit */
-      FLASH->CR &= ~FLASH_CR_OPTER;
-      
-      /* Enable the Option Bytes Programming operation */
-      FLASH->CR |= FLASH_CR_OPTPG;
-       
-      OB->RDP = OB_RDP;
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); 
-    
-      if(status != FLASH_TIMEOUT)
-      {
-        /* if the program operation is completed, disable the OPTPG Bit */
-        FLASH->CR &= ~FLASH_CR_OPTPG;
-      }
-    }
-    else 
-    {
-      if(status != FLASH_TIMEOUT)
-      {
-        /* Disable the OPTER Bit */
-        FLASH->CR &= ~FLASH_CR_OPTER;
-      }
-    }
-  }
-  /* Return the protection operation Status */
-  return status;
-}
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  OB_IWDG: Selects the WDG mode
-  *         This parameter can be one of the following values:
-  *             @arg OB_IWDG_SW: Software WDG selected
-  *             @arg OB_IWDG_HW: Hardware WDG selected
-  * @param  OB_STOP: Reset event when entering STOP mode.
-  *         This parameter can be one of the following values:
-  *             @arg OB_STOP_NoRST: No reset generated when entering in STOP
-  *             @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  OB_STDBY: Reset event when entering Standby mode.
-  *         This parameter can be one of the following values:
-  *             @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
-  *             @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG; 
-
-    OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    if(status != FLASH_TIMEOUT)
-    {
-      /* If the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-/**
-  * @brief  Sets or resets the BOOT1.
-  * @param  OB_BOOT1: Set or Reset the BOOT1.
-  *         This parameter can be one of the following values:
-  *             @arg OB_BOOT1_RESET: BOOT1 Reset
-  *             @arg OB_BOOT1_SET: BOOT1 Set
-  * @retval None
-  */
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT1(OB_BOOT1));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG;
-
-    OB->USER = OB_BOOT1 | 0xEF;
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    if(status != FLASH_TIMEOUT)
-    {
-      /* If the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-/**
-  * @brief  Sets or resets the analogue monitoring on VDDA Power source.
-  * @param  OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
-  *         This parameter can be one of the following values:
-  *             @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
-  *             @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
-  * @retval None
-  */
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG; 
-
-    OB->USER = OB_VDDA_ANALOG | 0xDF;
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-/**
-  * @brief  Sets or resets the SRAM parity.
-  * @param  OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
-  *         This parameter can be one of the following values:
-  *             @arg OB_SRAM_PARITY_SET: Set SRAM parity.
-  *             @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
-  * @retval None
-  */
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Check the parameters */
-  assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {  
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG; 
-
-    OB->USER = OB_SRAM_Parity | 0xBF;
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    if(status != FLASH_TIMEOUT)
-    {
-      /* if the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
-  *         BOOT1 and VDDA ANALOG monitoring.
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  OB_USER: Selects all user option bytes
-  *         This parameter is a combination of the following values:
-  *             @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
-  *             @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
-  *             @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
-  *             @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
-  *             @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF 
-  *             @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET   
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
-{
-  FLASH_Status status = FLASH_COMPLETE; 
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-  
-  if(status == FLASH_COMPLETE)
-  {
-    /* Enable the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG; 
-
-    OB->USER = OB_USER | 0x88;
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-    if(status != FLASH_TIMEOUT)
-    {
-      /* If the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }    
-  /* Return the Option Byte program Status */
-  return status;
-
-}
-
-/**
-  * @brief  Programs a half word at a specified Option Byte Data address.
-  * @note    To correctly run this function, the FLASH_OB_Unlock() function
-  *           must be called before.
-  *          Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes 
-  *          (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  Address: specifies the address to be programmed.
-  *   This parameter can be 0x1FFFF804 or 0x1FFFF806. 
-  * @param  Data: specifies the data to be programmed.
-  * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
-  *         FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
-{
-  FLASH_Status status = FLASH_COMPLETE;
-  /* Check the parameters */
-  assert_param(IS_OB_DATA_ADDRESS(Address));
-  status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
-  if(status == FLASH_COMPLETE)
-  {
-    /* Enables the Option Bytes Programming operation */
-    FLASH->CR |= FLASH_CR_OPTPG; 
-    *(__IO uint16_t*)Address = Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-    
-    if(status != FLASH_TIMEOUT)
-    {
-      /* If the program operation is completed, disable the OPTPG Bit */
-      FLASH->CR &= ~FLASH_CR_OPTPG;
-    }
-  }
-  /* Return the Option Byte Data Program Status */
-  return status;
-}
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @param  None
-  * @retval The FLASH User Option Bytes .
-  */
-uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return (uint8_t)(FLASH->OBR >> 8);
-}
-
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes value.
-  * @param  None
-  * @retval The FLASH Write Protection Option Bytes value
-  */
-uint32_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (uint32_t)(FLASH->WRPR);
-}
-
-/**
-  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
-  * @param  None
-  * @retval FLASH ReadOut Protection Status(SET or RESET)
-  */
-FlagStatus FLASH_OB_GetRDP(void)
-{
-  FlagStatus readstatus = RESET;
-  
-  if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
-  {
-    readstatus = SET;
-  }
-  else
-  {
-    readstatus = RESET;
-  }
-  return readstatus;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions
- *
-@verbatim   
- ===============================================================================
-             ##### Interrupts and flags management functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified FLASH interrupts.
-  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or 
-  *         disabled.
-  *         This parameter can be any combination of the following values:
-  *             @arg FLASH_IT_EOP: FLASH end of programming Interrupt
-  *             @arg FLASH_IT_ERR: FLASH Error Interrupt
-  * @retval None 
-  */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_IT(FLASH_IT)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if(NewState != DISABLE)
-  {
-    /* Enable the interrupt sources */
-    FLASH->CR |= FLASH_IT;
-  }
-  else
-  {
-    /* Disable the interrupt sources */
-    FLASH->CR &= ~(uint32_t)FLASH_IT;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified FLASH flag is set or not.
-  * @param  FLASH_FLAG: specifies the FLASH flag to check.
-  *         This parameter can be one of the following values:
-  *             @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
-  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
-  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
-  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
-  * @retval The new state of FLASH_FLAG (SET or RESET).
-  */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
-  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the new state of FLASH_FLAG (SET or RESET) */
-  return bitstatus; 
-}
-
-/**
-  * @brief  Clears the FLASH's pending flags.
-  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
-  *         This parameter can be any combination of the following values:
-  *             @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
-  *             @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
-  *             @arg FLASH_FLAG_EOP: FLASH End of Programming flag
-  * @retval None
-  */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-  
-  /* Clear the flags */
-  FLASH->SR = FLASH_FLAG;
-}
-
-/**
-  * @brief  Returns the FLASH Status.
-  * @param  None
-  * @retval FLASH Status: The returned value can be: 
-  *         FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
-  */
-FLASH_Status FLASH_GetStatus(void)
-{
-  FLASH_Status FLASHstatus = FLASH_COMPLETE;
-  
-  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
-  {
-    FLASHstatus = FLASH_BUSY;
-  }
-  else 
-  {  
-    if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
-    { 
-      FLASHstatus = FLASH_ERROR_WRP;
-    }
-    else 
-    {
-      if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
-      {
-        FLASHstatus = FLASH_ERROR_PROGRAM; 
-      }
-      else
-      {
-        FLASHstatus = FLASH_COMPLETE;
-      }
-    }
-  }
-  /* Return the FLASH Status */
-  return FLASHstatus;
-}
-
-
-/**
-  * @brief  Waits for a FLASH operation to complete or a TIMEOUT to occur.
-  * @param  Timeout: FLASH programming Timeout
-  * @retval FLASH Status: The returned value can be: FLASH_BUSY, 
-  *         FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  FLASH_Status status = FLASH_COMPLETE;
-   
-  /* Check for the FLASH Status */
-  status = FLASH_GetStatus();
-  
-  /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
-  while((status == FLASH_BUSY) && (Timeout != 0x00))
-  {
-    status = FLASH_GetStatus();
-    Timeout--;
-  }
-  
-  if(Timeout == 0x00 )
-  {
-    status = FLASH_TIMEOUT;
-  }
-  /* Return the operation status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-   
-  /**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c

@@ -1,504 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_gpio.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the GPIO peripheral:
-  *           + Initialization and Configuration functions
-  *           + GPIO Read and Write functions
-  *           + GPIO Alternate functions configuration functions
-  *
-  *  @verbatim
-  *
-  *
-    ===========================================================================
-                         ##### How to use this driver #####
-    ===========================================================================
-      [..]
-      (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
-      (#) Configure the GPIO pin(s) using GPIO_Init()
-          Four possible configuration are available for each pin:
-         (++) Input: Floating, Pull-up, Pull-down.
-         (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
-                      Open Drain (Pull-up, Pull-down or no Pull).
-              In output mode, the speed is configurable: Low, Medium, Fast or High.
-         (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
-                                  Open Drain (Pull-up, Pull-down or no Pull).
-         (++) Analog: required mode when a pin is to be used as ADC channel,
-              DAC output or comparator input.
-      (#) Peripherals alternate function:
-         (++) For ADC, DAC and comparators, configure the desired pin in analog 
-              mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
-         (++) For other peripherals (TIM, USART...):
-              (+++) Connect the pin to the desired peripherals' Alternate 
-                    Function (AF) using GPIO_PinAFConfig() function. For PortC, 
-                    PortD and PortF, no configuration is needed.
-              (+++) Configure the desired pin in alternate function mode using
-                    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
-              (+++) Select the type, pull-up/pull-down and output speed via 
-                    GPIO_PuPd, GPIO_OType and GPIO_Speed members
-              (+++) Call GPIO_Init() function
-      (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
-      (#) To set/reset the level of a pin configured in output mode use
-          GPIO_SetBits()/GPIO_ResetBits()
-      (#) During and just after reset, the alternate functions are not active and 
-          the GPIO pins are configured in input floating mode (except JTAG pins).
-      (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
-          general-purpose (PC14 and PC15, respectively) when the LSE oscillator 
-          is off. The LSE has priority over the GPIO function.
-      (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose 
-          PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has 
-          priority over the GPIO function.
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_gpio.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup GPIO 
-  * @brief GPIO driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions 
-  * @{
-  */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- *  @brief   Initialization and Configuration
- *
-@verbatim
- ===============================================================================
-                    ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the GPIOx peripheral registers to their default reset 
-  *         values.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @retval None
-  */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  if(GPIOx == GPIOA)
-  {
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
-  }
-  else if(GPIOx == GPIOB)
-  {
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
-  }
-  else if(GPIOx == GPIOC)
-  {
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
-  }
-  else if(GPIOx == GPIOD)
-  {
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
-    RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
-  }
-  else
-  {
-    if(GPIOx == GPIOF)
-    {
-      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
-      RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified 
-  *         parameters in the GPIO_InitStruct.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @note   The configured pins can be: GPIO_Pin_0 -> GPIO_Pin_15 for GPIOA, GPIOB and GPIOC,
-  *         GPIO_Pin_0 -> GPIO_Pin_2 for GPIOD, GPIO_Pin_0 -> GPIO_Pin_3 for GPIOF.
-  * @retval None
-  */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
-  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
-  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
-  /*-------------------------- Configure the port pins -----------------------*/
-  /*-- GPIO Mode Configuration --*/
-  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
-  {
-    pos = ((uint32_t)0x01) << pinpos;
-
-    /* Get the port pins position */
-    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
-    if (currentpin == pos)
-    {
-      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
-      {
-        /* Check Speed mode parameters */
-        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
-        /* Speed mode configuration */
-        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
-        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
-        /* Check Output mode parameters */
-        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
-        /* Output mode configuration */
-        GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
-        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
-      }
-
-      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
-      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
-      /* Pull-up Pull down resistor configuration */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
-      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
-    }
-  }
-}
-
-/**
-  * @brief  Fills each GPIO_InitStruct member with its default value.
-  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will 
-  *         be initialized.
-  * @retval None
-  */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
-  /* Reset GPIO init structure parameters values */
-  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
-  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
-  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
-  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
-  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  *         The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx: where x can be (A or B) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *   This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval None
-  */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = 0x00010000;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  tmp |= GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKK bit */
-  GPIOx->LCKR =  GPIO_Pin;
-  /* Set LCKK bit */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit */
-  tmp = GPIOx->LCKR;
-  /* Read LCKK bit */
-  tmp = GPIOx->LCKR;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- *  @brief   GPIO Read and Write
- *
-@verbatim   
- ===============================================================================
-                      ##### GPIO Read and Write #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to read.
-  * @note   This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 
-  *         GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
-  * @retval The input port pin value.
-  */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @retval The input port pin value.
-  */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  return ((uint16_t)GPIOx->IDR);
-}
-
-/**
-  * @brief  Reads the specified output data port bit.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_Pin: Specifies the port bit to read.
-  * @note   This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 
-  *         GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
-  * @retval The output port pin value.
-  */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint8_t bitstatus = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
-  {
-    bitstatus = (uint8_t)Bit_SET;
-  }
-  else
-  {
-    bitstatus = (uint8_t)Bit_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Reads the specified GPIO output data port.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @retval GPIO output data port value.
-  */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  return ((uint16_t)GPIOx->ODR);
-}
-
-/**
-  * @brief  Sets the selected data port bits.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  * @note   This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 
-  *         GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
-  * @retval None
-  */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Clears the selected data port bits.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bits to be written.
-  * @note   This parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, 
-  *         GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.
-  * @retval None
-  */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->BRR = GPIO_Pin;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  * @param  BitVal: specifies the value to be written to the selected bit.
-  *   This parameter can be one of the BitAction enumeration values:
-  *     @arg Bit_RESET: to clear the port pin
-  *     @arg Bit_SET: to set the port pin
-  * @note   The GPIO_Pin parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, 
-  *         GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF.  
-  * @retval None
-  */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
-  if (BitVal != Bit_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BRR = GPIO_Pin ;
-  }
-}
-
-/**
-  * @brief  Writes data to the specified GPIO data port.
-  * @param  GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral.
-  * @param  PortVal: specifies the value to be written to the port output data 
-  *                  register.
-  * @retval None
-  */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
-  GPIOx->ODR = PortVal;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
- *  @brief   GPIO Alternate functions configuration functions
- *
-@verbatim   
- ===============================================================================
-          ##### GPIO Alternate functions configuration functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes data to the specified GPIO data port.
-  * @param  GPIOx: where x can be (A or B) to select the GPIO peripheral.
-  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
-  *   This parameter can be GPIO_PinSourcex where x can be (0..15).
-  * @param  GPIO_AF: selects the pin to used as Alternate function.
-  *   This parameter can be one of the following value:
- *     @arg GPIO_AF_0:WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14,
- *                    BOOT,USART1, CEC, IR_OUT, SPI2 
- *     @arg GPIO_AF_1:USART2, CEC, Tim3, USART1, USART2,EVENTOUT, I2C1, I2C2, TIM15 
- *     @arg GPIO_AF_2:TIM2, TIM1, EVENTOUT, TIM16, TIM17.
- *     @arg GPIO_AF_3:TS, I2C1, TIM15, EVENTOUT 
- *     @arg GPIO_AF_4:TIM14.
- *     @arg GPIO_AF_5:TIM16, TIM17.
- *     @arg GPIO_AF_6:EVENTOUT.
- *     @arg GPIO_AF_7:COMP1 OUT, COMP2 OUT 
- * @note  The pin should already been configured in Alternate Function mode(AF)
- *        using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * @note  Refer to the Alternate function mapping table in the device datasheet 
- *        for the detailed mapping of the system and peripherals'alternate 
- *        function I/O pins.
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
-  uint32_t temp = 0x00;
-  uint32_t temp_2 = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
-  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
-  assert_param(IS_GPIO_AF(GPIO_AF));
-
-  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
-  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
-  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
-  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c

@@ -1,1565 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_i2c.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Inter-Integrated circuit (I2C):
-  *           + Initialization and Configuration
-  *           + Communications handling
-  *           + SMBUS management
-  *           + I2C registers management
-  *           + Data transfers management
-  *           + DMA transfers management
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
- ============================================================================
-                     ##### How to use this driver #####
- ============================================================================
-   [..]
-   (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
-       function for I2C1 or I2C2.
-   (#) Enable SDA, SCL  and SMBA (when used) GPIO clocks using 
-       RCC_AHBPeriphClockCmd() function. 
-   (#) Peripherals alternate function: 
-       (++) Connect the pin to the desired peripherals' Alternate 
-            Function (AF) using GPIO_PinAFConfig() function.
-       (++) Configure the desired pin in alternate function by:
-            GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
-       (++) Select the type, OpenDrain and speed via  
-            GPIO_PuPd, GPIO_OType and GPIO_Speed members
-       (++) Call GPIO_Init() function.
-   (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address 
-       using the I2C_Init() function.
-   (#) Optionally you can enable/configure the following parameters without
-       re-initialization (i.e there is no need to call again I2C_Init() function):
-       (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
-       (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
-       (++) Enable the general call using the I2C_GeneralCallCmd() function.
-       (++) Enable the clock stretching using I2C_StretchClockCmd() function.
-       (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
-       (++) For SMBus Mode:
-            (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
-   (#) Enable the NVIC and the corresponding interrupt using the function
-       I2C_ITConfig() if you need to use interrupt mode.
-   (#) When using the DMA mode 
-      (++) Configure the DMA using DMA_Init() function.
-      (++) Active the needed channel Request using I2C_DMACmd() function.
-   (#) Enable the I2C using the I2C_Cmd() function.
-   (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
-       transfers. 
-   [..]
-   (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
-       must be enabled by setting the driving capability control bit in SYSCFG.
-
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_i2c.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup I2C 
-  * @brief I2C driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK          ((uint32_t)0x00CFE0FF)  /*<! I2C CR1 clear register Mask */
-#define CR2_CLEAR_MASK          ((uint32_t)0x07FF7FFF)  /*<! I2C CR2 clear register Mask */
-#define TIMING_CLEAR_MASK       ((uint32_t)0xF0FFFFFF)  /*<! I2C TIMING clear register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
-  * @{
-  */
-
-
-/** @defgroup I2C_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
- ===============================================================================
-           ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..] This section provides a set of functions allowing to initialize the I2C Mode,
-         I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
-
-    [..] The I2C_Init() function follows the I2C configuration procedures (these procedures 
-         are available in reference manual).
-
-    [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
-         states machines are reset and communication control bits, as well as status bits come 
-         back to their reset value.
-
-    [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
-         HSI and Digital filters must be disabled.
-
-    [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
-         configured using I2C_OwnAddress2Config() function.
-
-    [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of 
-         each byte in slave mode when NBYTES is set to 0x01.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the I2Cx peripheral registers to their default reset values.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval None
-  */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  if (I2Cx == I2C1)
-  {
-    /* Enable I2C1 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
-    /* Release I2C1 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
-  }
-  else
-  {
-    /* Enable I2C2 reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
-    /* Release I2C2 from reset state */
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
-  }
-}
-
-/**
-  * @brief  Initializes the I2Cx peripheral according to the specified
-  *         parameters in the I2C_InitStruct.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
-  *         contains the configuration information for the specified I2C peripheral.
-  * @retval None
-  */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
-  assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
-  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
-  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
-  assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
-  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
-  /* Disable I2Cx Peripheral */
-  I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
-  /*---------------------------- I2Cx FILTERS Configuration ------------------*/
-  /* Get the I2Cx CR1 value */
-  tmpreg = I2Cx->CR1;
-  /* Clear I2Cx CR1 register */
-  tmpreg &= CR1_CLEAR_MASK;
-  /* Configure I2Cx: analog and digital filter */
-  /* Set ANFOFF bit according to I2C_AnalogFilter value */
-  /* Set DFN bits according to I2C_DigitalFilter value */
-  tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
-
-  /* Write to I2Cx CR1 */
-  I2Cx->CR1 = tmpreg;
-
-  /*---------------------------- I2Cx TIMING Configuration -------------------*/
-  /* Configure I2Cx: Timing */
-  /* Set TIMINGR bits according to I2C_Timing */
-  /* Write to I2Cx TIMING */
-  I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
-
-  /* Enable I2Cx Peripheral */
-  I2Cx->CR1 |= I2C_CR1_PE;
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Clear tmpreg local variable */
-  tmpreg = 0;
-  /* Clear OAR1 register */
-  I2Cx->OAR1 = (uint32_t)tmpreg;
-  /* Clear OAR2 register */
-  I2Cx->OAR2 = (uint32_t)tmpreg;
-  /* Configure I2Cx: Own Address1 and acknowledged address */
-  /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
-  /* Set OA1 bits according to I2C_OwnAddress1 value */
-  tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
-                      (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
-  /* Write to I2Cx OAR1 */
-  I2Cx->OAR1 = tmpreg;
-  /* Enable Own Address1 acknowledgement */
-  I2Cx->OAR1 |= I2C_OAR1_OA1EN;
-
-  /*---------------------------- I2Cx MODE Configuration ---------------------*/
-  /* Configure I2Cx: mode */
-  /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
-  tmpreg = I2C_InitStruct->I2C_Mode;
-  /* Write to I2Cx CR1 */
-  I2Cx->CR1 |= tmpreg;
-
-  /*---------------------------- I2Cx ACK Configuration ----------------------*/
-  /* Get the I2Cx CR2 value */
-  tmpreg = I2Cx->CR2;
-  /* Clear I2Cx CR2 register */
-  tmpreg &= CR2_CLEAR_MASK;
-  /* Configure I2Cx: acknowledgement */
-  /* Set NACK bit according to I2C_Ack value */
-  tmpreg |= I2C_InitStruct->I2C_Ack;
-  /* Write to I2Cx CR2 */
-  I2Cx->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Fills each I2C_InitStruct member with its default value.
-  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
-  /*---------------- Reset I2C init structure parameters values --------------*/
-  /* Initialize the I2C_Timing member */
-  I2C_InitStruct->I2C_Timing = 0;
-  /* Initialize the I2C_AnalogFilter member */
-  I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
-  /* Initialize the I2C_DigitalFilter member */
-  I2C_InitStruct->I2C_DigitalFilter = 0;
-  /* Initialize the I2C_Mode member */
-  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
-  /* Initialize the I2C_OwnAddress1 member */
-  I2C_InitStruct->I2C_OwnAddress1 = 0;
-  /* Initialize the I2C_Ack member */
-  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
-  /* Initialize the I2C_AcknowledgedAddress member */
-  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
-  * @brief  Enables or disables the specified I2C peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C peripheral */
-    I2Cx->CR1 |= I2C_CR1_PE;
-  }
-  else
-  {
-    /* Disable the selected I2C peripheral */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C software reset.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C software reset.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Peripheral under reset */
-    I2Cx->CR1 |= I2C_CR1_SWRST;
-  }
-  else
-  {
-    /* Peripheral not under reset */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SWRST);
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified I2C interrupts.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_ERRI: Error interrupt mask
-  *     @arg I2C_IT_TCI: Transfer Complete interrupt mask
-  *     @arg I2C_IT_STOPI: Stop Detection interrupt mask
-  *     @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
-  *     @arg I2C_IT_ADDRI: Address Match interrupt mask  
-  *     @arg I2C_IT_RXI: RX interrupt mask
-  *     @arg I2C_IT_TXI: TX interrupt mask
-  * @param  NewState: new state of the specified I2C interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C interrupts */
-    I2Cx->CR1 |= I2C_IT;
-  }
-  else
-  {
-    /* Disable the selected I2C interrupts */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
-  }
-}
-
-/**
-  * @brief  Enables or disables the I2C Clock stretching.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx Clock stretching.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable clock stretching */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);    
-  }
-  else
-  {
-    /* Disable clock stretching  */
-    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
-  }
-}
-
-/**
-  * @brief  Enables or disables I2C wakeup from stop mode.
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx stop mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable wakeup from stop mode */
-    I2Cx->CR1 |= I2C_CR1_WUPEN;   
-  }
-  else
-  {
-    /* Disable wakeup from stop mode */    
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN); 
-  }
-}
-
-/**
-  * @brief  Enables or disables the I2C own address 2.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C own address 2.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable own address 2 */
-    I2Cx->OAR2 |= I2C_OAR2_OA2EN;
-  }
-  else
-  {
-    /* Disable own address 2 */
-    I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
-  }
-}    
-
-/**
-  * @brief  Configures the I2C slave own address 2 and mask.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the slave address to be programmed.
-  * @param  Mask: specifies own address 2 mask to be programmed.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_OA2_NoMask: no mask.
-  *     @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
-  *     @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
-  *     @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
-  *     @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
-  *     @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
-  *     @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
-  *     @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
-  * @retval None
-  */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_OWN_ADDRESS2(Address));
-  assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
-  
-  /* Get the old register value */
-  tmpreg = I2Cx->OAR2;
-
-  /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0]  */
-  tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
-
-  /* Set I2Cx SADD */
-  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
-            (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
-
-  /* Store the new register value */
-  I2Cx->OAR2 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the I2C general call mode.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C general call mode.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable general call mode */
-    I2Cx->CR1 |= I2C_CR1_GCEN;
-  }
-  else
-  {
-    /* Disable general call mode */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
-  }
-} 
-
-/**
-  * @brief  Enables or disables the I2C slave byte control.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C slave byte control.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable slave byte control */
-    I2Cx->CR1 |= I2C_CR1_SBC;
-  }
-  else
-  {
-    /* Disable slave byte control */
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
-  }
-}
-
-/**
-  * @brief  Configures the slave address to be transmitted after start generation.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the slave address to be programmed.
-  * @note   This function should be called before generating start condition.
-  * @retval None
-  */
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_SLAVE_ADDRESS(Address));
-               
-  /* Get the old register value */
-  tmpreg = I2Cx->CR2;
-
-  /* Reset I2Cx SADD bit [9:0] */
-  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
-
-  /* Set I2Cx SADD */
-  tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
-
-  /* Store the new register value */
-  I2Cx->CR2 = tmpreg;
-}
-  
-/**
-  * @brief  Enables or disables the I2C 10-bit addressing mode for the master.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C 10-bit addressing mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note   This function should be called before generating start condition.
-  * @retval None
-  */
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable 10-bit addressing mode */
-    I2Cx->CR2 |= I2C_CR2_ADD10;
-  }
-  else
-  {
-    /* Disable 10-bit addressing mode */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
-  }
-} 
-
-/**
-  * @}
-  */
-
-
-/** @defgroup I2C_Group2 Communications handling functions
- *  @brief   Communications handling functions 
- *
-@verbatim
- ===============================================================================
-                  ##### Communications handling functions #####
- ===============================================================================  
-    [..] This section provides a set of functions that handles I2C communication.
-
-    [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
-         mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
-
-    [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
-         this configuration should be done before generating start condition in master 
-         mode.
-
-    [..] When switching from master write operation to read operation in 10Bit addressing
-         mode, master can only sends the 1st 7 bits of the 10 bit address, followed by 
-         Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
-
-    [..] In master mode, when transferring more than 255 bytes Reload mode should be used
-         to handle communication. In the first phase of transfer, Nbytes should be set to 
-         255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
-         function should be called to handle remaining communication.
-
-    [..] In master mode, when software end mode is selected when all data is transferred
-         TC flag is set I2C_TransferHandling() function should be called to generate STOP
-         or generate ReStart.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Enables or disables the I2C automatic end mode (stop condition is 
-  *         automatically sent when nbytes data are transferred).
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C automatic end mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note   This function has effect if Reload mode is disabled.
-  * @retval None
-  */
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Auto end mode */
-    I2Cx->CR2 |= I2C_CR2_AUTOEND;
-  }
-  else
-  {
-    /* Disable Auto end mode */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
-  }
-} 
-
-/**
-  * @brief  Enables or disables the I2C nbytes reload mode.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the nbytes reload mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Auto Reload mode */
-    I2Cx->CR2 |= I2C_CR2_RELOAD;
-  }
-  else
-  {
-    /* Disable Auto Reload mode */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
-  }
-}
-
-/**
-  * @brief  Configures the number of bytes to be transmitted/received.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Number_Bytes: specifies the number of bytes to be programmed.
-  * @retval None
-  */
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
-  /* Get the old register value */
-  tmpreg = I2Cx->CR2;
-
-  /* Reset I2Cx Nbytes bit [7:0] */
-  tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
-
-  /* Set I2Cx Nbytes */
-  tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
-
-  /* Store the new register value */
-  I2Cx->CR2 = tmpreg;
-}  
-  
-/**
-  * @brief  Configures the type of transfer request for the master.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_Direction: specifies the transfer request direction to be programmed.
-  *    This parameter can be one of the following values:
-  *     @arg I2C_Direction_Transmitter: Master request a write transfer
-  *     @arg I2C_Direction_Receiver: Master request a read transfer  
-  * @retval None
-  */
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
-{
-/* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_DIRECTION(I2C_Direction));
-  
-  /* Test on the direction to set/reset the read/write bit */
-  if (I2C_Direction == I2C_Direction_Transmitter)
-  {
-    /* Request a write Transfer */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
-  }
-  else
-  {
-    /* Request a read Transfer */
-    I2Cx->CR2 |= I2C_CR2_RD_WRN;
-  }
-}  
-  
-/**
-  * @brief  Generates I2Cx communication START condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C START condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Generate a START condition */
-    I2Cx->CR2 |= I2C_CR2_START;
-  }
-  else
-  {
-    /* Disable the START condition generation */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
-  }
-}  
-  
-/**
-  * @brief  Generates I2Cx communication STOP condition.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C STOP condition generation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Generate a STOP condition */
-    I2Cx->CR2 |= I2C_CR2_STOP;
-  }
-  else
-  {
-    /* Disable the STOP condition generation */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
-  }
-}  
-
-/**
-  * @brief  Enables or disables the I2C 10-bit header only mode with read direction.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the I2C 10-bit header only mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note   This mode can be used only when switching from master transmitter mode 
-  *         to master receiver mode.
-  * @retval None
-  */
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable 10-bit header only mode */
-    I2Cx->CR2 |= I2C_CR2_HEAD10R;
-  }
-  else
-  {
-    /* Disable 10-bit header only mode */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
-  }
-}    
-
-/**
-  * @brief  Generates I2C communication Acknowledge.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  NewState: new state of the Acknowledge.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable ACK generation */
-    I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);    
-  }
-  else
-  {
-    /* Enable NACK generation */
-    I2Cx->CR2 |= I2C_CR2_NACK;
-  }
-}
-
-/**
-  * @brief  Returns the I2C slave matched address .
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The value of the slave matched address .
-  */
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  
-  /* Return the slave matched address in the SR1 register */
-  return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
-}
-
-/**
-  * @brief  Returns the I2C slave received request.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The value of the received request.
-  */
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
-{
-  uint32_t tmpreg = 0;
-  uint16_t direction = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  
-  /* Return the slave matched address in the SR1 register */
-  tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
-  
-  /* If write transfer is requested */
-  if (tmpreg == 0)
-  {
-    /* write transfer is requested */
-    direction = I2C_Direction_Transmitter;
-  }
-  else
-  {
-    /* Read transfer is requested */
-    direction = I2C_Direction_Receiver;
-  }  
-  return direction;
-}
-
-/**
-  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Address: specifies the slave address to be programmed.
-  * @param  Number_Bytes: specifies the number of bytes to be programmed.
-  *   This parameter must be a value between 0 and 255.
-  * @param  ReloadEndMode: new state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_Reload_Mode: Enable Reload mode .
-  *     @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
-  *     @arg I2C_SoftEnd_Mode: Enable Software end mode.
-  * @param  StartStopMode: new state of the I2C START condition generation.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_No_StartStop: Don't Generate stop and start condition.
-  *     @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
-  *     @arg I2C_Generate_Start_Read: Generate Restart for read request.
-  *     @arg I2C_Generate_Start_Write: Generate Restart for write request.
-  * @retval None
-  */
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_SLAVE_ADDRESS(Address));  
-  assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
-  assert_param(IS_START_STOP_MODE(StartStopMode));
-    
-  /* Get the CR2 register value */
-  tmpreg = I2Cx->CR2;
-  
-  /* clear tmpreg specific bits */
-  tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-  
-  /* update tmpreg */
-  tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
-            (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
-  
-  /* update CR2 register */
-  I2Cx->CR2 = tmpreg;  
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup I2C_Group3 SMBUS management functions
- *  @brief   SMBUS management functions 
- *
-@verbatim
- ===============================================================================
-                      ##### SMBUS management functions #####
- ===============================================================================  
-    [..] This section provides a set of functions that handles SMBus communication
-         and timeouts detection.
-
-    [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
-         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
-         I2C_Mode_SMBusDevice.
-
-    [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
-         function and setting I2C_Mode member of I2C_InitTypeDef() structure to 
-         I2C_Mode_SMBusHost.
-
-    [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
-         function.
-
-    [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be 
-         configured (in accordance to SMBus specification) using I2C_TimeoutBConfig() 
-         function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
-         the detection.
-
-    [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
-         function followed by the call of I2C_ClockTimeoutCmd(). When adding to this 
-         procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition 
-         (both SCL and SDA high) is detected also.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables I2C SMBus alert.
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx SMBus alert.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable SMBus alert */
-    I2Cx->CR1 |= I2C_CR1_ALERTEN;   
-  }
-  else
-  {
-    /* Disable SMBus alert */    
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); 
-  }
-}
-
-/**
-  * @brief  Enables or disables I2C Clock Timeout (SCL Timeout detection).
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx clock Timeout.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Clock Timeout */
-    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;   
-  }
-  else
-  {
-    /* Disable Clock Timeout */    
-    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); 
-  }
-}
-
-/**
-  * @brief  Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx Extended clock Timeout.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Clock Timeout */
-    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;   
-  }
-  else
-  {
-    /* Disable Clock Timeout */    
-    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); 
-  }
-}
-
-/**
-  * @brief  Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA 
-  *         high detection).
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx Idle clock Timeout.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable Clock Timeout */
-    I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;   
-  }
-  else
-  {
-    /* Disable Clock Timeout */    
-    I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); 
-  }
-}
-
-/**
-  * @brief  Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus 
-  *   idle SCL and SDA high when TIDLE = 1).
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  Timeout: specifies the TimeoutA to be programmed. 
-  * @retval None
-  */
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_I2C_TIMEOUT(Timeout));
-    
-  /* Get the old register value */
-  tmpreg = I2Cx->TIMEOUTR;
-
-  /* Reset I2Cx TIMEOUTA bit [11:0] */
-  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
-
-  /* Set I2Cx TIMEOUTA */
-  tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
-
-  /* Store the new register value */
-  I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
-  * @brief  Configures the I2C Bus Timeout B (SCL cumulative Timeout).
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  Timeout: specifies the TimeoutB to be programmed. 
-  * @retval None
-  */
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_I2C_TIMEOUT(Timeout));
-
-  /* Get the old register value */
-  tmpreg = I2Cx->TIMEOUTR;
-
-  /* Reset I2Cx TIMEOUTB bit [11:0] */
-  tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
-
-  /* Set I2Cx TIMEOUTB */
-  tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
-
-  /* Store the new register value */
-  I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables I2C PEC calculation.
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx PEC calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable PEC calculation */
-    I2Cx->CR1 |= I2C_CR1_PECEN;   
-  }
-  else
-  {
-    /* Disable PEC calculation */    
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); 
-  }
-}
-
-/**
-  * @brief  Enables or disables I2C PEC transmission/reception request.
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @param  NewState: new state of the I2Cx PEC request.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable PEC transmission/reception request */
-    I2Cx->CR1 |= I2C_CR2_PECBYTE;   
-  }
-  else
-  {
-    /* Disable PEC transmission/reception request */    
-    I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); 
-  }
-}
-
-/**
-  * @brief  Returns the I2C PEC.
-  * @param  I2Cx: where x can be 1 to select the I2C peripheral.
-  * @retval The value of the PEC .
-  */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_1_PERIPH(I2Cx));
-  
-  /* Return the slave matched address in the SR1 register */
-  return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
-}
-
-/**
-  * @}
-  */  
-
-
-/** @defgroup I2C_Group4 I2C registers management functions
- *  @brief   I2C registers management functions 
- *
-@verbatim
- ===============================================================================
-                ##### I2C registers management functions #####
- ===============================================================================  
-    [..] This section provides a functions that allow user the management of 
-         I2C registers.
-
-@endverbatim
-  * @{
-  */
-
-  /**
-  * @brief  Reads the specified I2C register and returns its value.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_Register: specifies the register to read.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_Register_CR1: CR1 register.
-  *     @arg I2C_Register_CR2: CR2 register.
-  *     @arg I2C_Register_OAR1: OAR1 register.
-  *     @arg I2C_Register_OAR2: OAR2 register.
-  *     @arg I2C_Register_TIMINGR: TIMING register.
-  *     @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
-  *     @arg I2C_Register_ISR: ISR register.
-  *     @arg I2C_Register_ICR: ICR register.
-  *     @arg I2C_Register_PECR: PECR register.
-  *     @arg I2C_Register_RXDR: RXDR register.
-  *     @arg I2C_Register_TXDR: TXDR register.
-  * @retval The value of the read register.
-  */
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_REGISTER(I2C_Register));
-
-  tmp = (uint32_t)I2Cx;
-  tmp += I2C_Register;
-
-  /* Return the selected register value */
-  return (*(__IO uint32_t *) tmp);
-}
-
-/**
-  * @}
-  */  
-  
-/** @defgroup I2C_Group5 Data transfers management functions
- *  @brief   Data transfers management functions 
- *
-@verbatim
- ===============================================================================
-                ##### Data transfers management functions #####
- ===============================================================================  
-    [..] This subsection provides a set of functions allowing to manage 
-         the I2C data transfers.
-
-    [..] The read access of the I2C_RXDR register can be done using 
-         the I2C_ReceiveData() function and returns the received value.
-         Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
-         function and stores the written data into TXDR.
-@endverbatim
-  * @{
-  */  
-  
-/**
-  * @brief  Sends a data byte through the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  Data: Byte to be transmitted..
-  * @retval None
-  */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  
-  /* Write in the DR register the data to be sent */
-  I2Cx->TXDR = (uint8_t)Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the I2Cx peripheral.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @retval The value of the received data.
-  */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  
-  /* Return the data in the DR register */
-  return (uint8_t)I2Cx->RXDR;
-}  
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup I2C_Group6 DMA transfers management functions
- *  @brief   DMA transfers management functions 
- *
-@verbatim
- ===============================================================================
-                ##### DMA transfers management functions #####
- ===============================================================================  
-    [..] This section provides two functions that can be used only in DMA mode.
-    [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel 
-         requests:
-         (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
-         (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
-    [..] In this Mode it is advised to use the following function:
-         (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-@endverbatim
-  * @{
-  */  
-    
-/**
-  * @brief  Enables or disables the I2C DMA interface.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_DMAReq_Tx: Tx DMA transfer request
-  *     @arg I2C_DMAReq_Rx: Rx DMA transfer request
-  * @param  NewState: new state of the selected I2C DMA transfer request.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected I2C DMA requests */
-    I2Cx->CR1 |= I2C_DMAReq;
-  }
-  else
-  {
-    /* Disable the selected I2C DMA requests */
-    I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
-  }
-}
-/**
-  * @}
-  */  
-
-
-/** @defgroup I2C_Group7 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions 
- *
-@verbatim
- ===============================================================================
-             ##### Interrupts and flags management functions  #####
- ===============================================================================  
-    [..] This section provides functions allowing to configure the I2C Interrupts 
-         sources and check or clear the flags or pending bits status.
-         The user should identify which mode will be used in his application to manage 
-         the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).
-
-  *** Polling Mode ***
-  ====================
-    [..] In Polling Mode, the I2C communication can be managed by 15 flags:
-        (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
-        (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
-        (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
-        (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
-        (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
-        (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
-        (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
-        (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
-        (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
-        (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
-        (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
-        (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
-        (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
-        (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
-        (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
-
-    [..] In this Mode it is advised to use the following functions:
-        (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-        (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-    [..]
-        (@)Do not use the BUSY flag to handle each data transmission or reception.It is 
-           better to use the TXIS and RXNE flags instead.
-
-  *** Interrupt Mode ***
-  ======================
-    [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
-         and 15 pending bits: 
-    [..] Interrupt Source:
-        (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
-        (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
-        (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
-        (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
-        (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
-        (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
-        (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
-
-    [..] Pending Bits:
-        (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
-        (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
-        (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
-        (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
-        (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
-        (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
-        (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
-        (#) I2C_IT_BERR: to indicate the status of Bus error flag.
-        (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
-        (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
-        (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
-        (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
-        (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
-
-    [..] In this Mode it is advised to use the following functions:
-        (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-        (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-@endverbatim
-  * @{
-  */  
-
-/**
-  * @brief  Checks whether the specified I2C flag is set or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg I2C_FLAG_TXE: Transmit data register empty
-  *     @arg I2C_FLAG_TXIS: Transmit interrupt status
-  *     @arg I2C_FLAG_RXNE: Receive data register not empty
-  *     @arg I2C_FLAG_ADDR: Address matched (slave mode)
-  *     @arg I2C_FLAG_NACKF: NACK received flag
-  *     @arg I2C_FLAG_STOPF: STOP detection flag
-  *     @arg I2C_FLAG_TC: Transfer complete (master mode)
-  *     @arg I2C_FLAG_TCR: Transfer complete reload
-  *     @arg I2C_FLAG_BERR: Bus error
-  *     @arg I2C_FLAG_ARLO: Arbitration lost
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun
-  *     @arg I2C_FLAG_PECERR: PEC error in reception
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
-  *     @arg I2C_FLAG_ALERT: SMBus Alert
-  *     @arg I2C_FLAG_BUSY: Bus busy
-  * @retval The new state of I2C_FLAG (SET or RESET).
-  */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
-  uint32_t tmpreg = 0;
-  FlagStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-  
-  /* Get the ISR register value */
-  tmpreg = I2Cx->ISR;
-  
-  /* Get flag status */
-  tmpreg &= I2C_FLAG;
-  
-  if(tmpreg != 0)
-  {
-    /* I2C_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_FLAG is reset */
-    bitstatus = RESET;
-  }
-  return bitstatus;
-} 
-
-/**
-  * @brief  Clears the I2Cx's pending flags.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_FLAG: specifies the flag to clear. 
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_FLAG_ADDR: Address matched (slave mode)
-  *     @arg I2C_FLAG_NACKF: NACK received flag
-  *     @arg I2C_FLAG_STOPF: STOP detection flag
-  *     @arg I2C_FLAG_BERR: Bus error
-  *     @arg I2C_FLAG_ARLO: Arbitration lost
-  *     @arg I2C_FLAG_OVR: Overrun/Underrun
-  *     @arg I2C_FLAG_PECERR: PEC error in reception
-  *     @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
-  *     @arg I2C_FLAG_ALERT: SMBus Alert
-  * @retval The new state of I2C_FLAG (SET or RESET).
-  */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{ 
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-
-  /* Clear the selected flag */
-  I2Cx->ICR = I2C_FLAG;
-  }
-
-/**
-  * @brief  Checks whether the specified I2C interrupt has occurred or not.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg I2C_IT_TXIS: Transmit interrupt status
-  *     @arg I2C_IT_RXNE: Receive data register not empty
-  *     @arg I2C_IT_ADDR: Address matched (slave mode)
-  *     @arg I2C_IT_NACKF: NACK received flag
-  *     @arg I2C_IT_STOPF: STOP detection flag
-  *     @arg I2C_IT_TC: Transfer complete (master mode)
-  *     @arg I2C_IT_TCR: Transfer complete reload
-  *     @arg I2C_IT_BERR: Bus error
-  *     @arg I2C_IT_ARLO: Arbitration lost
-  *     @arg I2C_IT_OVR: Overrun/Underrun
-  *     @arg I2C_IT_PECERR: PEC error in reception
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
-  *     @arg I2C_IT_ALERT: SMBus Alert
-  * @retval The new state of I2C_IT (SET or RESET).
-  */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  uint32_t tmpreg = 0;
-  ITStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_GET_IT(I2C_IT));
-  
-  /* Get the ISR register value */
-  tmpreg = I2Cx->ISR;
-  
-  /* Get flag status */
-  tmpreg &= I2C_IT;
-  
-  if(tmpreg != 0)
-  {
-    /* I2C_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* I2C_IT is reset */
-    bitstatus = RESET;
-  }
-  return bitstatus;
-} 
-
-/**
-  * @brief  Clears the I2Cx's interrupt pending bits.
-  * @param  I2Cx: where x can be 1 or 2 to select the I2C peripheral.
-  * @param  I2C_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg I2C_IT_ADDR: Address matched (slave mode)
-  *     @arg I2C_IT_NACKF: NACK received flag
-  *     @arg I2C_IT_STOPF: STOP detection flag
-  *     @arg I2C_IT_BERR: Bus error
-  *     @arg I2C_IT_ARLO: Arbitration lost
-  *     @arg I2C_IT_OVR: Overrun/Underrun
-  *     @arg I2C_IT_PECERR: PEC error in reception
-  *     @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
-  *     @arg I2C_IT_ALERT: SMBus Alert
-  * @retval The new state of I2C_IT (SET or RESET).
-  */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
-  /* Clear the selected flag */
-  I2Cx->ICR = I2C_IT;
-}
-
-/**
-  * @}
-  */  
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c

@@ -1,293 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_iwdg.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Independent watchdog (IWDG) peripheral:           
-  *           + Prescaler and Counter configuration
-  *           + IWDG activation
-  *           + Flag management
-  *
-  *  @verbatim  
-  *  
-  ============================================================================== 
-                          ##### IWDG features #####
-  ============================================================================== 
-    [..] The IWDG can be started by either software or hardware (configurable
-         through option byte).
-             
-    [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
-         thus stays active even if the main clock fails.
-         Once the IWDG is started, the LSI is forced ON and cannot be disabled
-         (LSI cannot be disabled too), and the counter starts counting down from 
-         the reset value of 0xFFF. When it reaches the end of count value (0x000)
-         a system reset is generated.
-         The IWDG counter should be reloaded at regular intervals to prevent
-         an MCU reset.
-                             
-    [..] The IWDG is implemented in the VDD voltage domain that is still functional
-         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-              
-    [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
-         reset occurs.
-              
-    [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
-         The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
-         devices provide the capability to measure the LSI frequency (LSI clock
-         should be seleted as RTC clock which is internally connected to TIM10 CH1
-         input capture). The measured value can be used to have an IWDG timeout with
-         an acceptable accuracy. 
-         For more information, please refer to the STM32F0xx Reference manual.
-            
-                          ##### How to use this driver ##### 
-  ============================================================================== 
-    [..] This driver allows to use IWDG peripheral with either window option enabled
-         or disabled. To do so follow one of the two procedures below.
-    (#) Window option is enabled:    
-        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
-             in software mode (no need to enable the LSI, it will be enabled
-             by hardware).        
-        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
-             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
-        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
-        (++) Configure the IWDG counter value using IWDG_SetReload() function.
-             This value will be loaded in the IWDG counter each time the counter
-             is reloaded, then the IWDG will start counting down from this value.
-        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
-        (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
-
-    (#) Window option is disabled:    
-        (++) Enable write access to IWDG_PR and IWDG_RLR registers using
-             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
-        (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
-        (++) Configure the IWDG counter value using IWDG_SetReload() function.
-             This value will be loaded in the IWDG counter each time the counter
-             is reloaded, then the IWDG will start counting down from this value.
-        (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
-        (++) reload the IWDG counter at regular intervals during normal operation 
-             to prevent an MCU reset, using IWDG_ReloadCounter() function.
-        (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
-             in software mode (no need to enable the LSI, it will be enabled
-             by hardware).
-              
-    @endverbatim
-  *    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_iwdg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup IWDG 
-  * @brief IWDG driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
-  * @{
-  */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- *  @brief   Prescaler and Counter configuration functions
- *
-@verbatim   
-  ==============================================================================
-            ##### Prescaler and Counter configuration functions #####
-  ==============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
-  *     @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
-  * @retval None
-  */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
-  IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
-  * @brief  Sets IWDG Prescaler value.
-  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_Prescaler_4: IWDG prescaler set to 4
-  *     @arg IWDG_Prescaler_8: IWDG prescaler set to 8
-  *     @arg IWDG_Prescaler_16: IWDG prescaler set to 16
-  *     @arg IWDG_Prescaler_32: IWDG prescaler set to 32
-  *     @arg IWDG_Prescaler_64: IWDG prescaler set to 64
-  *     @arg IWDG_Prescaler_128: IWDG prescaler set to 128
-  *     @arg IWDG_Prescaler_256: IWDG prescaler set to 256
-  * @retval None
-  */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
-  IWDG->PR = IWDG_Prescaler;
-}
-
-/**
-  * @brief  Sets IWDG Reload value.
-  * @param  Reload: specifies the IWDG Reload value.
-  *   This parameter must be a number between 0 and 0x0FFF.
-  * @retval None
-  */
-void IWDG_SetReload(uint16_t Reload)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_RELOAD(Reload));
-  IWDG->RLR = Reload;
-}
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *   (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None
-  * @retval None
-  */
-void IWDG_ReloadCounter(void)
-{
-  IWDG->KR = KR_KEY_RELOAD;
-}
-
-
-/**
-  * @brief  Sets the IWDG window value.
-  * @param  WindowValue: specifies the window value to be compared to the downcounter.
-  * @retval None
-  */
-void IWDG_SetWindowValue(uint16_t WindowValue)
-{
-  /* Check the parameters */
-  assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
-  IWDG->WINR = WindowValue;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- *  @brief   IWDG activation function 
- *
-@verbatim   
- ==============================================================================
-                          ##### IWDG activation function #####
- ==============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  None.
-  * @retval None.
-  */
-void IWDG_Enable(void)
-{
-  IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Group3 Flag management function 
- *  @brief  Flag management function  
- *
-@verbatim   
- ===============================================================================
-                      ##### Flag management function ##### 
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified IWDG flag is set or not.
-  * @param  IWDG_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg IWDG_FLAG_PVU: Prescaler Value Update on going
-  *     @arg IWDG_FLAG_RVU: Reload Value Update on going
-  *     @arg IWDG_FLAG_WVU: Counter Window Value Update on going
-  * @retval The new state of IWDG_FLAG (SET or RESET).
-  */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
-  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c

@@ -1,169 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_misc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides all the miscellaneous firmware functions (add-on
-  *          to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_misc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup MISC 
-  * @brief MISC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
-  * @{
-  */
-/**
-  *
-@verbatim
- *******************************************************************************
-                   ##### Interrupts configuration functions #####
- *******************************************************************************
-    [..] This section provide functions allowing to configure the NVIC interrupts
-        (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.
-         (#) Enable and Configure the priority of the selected IRQ Channels. 
-             The priority can be 0..3. 
-
-        -@- Lower priority values gives higher priority.
-        -@- Priority Order:
-            (#@) Lowest priority.
-            (#@) Lowest hardware priority (IRQn position).  
-  
-@endverbatim
-*/
-
-/**
-  * @brief  Initializes the NVIC peripheral according to the specified
-  *         parameters in the NVIC_InitStruct.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before.    
-  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
-  *         the configuration information for the specified NVIC peripheral.
-  * @retval None
-  */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
-  uint32_t tmppriority = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
-  assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));  
-    
-  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
-  {
-    /* Compute the Corresponding IRQ Priority --------------------------------*/    
-    tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
-    tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
-    tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));    
-    
-    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
-    
-    /* Enable the Selected IRQ Channels --------------------------------------*/
-    NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-  else
-  {
-    /* Disable the Selected IRQ Channels -------------------------------------*/
-    NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
-  }
-}
-
-/**
-  * @brief  Selects the condition for the system to enter low power mode.
-  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
-  *   This parameter can be one of the following values:
-  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
-  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
-  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
-  * @param  NewState: new state of LP condition. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_LP(LowPowerMode));
-  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));  
-  
-  if (NewState != DISABLE)
-  {
-    SCB->SCR |= LowPowerMode;
-  }
-  else
-  {
-    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
-  }
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  SysTick_CLKSource: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-  
-  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
-  {
-    SysTick->CTRL |= SysTick_CLKSource_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
-  }
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c

@@ -1,542 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_pwr.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Backup Domain Access
-  *           + PVD configuration
-  *           + WakeUp pins configuration
-  *           + Low Power modes configuration
-  *           + Flags management
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_pwr.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup PWR 
-  * @brief PWR driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
-  * @{
-  */
-
-/** @defgroup PWR_Group1 Backup Domain Access function 
- *  @brief   Backup Domain Access function
- *
-@verbatim
-  ==============================================================================
-                   ##### Backup Domain Access function #####
-  ==============================================================================
-
-    [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
-         and RTC backup registers) are protected against possible stray write accesses.
-    [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void PWR_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
-  * @brief  Enables or disables access to the Backup domain registers.
-  * @note   If the HSE divided by 32 is used as the RTC clock, the 
-  *         Backup Domain Access should be kept enabled.
-  * @param  NewState: new state of the access to the Backup domain registers.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Backup Domain Access */
-    PWR->CR |= PWR_CR_DBP;
-  }
-  else
-  {
-    /* Disable the Backup Domain Access */
-    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
-  } 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- *  @brief   PVD configuration functions 
- *
-@verbatim
-  ==============================================================================
-                    ##### PVD configuration functions #####
-  ==============================================================================
-  [..]
-  (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
-      selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-  (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
-      PVD threshold. This event is internally connected to the EXTI line16
-      and can generate an interrupt if enabled through the EXTI registers.
-  (+) The PVD is stopped in Standby mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  PWR_PVDLevel: specifies the PVD detection level
-  *         This parameter can be one of the following values:
-  *             @arg PWR_PVDLevel_0: PVD detection level set to 1.9V
-  *             @arg PWR_PVDLevel_1: PVD detection level set to 2.1V
-  *             @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
-  *             @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
-  *             @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
-  *             @arg PWR_PVDLevel_5: PVD detection level set to 2.9V
-  *             @arg PWR_PVDLevel_6: PVD detection level set to 3.1V
-  *             @arg PWR_PVDLevel_7: PVD detection level set to 3.3V
-  * @retval None
-  */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-  
-  tmpreg = PWR->CR;
-  
-  /* Clear PLS[7:5] bits */
-  tmpreg &= CR_PLS_MASK;
-  
-  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
-  tmpreg |= PWR_PVDLevel;
-  
-  /* Store the new value */
-  PWR->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Power Voltage Detector(PVD).
-  * @param  NewState: new state of the PVD.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_PVDCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the PVD */
-    PWR->CR |= PWR_CR_PVDE;
-  }
-  else
-  {
-    /* Disable the PVD */
-    PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
-  } 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Group3 WakeUp pins configuration functions
- *  @brief   WakeUp pins configuration functions 
- *
-@verbatim
-  ==============================================================================
-               ##### WakeUp pin configuration functions #####
-  ==============================================================================
-
-  (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are 
-      forced in input pull down configuration and are active on rising edges.
-  (+) There are three WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the WakeUp Pin functionality.
-  * @param  PWR_WakeUpPin: specifies the WakeUpPin.
-  *         This parameter can be: PWR_WakeUpPin_1 or PWR_WakeUpPin_2.
-  * @param  NewState: new state of the WakeUp Pin functionality.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the EWUPx pin */
-    PWR->CSR |= PWR_WakeUpPin;
-  }
-  else
-  {
-    /* Disable the EWUPx pin */
-    PWR->CSR &= ~PWR_WakeUpPin;
-  }
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup PWR_Group4 Low Power modes configuration functions
- *  @brief   Low Power modes configuration functions 
- *
-@verbatim
-  ==============================================================================
-              ##### Low Power modes configuration functions #####
-  ==============================================================================
-
-    [..] The devices feature three low-power modes:
-    (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
-    (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
-    (+) Standby mode: VCORE domain powered off
-
-  *** Sleep mode *** 
-  ==================
-  [..] 
-    (+) Entry:
-        (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
-    (+) Exit:
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt 
-             controller (NVIC) can wake up the device from Sleep mode.
-
-  *** Stop mode *** 
-  =================
-  [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
-       the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register 
-       contents are preserved.
-       The voltage regulator can be configured either in normal or low-power mode.
-
-    (+) Entry:
-        (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
-             function with regulator in LowPower or with Regulator ON.
-    (+) Exit:
-        (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
-             or any internal IPs (I2C, UASRT or CEC) wakeup event.
-
-  *** Standby mode *** 
-  ====================
-  [..] The Standby mode allows to achieve the lowest power consumption. It is based 
-       on the Cortex-M0 deepsleep mode, with the voltage regulator disabled. 
-       The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14 
-       oscillator and the HSE oscillator are also switched off. SRAM and register 
-       contents are lost except for the Backup domain (RTC registers, RTC backup 
-       registers and Standby circuitry).
-   
-  [..] The voltage regulator is OFF.
-
-    (+) Entry:
-        (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
-    (+) Exit:
-        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-  *** Auto-wakeup (AWU) from low-power mode *** 
-  =============================================
-  [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper 
-       event, a time-stamp event, or a comparator event, without depending on an 
-       external interrupt (Auto-wakeup mode).
-
-    (+) RTC auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
-             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
-                   or Event modes) using the EXTI_Init() function.
-             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
-             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
-                   and RTC_AlarmCmd() functions.
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt 
-                   or Event modes) using the EXTI_Init() function.
-             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
-                   function.
-             (+++) Configure the RTC to detect the tamper or time stamp event using the
-                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
-                   functions.
-
-    (+) RTC auto-wakeup (AWU) from the Standby mode
-        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
-             (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
-             (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
-                   and RTC_AlarmCmd() functions.
-        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
-                   function.
-             (+++) Configure the RTC to detect the tamper or time stamp event using the
-                   RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
-                   functions.
-
-    (+) Comparator auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
-             event, it is necessary to:
-             (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 
-                   to be sensitive to to the selected edges (falling, rising or falling 
-                   and rising) (Interrupt or Event modes) using the EXTI_Init() function.
-             (+++) Configure the comparator to generate the event.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enters Sleep mode.
-  * @note   In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param  PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
-  *         This parameter can be one of the following values:
-  *             @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
-  *             @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
-
-  /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-  
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-}
-
-/**
-  * @brief  Enters STOP mode.
-  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
-  *         the HSI RC oscillator is selected as system clock.
-  * @note   When the voltage regulator operates in low power mode, an additional 
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption 
-  *         is higher although the startup time is reduced.
-  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
-  *         This parameter can be one of the following values:
-  *             @arg PWR_Regulator_ON: STOP mode with regulator ON
-  *             @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
-  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
-  *         This parameter can be one of the following values:
-  *             @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
-  *             @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tmpreg = PWR->CR;
-  /* Clear PDDS and LPDSR bits */
-  tmpreg &= CR_DS_MASK;
-
-  /* Set LPDSR bit according to PWR_Regulator value */
-  tmpreg |= PWR_Regulator;
-
-  /* Store the new value */
-  PWR->CR = tmpreg;
-
-  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
-}
-
-/**
-  * @brief  Enters STANDBY mode.
-  * @note   In Standby mode, all I/O pins are high impedance except for:
-  *         Reset pad (still available) 
-  *         RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, 
-  *         time-stamp, RTC Alarm out, or RTC clock calibration out.
-  *         WKUP pin 1 (PA0) if enabled.
-  * @param  None
-  * @retval None
-  */
-void PWR_EnterSTANDBYMode(void)
-{
-  /* Clear Wakeup flag */
-  PWR->CR |= PWR_CR_CWUF;
-
-  /* Select STANDBY mode */
-  PWR->CR |= PWR_CR_PDDS;
-
-  /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Group5 Flags management functions
- *  @brief   Flags management functions 
- *
-@verbatim
-  ==============================================================================
-                       ##### Flags management functions #####
-  ==============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified PWR flag is set or not.
-  * @param  PWR_FLAG: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *             @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
-  *                  event was received from the WKUP pin or from the RTC alarm 
-  *                  (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
-  *             @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the 
-  *                  system was resumed from StandBy mode.
-  *             @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD 
-  *                  is enabled by the PWR_PVDCmd() function.
-  *             @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. 
-  *                  This flag indicates the state of the internal voltage 
-  *                  reference, VREFINT.
-  * @retval The new state of PWR_FLAG (SET or RESET).
-  */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
-  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the PWR's pending flags.
-  * @param  PWR_FLAG: specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *             @arg PWR_FLAG_WU: Wake Up flag
-  *             @arg PWR_FLAG_SB: StandBy flag
-  * @retval None
-  */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
-  PWR->CR |=  PWR_FLAG << 2;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c

@@ -1,1555 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_rcc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Reset and clock control (RCC) peripheral:
-  *           + Internal/external clocks, PLL, CSS and MCO configuration
-  *           + System, AHB and APB busses clocks configuration
-  *           + Peripheral clocks configuration
-  *           + Interrupts and flags management
-  *
- @verbatim
-
- ===============================================================================
-                        ##### RCC specific features #####
- ===============================================================================
-    [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS, 
-         all peripherals are off except internal SRAM, Flash and SWD.
-         (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
-             all peripherals mapped on these busses are running at HSI speed.
-         (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
-         (#) All GPIOs are in input floating state, except the SWD pins which
-             are assigned to be used for debug purpose.
-    [..] Once the device started from reset, the user application has to:
-         (#) Configure the clock source to be used to drive the System clock
-             (if the application needs higher frequency/performance)
-         (#) Configure the System clock frequency and Flash settings
-         (#) Configure the AHB and APB busses prescalers
-         (#) Enable the clock for the peripheral(s) to be used
-         (#) Configure the clock source(s) for peripherals which clocks are not
-             derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
-
- @endverbatim
-  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RCC 
-  * @brief RCC driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- RCC registers mask -------------------------------- */
-/* RCC Flag Mask */
-#define FLAG_MASK                 ((uint8_t)0x1F)
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS          ((uint32_t)0x40021002)
-
-/* CFGR register byte 3 (Bits[31:23]) base address */
-#define CFGR_BYTE3_ADDRESS        ((uint32_t)0x40021007)
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS         ((uint32_t)0x40021009)
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS         ((uint32_t)0x4002100A)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
-  * @{
-  */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
- *
-@verbatim
- ===============================================================================
- ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
- ===============================================================================
-    [..] This section provides functions allowing to configure the internal/external clocks,
-         PLL, CSS and MCO.
-         (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly 
-             or through the PLL as System clock source.
-             The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
-         (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
-             the ADC peripheral.
-         (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
-             clock source.
-         (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
-             through the PLL as System clock source. Can be used also as RTC clock source.
-         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 
-             LSE can be used also to clock the USART and CEC peripherals.   
-         (#) PLL (clocked by HSI or HSE), for System clock.
-         (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs 
-             (HSE used directly or through PLL as System clock source), the System clock
-             is automatically switched to HSI and an interrupt is generated if enabled. 
-             The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt) 
-             exception vector.   
-         (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
-             HSE, LSE or PLL (divided by 2) clock on PA8 pin.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  * @note      HSI ON and used as system clock source 
-  * @note      HSI14, HSE and PLL OFF
-  * @note      AHB, APB prescaler set to 1.
-  * @note      CSS and MCO OFF
-  * @note      All interrupts disabled
-  * @note   However, this function doesn't modify the configuration of the
-  * @note      Peripheral clocks
-  * @note      LSI, LSE and RTC clocks
-  * @param  None
-  * @retval None
-  */
-void RCC_DeInit(void)
-{
-  /* Set HSION bit */
-  RCC->CR |= (uint32_t)0x00000001;
-
-  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
-  RCC->CFGR &= (uint32_t)0xF8FFB80C;
-  
-  /* Reset HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFFF;
-
-  /* Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
-  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
-  /* Reset PREDIV1[3:0] bits */
-  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
-  /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
-  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-  
-  /* Reset HSI14 bit */
-  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
-  /* Disable all interrupts */
-  RCC->CIR = 0x00000000;
-}
-
-/**
-  * @brief  Configures the External High Speed oscillator (HSE).
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *           software should wait on HSERDY flag to be set indicating that HSE clock
-  *           is stable and can be used to clock the PLL and/or system clock.
-  *  @note    HSE state can not be changed if it is used directly or through the
-  *           PLL as system clock. In this case, you have to select another source
-  *           of the system clock then change the HSE state (ex. disable it).
-  *  @note    The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function resets the CSSON bit, so if the Clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param RCC_HSE: specifies the new state of the HSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                       6 HSE oscillator clock cycles.
-  *     @arg RCC_HSE_ON: turn ON the HSE oscillator
-  *     @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_HSE(RCC_HSE));
-
-  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
-  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
-
-  /* Set the new HSE configuration -------------------------------------------*/
-  *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
-
-}
-
-/**
-  * @brief  Waits for HSE start-up.
-  * @note   This function waits on HSERDY flag to be set and return SUCCESS if 
-  *         this flag is set, otherwise returns ERROR if the timeout is reached 
-  *         and this flag is not set. The timeout value is defined by the constant
-  *         HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
-  *         on the HSE crystal used in your application.
-  *         - The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @param  None
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: HSE oscillator is stable and ready to use
-  *          - ERROR: HSE oscillator not yet ready
-  */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
-  __IO uint32_t StartUpCounter = 0;
-  ErrorStatus status = ERROR;
-  FlagStatus HSEStatus = RESET;
-  
-  /* Wait till HSE is ready and if timeout is reached exit */
-  do
-  {
-    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
-    StartUpCounter++;  
-  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-  
-  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
-  {
-    status = SUCCESS;
-  }
-  else
-  {
-    status = ERROR;
-  }  
-  return (status);
-}
-
-/**
-  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  *         Refer to the Application Note AN3300 for more details on how to  
-  *         calibrate the HSI.
-  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
-  *         This parameter must be a number between 0 and 0x1F.
-  * @retval None
-  */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-  
-  tmpreg = RCC->CR;
-  
-  /* Clear HSITRIM[4:0] bits */
-  tmpreg &= ~RCC_CR_HSITRIM;
-  
-  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
-  tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
-  /* Store the new value */
-  RCC->CR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
-  * @note     After enabling the HSI, the application software should wait on 
-  *           HSIRDY flag to be set indicating that HSI clock is stable and can
-  *           be used to clock the PLL and/or system clock.
-  * @note     HSI can not be stopped if it is used directly or through the PLL
-  *           as system clock. In this case, you have to select another source 
-  *           of the system clock then stop the HSI.
-  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  * @param  NewState: new state of the HSI.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-void RCC_HSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CR |= RCC_CR_HSION;
-  }
-  else
-  {
-    RCC->CR &= ~RCC_CR_HSION;
-  }
-}
-
-/**
-  * @brief  Adjusts the Internal High Speed oscillator for ADC (HSI14) 
-  *         calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  *         Refer to the Application Note AN3300 for more details on how to  
-  *         calibrate the HSI14.
-  * @param  HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
-  *         This parameter must be a number between 0 and 0x1F.
-  * @retval None
-  */
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
-  
-  tmpreg = RCC->CR2;
-  
-  /* Clear HSI14TRIM[4:0] bits */
-  tmpreg &= ~RCC_CR2_HSI14TRIM;
-  
-  /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
-  tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
-
-  /* Store the new value */
-  RCC->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Internal High Speed oscillator for ADC (HSI14).
-  * @note     After enabling the HSI14, the application software should wait on 
-  *           HSIRDY flag to be set indicating that HSI clock is stable and can
-  *           be used to clock the ADC.
-  * @note     The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
-  * @param  NewState: new state of the HSI14.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
-  *         clock cycles.
-  * @retval None
-  */
-void RCC_HSI14Cmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CR2 |= RCC_CR2_HSI14ON;
-  }
-  else
-  {
-    RCC->CR2 &= ~RCC_CR2_HSI14ON;
-  }
-}
-
-/**
-  * @brief  Enables or disables the Internal High Speed oscillator request from ADC.
-  * @param  NewState: new state of the HSI14 ADC request.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CR2 &= ~RCC_CR2_HSI14DIS;
-  }
-  else
-  {
-    RCC->CR2 |= RCC_CR2_HSI14DIS;
-  }
-}
-
-/**
-  * @brief  Configures the External Low Speed oscillator (LSE).
-  * @note     As the LSE is in the Backup domain and write access is denied to this
-  *           domain after reset, you have to enable write access using 
-  *           PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
-  *           (to be done once after reset).
-  * @note     After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
-  *           software should wait on LSERDY flag to be set indicating that LSE clock
-  *           is stable and can be used to clock the RTC.
-  * @param  RCC_LSE: specifies the new state of the LSE.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                       6 LSE oscillator clock cycles.
-  *     @arg RCC_LSE_ON: turn ON the LSE oscillator
-  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
-  * @retval None
-  */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE(RCC_LSE));
-
-  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
-  /* Reset LSEON bit */
-  RCC->BDCR &= ~(RCC_BDCR_LSEON);
-
-  /* Reset LSEBYP bit */
-  RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
-
-  /* Configure LSE */
-  RCC->BDCR |= RCC_LSE;
-}
-
-/**
-  * @brief  Configures the External Low Speed oscillator (LSE) drive capability.
-  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
-  *     @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
-  *     @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
-  *     @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
-  * @retval None
-  */
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
-  
-  /* Clear LSEDRV[1:0] bits */
-  RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
-
-  /* Set the LSE Drive */
-  RCC->BDCR |= RCC_LSEDrive;
-}
-
-/**
-  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
-  * @note     After enabling the LSI, the application software should wait on 
-  *           LSIRDY flag to be set indicating that LSI clock is stable and can
-  *           be used to clock the IWDG and/or the RTC.
-  * @note     LSI can not be disabled if the IWDG is running.
-  * @param  NewState: new state of the LSI.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-void RCC_LSICmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CSR |= RCC_CSR_LSION;
-  }
-  else
-  {
-    RCC->CSR &= ~RCC_CSR_LSION;
-  }
-}
-
-/**
-  * @brief  Configures the PLL clock source and multiplication factor.
-  * @note   This function must be used only when the PLL is disabled.
-  *
-  * @param  RCC_PLLSource: specifies the PLL entry clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
-  *     @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
-  * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
-  *         PLL source).
-  *
-  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
-  *         This parameter can be RCC_PLLMul_x where x:[2,16] 
-  *
-  * @retval None
-  */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
-  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
-  /* Clear PLL Source [16] and Multiplier [21:18] bits */
-  RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
-
-  /* Set the PLL Source and Multiplier */
-  RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
-}
-
-/**
-  * @brief  Enables or disables the PLL.
-  * @note   - After enabling the PLL, the application software should wait on 
-  *           PLLRDY flag to be set indicating that PLL clock is stable and can
-  *           be used as system clock source.
-  *         - The PLL can not be disabled if it is used as system clock source
-  *         - The PLL is disabled by hardware when entering STOP and STANDBY modes.
-  * @param  NewState: new state of the PLL.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_PLLCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CR |= RCC_CR_PLLON;
-  }
-  else
-  {
-    RCC->CR &= ~RCC_CR_PLLON;
-  }
-}
-
-/**
-  * @brief  Configures the PREDIV1 division factor.
-  * @note   This function must be used only when the PLL is disabled.
-  * @param  RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
-  *         This parameter can be RCC_PREDIV1_Divx where x:[1,16]
-  * @retval None
-  */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
-  tmpreg = RCC->CFGR2;
-  /* Clear PREDIV1[3:0] bits */
-  tmpreg &= ~(RCC_CFGR2_PREDIV1);
-  /* Set the PREDIV1 division factor */
-  tmpreg |= RCC_PREDIV1_Div;
-  /* Store the new value */
-  RCC->CFGR2 = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
-  *         the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
-  * @param  NewState: new state of the Clock Security System.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->CR |= RCC_CR_CSSON;
-  }
-  else
-  {
-    RCC->CR &= ~RCC_CR_CSSON;
-  }
-}
-
-/**
-  * @brief  Selects the clock source to output on MCO pin (PA8).
-  * @note   PA8 should be configured in alternate function mode.
-  * @param  RCC_MCOSource: specifies the clock source to output.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_MCOSource_NoClock: No clock selected.
-  *     @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
-  *     @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
-  *     @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
-  *     @arg RCC_MCOSource_SYSCLK: System clock selected.
-  *     @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
-  *     @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
-  *     @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
-  * @retval None
-  */
-void RCC_MCOConfig(uint8_t RCC_MCOSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
-    
-  /* Select MCO clock source and prescaler */
-  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS =  RCC_MCOSource;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- *  @brief   System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
-     ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
-
-    [..] This section provide functions allowing to configure the System, AHB and 
-         APB busses clocks.
-         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
-             HSE and PLL.
-             The AHB clock (HCLK) is derived from System clock through configurable prescaler
-             and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
-             and APB (PCLK) clocks are derived from AHB clock through 
-             configurable prescalers and used to clock the peripherals mapped on these busses.
-             You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
-         -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-             (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
-                  programmable prescaler: 2 or 4).
-             (+@) The CEC clock which is derived from LSE or HSI divided by 244.
-             (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
-             (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
-             (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
-                  divided by a programmable prescaler).
-                  The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
-                  clock frequency.
-             (+@) IWDG clock which is always the LSI clock.
-       
-         (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
-             Depending on the maximum frequency, the FLASH wait states (WS) should be 
-             adapted accordingly:
-        +--------------------------------------------- +
-        |  Wait states  |   HCLK clock frequency (MHz) |
-        |---------------|------------------------------|
-        |0WS(1CPU cycle)|       0 < HCLK <= 24         |
-        |---------------|------------------------------|
-        |1WS(2CPU cycle)|       24 < HCLK <= 48        |
-        +----------------------------------------------+
-
-         (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and 
-             prefetch is disabled.
-  
-    [..] It is recommended to use the following software sequences to tune the number
-         of wait states needed to access the Flash memory with the CPU frequency (HCLK).
-         (+) Increasing the CPU frequency
-         (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)" 
-              function
-         (++) Check that Flash Prefetch buffer activation is taken into account by 
-              reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
-         (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
-         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
-         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
-         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
-         (++) Check that the new CPU clock source is taken into account by reading 
-              the clock source status, using "RCC_GetSYSCLKSource()" function 
-         (+) Decreasing the CPU frequency
-         (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
-         (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
-         (++) Check that the new CPU clock source is taken into account by reading 
-              the clock source status, using "RCC_GetSYSCLKSource()" function
-         (++) Program the new number of WS, using "FLASH_SetLatency()" function
-         (++) Check that the new number of WS is taken into account by reading FLASH_ACR
-         (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)" 
-              function
-         (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
-              using the FLASH_GetPrefetchBufferStatus() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the system clock (SYSCLK).
-  * @note    The HSI is used (enabled by hardware) as system clock source after
-  *           startup from Reset, wake-up from STOP and STANDBY mode, or in case
-  *           of failure of the HSE used directly or indirectly as system clock
-  *           (if the Clock Security System CSS is enabled).
-  * @note     A switch from one clock source to another occurs only if the target
-  *           clock source is ready (clock stable after startup delay or PLL locked). 
-  *           If a clock source which is not yet ready is selected, the switch will
-  *           occur when the clock source will be ready. 
-  *           You can use RCC_GetSYSCLKSource() function to know which clock is
-  *           currently used as system clock source.  
-  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock source 
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
-  *     @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
-  *     @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
-  * @retval None
-  */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-  
-  tmpreg = RCC->CFGR;
-  
-  /* Clear SW[1:0] bits */
-  tmpreg &= ~RCC_CFGR_SW;
-  
-  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
-  tmpreg |= RCC_SYSCLKSource;
-  
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Returns the clock source used as system clock.
-  * @param  None
-  * @retval The clock source used as system clock. The returned value can be one 
-  *         of the following values:
-  *              - 0x00: HSI used as system clock
-  *              - 0x04: HSE used as system clock  
-  *              - 0x08: PLL used as system clock
-  */
-uint8_t RCC_GetSYSCLKSource(void)
-{
-  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Configures the AHB clock (HCLK).
-  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
-  *                     the system clock (SYSCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_SYSCLK_Div1:   AHB clock = SYSCLK
-  *     @arg RCC_SYSCLK_Div2:   AHB clock = SYSCLK/2
-  *     @arg RCC_SYSCLK_Div4:   AHB clock = SYSCLK/4
-  *     @arg RCC_SYSCLK_Div8:   AHB clock = SYSCLK/8
-  *     @arg RCC_SYSCLK_Div16:  AHB clock = SYSCLK/16
-  *     @arg RCC_SYSCLK_Div64:  AHB clock = SYSCLK/64
-  *     @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
-  *     @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
-  *     @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
-  * @retval None
-  */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-  
-  tmpreg = RCC->CFGR;
-  
-  /* Clear HPRE[3:0] bits */
-  tmpreg &= ~RCC_CFGR_HPRE;
-  
-  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
-  tmpreg |= RCC_SYSCLK;
-  
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the APB clock (PCLK).
-  * @param  RCC_HCLK: defines the APB clock divider. This clock is derived from 
-  *         the AHB clock (HCLK).
-  *   This parameter can be one of the following values:
-  *     @arg RCC_HCLK_Div1: APB clock = HCLK
-  *     @arg RCC_HCLK_Div2: APB clock = HCLK/2
-  *     @arg RCC_HCLK_Div4: APB clock = HCLK/4
-  *     @arg RCC_HCLK_Div8: APB clock = HCLK/8
-  *     @arg RCC_HCLK_Div16: APB clock = HCLK/16
-  * @retval None
-  */
-void RCC_PCLKConfig(uint32_t RCC_HCLK)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_PCLK(RCC_HCLK));
-  
-  tmpreg = RCC->CFGR;
-  
-  /* Clear PPRE[2:0] bits */
-  tmpreg &= ~RCC_CFGR_PPRE;
-  
-  /* Set PPRE[2:0] bits according to RCC_HCLK value */
-  tmpreg |= RCC_HCLK;
-  
-  /* Store the new value */
-  RCC->CFGR = tmpreg;
-}
-
-/**
-  * @brief  Configures the ADC clock (ADCCLK).
-  * @param  RCC_ADCCLK: defines the ADC clock source. This clock is derived 
-  *         from the HSI14 or APB clock (PCLK).
-  *         This parameter can be one of the following values:
-  *             @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
-  *             @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
-  *             @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4  
-  * @retval None
-  */
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
-{ 
-  /* Check the parameters */
-  assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
-
-  /* Clear ADCPRE bit */
-  RCC->CFGR &= ~RCC_CFGR_ADCPRE;
-  /* Set ADCPRE bits according to RCC_PCLK value */
-  RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
-
-  /* Clear ADCSW bit */
-  RCC->CFGR3 &= ~RCC_CFGR3_ADCSW; 
-  /* Set ADCSW bits according to RCC_ADCCLK value */
-  RCC->CFGR3 |= RCC_ADCCLK >> 16;  
-}
-
-/**
-  * @brief  Configures the CEC clock (CECCLK).
-  * @param  RCC_CECCLK: defines the CEC clock source. This clock is derived 
-  *         from the HSI or LSE clock.
-  *         This parameter can be one of the following values:
-  *             @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
-  *             @arg RCC_CECCLK_LSE: CEC clock = LSE
-  * @retval None
-  */
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
-{ 
-  /* Check the parameters */
-  assert_param(IS_RCC_CECCLK(RCC_CECCLK));
-
-  /* Clear CECSW bit */
-  RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
-  /* Set CECSW bits according to RCC_CECCLK value */
-  RCC->CFGR3 |= RCC_CECCLK;
-}
-
-/**
-  * @brief  Configures the I2C1 clock (I2C1CLK).
-  * @param  RCC_I2CCLK: defines the I2C1 clock source. This clock is derived 
-  *         from the HSI or System clock.
-  *         This parameter can be one of the following values:
-  *             @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
-  *             @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
-  * @retval None
-  */
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
-{ 
-  /* Check the parameters */
-  assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
-
-  /* Clear I2CSW bit */
-  RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
-  /* Set I2CSW bits according to RCC_I2CCLK value */
-  RCC->CFGR3 |= RCC_I2CCLK;
-}
-
-/**
-  * @brief  Configures the USART1 clock (USART1CLK).
-  * @param  RCC_USARTCLK: defines the USART1 clock source. This clock is derived 
-  *         from the HSI or System clock.
-  *         This parameter can be one of the following values:
-  *             @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
-  *             @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
-  *             @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
-  *             @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
-  * @retval None
-  */
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
-{ 
-  /* Check the parameters */
-  assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
-
-  /* Clear USARTSW[1:0] bit */
-  RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
-  /* Set USARTSW bits according to RCC_USARTCLK value */
-  RCC->CFGR3 |= RCC_USARTCLK;
-}
-
-/**
-  * @brief  Returns the frequencies of the System, AHB and APB busses clocks.
-  * @note    The frequency returned by this function is not the real frequency
-  *           in the chip. It is calculated based on the predefined constant and
-  *           the source selected by RCC_SYSCLKConfig():
-  *                                              
-  * @note     If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
-  *                                              
-  * @note     If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
-  *                          
-  * @note     If SYSCLK source is PLL, function returns constant HSE_VALUE(**) 
-  *             or HSI_VALUE(*) multiplied by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
-  *             8 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              return wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.   
-  *             
-  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold 
-  *         the clocks frequencies. 
-  *     
-  * @note     This function can be used by the user application to compute the 
-  *           baudrate for the communication peripherals or configure other parameters.
-  * @note     Each time SYSCLK, HCLK and/or PCLK clock changes, this function
-  *           must be called to update the structure's field. Otherwise, any
-  *           configuration based on this function will be incorrect.
-  *    
-  * @retval None
-  */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
-  uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* HSI used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-    case 0x04:  /* HSE used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
-      break;
-    case 0x08:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-      pllmull = ( pllmull >> 18) + 2;
-      
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
-      }
-      else
-      {
-        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
-        /* HSE oscillator clock selected as PREDIV1 clock entry */
-        RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
-      }      
-      break;
-    default: /* HSI used as system clock */
-      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
-      break;
-  }
-  /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = RCC->CFGR & RCC_CFGR_HPRE;
-  tmp = tmp >> 4;
-  presc = APBAHBPrescTable[tmp]; 
-  /* HCLK clock frequency */
-  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
-  /* Get PCLK prescaler */
-  tmp = RCC->CFGR & RCC_CFGR_PPRE;
-  tmp = tmp >> 8;
-  presc = APBAHBPrescTable[tmp];
-  /* PCLK clock frequency */
-  RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
-  /* ADCCLK clock frequency */
-  if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
-  {
-    /* ADC Clock is HSI14 Osc. */
-    RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
-  }
-  else
-  {
-    if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
-    {
-      /* ADC Clock is derived from PCLK/2 */
-      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
-    }
-    else
-    {
-      /* ADC Clock is derived from PCLK/4 */
-      RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
-    }
-    
-  }
-
-  /* CECCLK clock frequency */
-  if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
-  {
-    /* CEC Clock is HSI/256 */
-    RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
-  }
-  else
-  {
-    /* CECC Clock is LSE Osc. */
-    RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
-  }
-
-  /* I2C1CLK clock frequency */
-  if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
-  {
-    /* I2C1 Clock is HSI Osc. */
-    RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
-  }
-  else
-  {
-    /* I2C1 Clock is System Clock */
-    RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
-  }
-
-  /* USART1CLK clock frequency */
-  if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
-  {
-    /* USART1 Clock is PCLK */
-    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
-  }
-  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
-  {
-    /* USART1 Clock is System Clock */
-    RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
-  }
-  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
-  {
-    /* USART1 Clock is LSE Osc. */
-    RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
-  }
-  else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
-  {
-    /* USART1 Clock is HSI Osc. */
-    RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
-  }
-
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- *  @brief   Peripheral clocks configuration functions 
- *
-@verbatim
- ===============================================================================
-             #####Peripheral clocks configuration functions #####
- ===============================================================================  
-
-    [..] This section provide functions allowing to configure the Peripheral clocks. 
-         (#) The RTC clock which is derived from the LSE, LSI or  HSE_Div32 (HSE
-             divided by 32).
-         (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
-             except internal SRAM, Flash and SWD. Before to start using a peripheral you
-             have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
-             RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
-         (#) To reset the peripherals configuration (to the default state after device reset)
-             you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
-             RCC_APB1PeriphResetCmd() functions.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the RTC clock (RTCCLK).
-  * @note     As the RTC clock configuration bits are in the Backup domain and write
-  *           access is denied to this domain after reset, you have to enable write
-  *           access using PWR_BackupAccessCmd(ENABLE) function before to configure
-  *           the RTC clock source (to be done once after reset).    
-  * @note     Once the RTC clock is configured it can't be changed unless the RTC
-  *           is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
-  *             
-  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
-  *   This parameter can be one of the following values:
-  *     @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
-  *     @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
-  *     @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
-  *       
-  * @note     If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *           work in STOP and STANDBY modes, and can be used as wakeup source.
-  *           However, when the HSE clock is used as RTC clock source, the RTC
-  *           cannot be used in STOP and STANDBY modes.
-  *             
-  * @note     The maximum input clock frequency for RTC is 2MHz (when using HSE as
-  *           RTC clock source).
-  *                          
-  * @retval None
-  */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-  
-  /* Select the RTC clock source */
-  RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
-  * @brief  Enables or disables the RTC clock.
-  * @note   This function must be used only after the RTC clock source was selected
-  *         using the RCC_RTCCLKConfig function.
-  * @param  NewState: new state of the RTC clock.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-  else
-  {
-    RCC->BDCR &= ~RCC_BDCR_RTCEN;
-  }
-}
-
-/**
-  * @brief  Forces or releases the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_BDCR register.
-  * @param  NewState: new state of the Backup domain reset.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->BDCR |= RCC_BDCR_BDRST;
-  }
-  else
-  {
-    RCC->BDCR &= ~RCC_BDCR_BDRST;
-  }
-}
-
-/**
-  * @brief  Enables or disables the AHB peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.    
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
-  *         This parameter can be any combination of the following values:
-  *             @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
-  *             @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
-  *             @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
-  *             @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
-  *             @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
-  *             @arg RCC_AHBPeriph_TS:            TS clock
-  *             @arg RCC_AHBPeriph_CRC:           CRC clock
-  *             @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)  
-  *             @arg RCC_AHBPeriph_SRAM:          SRAM clock
-  *             @arg RCC_AHBPeriph_DMA1:          DMA1 clock
-  * @param  NewState: new state of the specified peripheral clock.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    RCC->AHBENR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBENR &= ~RCC_AHBPeriph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
-  *         This parameter can be any combination of the following values:
-  *             @arg RCC_APB2Periph_SYSCFG:      SYSCFG clock
-  *             @arg RCC_APB2Periph_ADC1:        ADC1 clock
-  *             @arg RCC_APB2Periph_TIM1:        TIM1 clock
-  *             @arg RCC_APB2Periph_SPI1:        SPI1 clock
-  *             @arg RCC_APB2Periph_USART1:      USART1 clock
-  *             @arg RCC_APB2Periph_TIM15:       TIM15 clock
-  *             @arg RCC_APB2Periph_TIM16:       TIM16 clock
-  *             @arg RCC_APB2Periph_TIM17:       TIM17 clock
-  *             @arg RCC_APB2Periph_DBGMCU:      DBGMCU clock
-  * @param  NewState: new state of the specified peripheral clock.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->APB2ENR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2ENR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
-  *         This parameter can be any combination of the following values:
-  *           @arg RCC_APB1Periph_TIM2:      TIM2 clock
-  *           @arg RCC_APB1Periph_TIM3:      TIM3 clock
-  *           @arg RCC_APB1Periph_TIM6:      TIM6 clock
-  *           @arg RCC_APB1Periph_TIM14:     TIM14 clock
-  *           @arg RCC_APB1Periph_WWDG:      WWDG clock
-  *           @arg RCC_APB1Periph_SPI2:      SPI2 clock
-  *           @arg RCC_APB1Periph_USART2:    USART2 clock
-  *           @arg RCC_APB1Periph_I2C1:      I2C1 clock
-  *           @arg RCC_APB1Periph_I2C2:      I2C2 clock
-  *           @arg RCC_APB1Periph_PWR:       PWR clock
-  *           @arg RCC_APB1Periph_DAC:       DAC clock
-  *           @arg RCC_APB1Periph_CEC:       CEC clock                               
-  * @param  NewState: new state of the specified peripheral clock.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->APB1ENR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1ENR &= ~RCC_APB1Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases AHB peripheral reset.
-  * @param  RCC_AHBPeriph: specifies the AHB peripheral to reset.
-  *         This parameter can be any combination of the following values:
-  *             @arg RCC_AHBPeriph_GPIOA:         GPIOA clock
-  *             @arg RCC_AHBPeriph_GPIOB:         GPIOB clock
-  *             @arg RCC_AHBPeriph_GPIOC:         GPIOC clock
-  *             @arg RCC_AHBPeriph_GPIOD:         GPIOD clock
-  *             @arg RCC_AHBPeriph_GPIOF:         GPIOF clock
-  *             @arg RCC_AHBPeriph_TS:            TS clock
-  * @param  NewState: new state of the specified peripheral reset.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->AHBRSTR |= RCC_AHBPeriph;
-  }
-  else
-  {
-    RCC->AHBRSTR &= ~RCC_AHBPeriph;
-  }
-}
-
-/**
-  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
-  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
-  *         This parameter can be any combination of the following values:
-  *             @arg RCC_APB2Periph_SYSCFG:      SYSCFG clock
-  *             @arg RCC_APB2Periph_ADC1:        ADC1 clock
-  *             @arg RCC_APB2Periph_TIM1:        TIM1 clock
-  *             @arg RCC_APB2Periph_SPI1:        SPI1 clock
-  *             @arg RCC_APB2Periph_USART1:      USART1 clock
-  *             @arg RCC_APB2Periph_TIM15:       TIM15 clock
-  *             @arg RCC_APB2Periph_TIM16:       TIM16 clock
-  *             @arg RCC_APB2Periph_TIM17:       TIM17 clock
-  *             @arg RCC_APB2Periph_DBGMCU:      DBGMCU clock
-  * @param  NewState: new state of the specified peripheral reset.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->APB2RSTR |= RCC_APB2Periph;
-  }
-  else
-  {
-    RCC->APB2RSTR &= ~RCC_APB2Periph;
-  }
-}
-
-/**
-  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
-  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
-  *         This parameter can be any combination of the following values:
-  *           @arg RCC_APB1Periph_TIM2:      TIM2 clock
-  *           @arg RCC_APB1Periph_TIM3:      TIM3 clock
-  *           @arg RCC_APB1Periph_TIM6:      TIM6 clock
-  *           @arg RCC_APB1Periph_TIM14:     TIM14 clock
-  *           @arg RCC_APB1Periph_WWDG:      WWDG clock
-  *           @arg RCC_APB1Periph_SPI2:      SPI2 clock
-  *           @arg RCC_APB1Periph_USART2:    USART2 clock
-  *           @arg RCC_APB1Periph_I2C1:      I2C1 clock
-  *           @arg RCC_APB1Periph_I2C2:      I2C2 clock
-  *           @arg RCC_APB1Periph_PWR:       PWR clock
-  *           @arg RCC_APB1Periph_DAC:       DAC clock
-  *           @arg RCC_APB1Periph_CEC:       CEC clock
-  * @param  NewState: new state of the specified peripheral clock.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    RCC->APB1RSTR |= RCC_APB1Periph;
-  }
-  else
-  {
-    RCC->APB1RSTR &= ~RCC_APB1Periph;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions 
- *
-@verbatim
- ===============================================================================
-             ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified RCC interrupts.
-  * @note   The CSS interrupt doesn't have an enable bit; once the CSS is enabled
-  *         and if the HSE clock fails, the CSS interrupt occurs and an NMI is
-  *         automatically generated. The NMI will be executed indefinitely, and 
-  *         since NMI has higher priority than any other IRQ (and main program)
-  *         the application will be stacked in the NMI ISR unless the CSS interrupt
-  *         pending bit is cleared.
-  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *              @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *              @arg RCC_IT_LSERDY: LSE ready interrupt
-  *              @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *              @arg RCC_IT_HSERDY: HSE ready interrupt
-  *              @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *              @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
-  * @param  NewState: new state of the specified RCC interrupts.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_IT(RCC_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
-  }
-  else
-  {
-    /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
-    *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
-  }
-}
-
-/**
-  * @brief  Checks whether the specified RCC flag is set or not.
-  * @param  RCC_FLAG: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *             @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready  
-  *             @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
-  *             @arg RCC_FLAG_PLLRDY: PLL clock ready
-  *             @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
-  *             @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
-  *             @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset 
-  *             @arg RCC_FLAG_PINRST: Pin reset
-  *             @arg RCC_FLAG_V18PWRRSTF:  V1.8 power domain reset  
-  *             @arg RCC_FLAG_PORRST: POR/PDR reset
-  *             @arg RCC_FLAG_SFTRST: Software reset
-  *             @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
-  *             @arg RCC_FLAG_WWDGRST: Window Watchdog reset
-  *             @arg RCC_FLAG_LPWRRST: Low Power reset
-  *             @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready  
-  * @retval The new state of RCC_FLAG (SET or RESET).
-  */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
-  uint32_t tmp = 0;
-  uint32_t statusreg = 0;
-  FlagStatus bitstatus = RESET;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_FLAG(RCC_FLAG));
-
-  /* Get the RCC register index */
-  tmp = RCC_FLAG >> 5;
-
-  if (tmp == 0)               /* The flag to check is in CR register */
-  {
-    statusreg = RCC->CR;
-  }
-  else if (tmp == 1)          /* The flag to check is in BDCR register */
-  {
-    statusreg = RCC->BDCR;
-  }
-  else if (tmp == 2)          /* The flag to check is in CSR register */
-  {
-    statusreg = RCC->CSR;
-  }
-  else                        /* The flag to check is in CR2 register */
-  {
-    statusreg = RCC->CR2;
-  }    
-
-  /* Get the flag position */
-  tmp = RCC_FLAG & FLAG_MASK;
-
-  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the flag status */
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC reset flags.
-  *         The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
-  *         RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
-  *         RCC_FLAG_LPWRRST.
-  * @param  None
-  * @retval None
-  */
-void RCC_ClearFlag(void)
-{
-  /* Set RMVF bit to clear the reset flags */
-  RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
-  * @brief  Checks whether the specified RCC interrupt has occurred or not.
-  * @param  RCC_IT: specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *             @arg RCC_IT_LSERDY: LSE ready interrupt
-  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *             @arg RCC_IT_HSERDY: HSE ready interrupt
-  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt 
-  *             @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval The new state of RCC_IT (SET or RESET).
-  */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
-  ITStatus bitstatus = RESET;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_GET_IT(RCC_IT));
-  
-  /* Check the status of the specified RCC interrupt */
-  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  /* Return the RCC_IT status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the RCC's interrupt pending bits.
-  * @param  RCC_IT: specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *             @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *             @arg RCC_IT_LSERDY: LSE ready interrupt
-  *             @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *             @arg RCC_IT_HSERDY: HSE ready interrupt
-  *             @arg RCC_IT_PLLRDY: PLL ready interrupt
-  *             @arg RCC_IT_HSI14RDY: HSI14 ready interrupt  
-  *             @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval None
-  */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-  
-  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
-     pending bits */
-  *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c

@@ -1,2367 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_rtc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Real-Time Clock (RTC) peripheral:
-  *           + Initialization
-  *           + Calendar (Time and Date) configuration
-  *           + Alarms (Alarm A) configuration
-  *           + Daylight Saving configuration
-  *           + Output pin Configuration
-  *           + Digital Calibration configuration  
-  *           + TimeStamp configuration
-  *           + Tampers configuration
-  *           + Backup Data Registers configuration
-  *           + Output Type Config configuration
-  *           + Shift control synchronisation  
-  *           + Interrupts and flags management
-  *
- @verbatim
- ===============================================================================
-                    ##### Backup Domain Operating Condition #####
- ===============================================================================
-    [..] The real-time clock (RTC) and the RTC backup registers can be powered
-         from the VBAT voltage when the main VDD supply is powered off.
-         To retain the content of the RTC backup registers and supply the RTC 
-         when VDD is turned off, VBAT pin can be connected to an optional
-         standby voltage supplied by a battery or by another source.
-  
-    [..] To allow the RTC to operate even when the main digital supply (VDD) 
-         is turned off, the VBAT pin powers the following blocks:
-           (#) The RTC
-           (#) The LSE oscillator
-           (#) PC13 to PC15 I/Os I/Os (when available)
-  
-    [..] When the backup domain is supplied by VDD (analog switch connected 
-         to VDD), the following functions are available:
-           (#) PC14 and PC15 can be used as either GPIO or LSE pins
-           (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-  
-    [..] When the backup domain is supplied by VBAT (analog switch connected 
-         to VBAT because VDD is not present), the following functions are available:
-           (#) PC14 and PC15 can be used as LSE pins only
-           (#) PC13 can be used as the RTC_AF1 pin 
-  
-                     ##### Backup Domain Reset #####
- ===============================================================================
-    [..] The backup domain reset sets all RTC registers and the RCC_BDCR 
-         register to their reset values. 
-         A backup domain reset is generated when one of the following events
-         occurs:
-           (#) Software reset, triggered by setting the BDRST bit in the 
-               RCC Backup domain control register (RCC_BDCR). You can use the
-               RCC_BackupResetCmd().
-           (#) VDD or VBAT power on, if both supplies have previously been
-               powered off.
-  
-                     ##### Backup Domain Access #####
- ===============================================================================
-    [..] After reset, the backup domain (RTC registers and RTC backup data 
-         registers) is protected against possible unwanted write accesses. 
-    [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
-         (#) Enable the Power Controller (PWR) APB1 interface clock using the
-             RCC_APB1PeriphClockCmd() function.
-         (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
-         (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
-         (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-                                                                                           
-  
-                     ##### How to use this driver #####
- ===============================================================================
-    [..]
-        (+) Enable the backup domain access (see description in the section above)
-        (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
-            RTC hour format using the RTC_Init() function.
-  
- ***Time and Date configuration ***
- ==================================
-     [..]
-        (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
-            and RTC_SetDate() functions.
-        (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
-            functions.
-        (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
-        (+) Use the RTC_DayLightSavingConfig() function to add or sub one
-            hour to the RTC Calendar.
-  
- ***Alarm configuration ***
- ========================== 
-     [..]  
-        (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
-        (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function  
-        (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
-        (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-  
- ***Outputs configuration ***
- ============================
-    [..] The RTC has 2 different outputs:
-        (+) AFO_ALARM: this output is used to manage the RTC Alarm A.
-            To output the selected RTC signal on RTC_AF1 pin, use the 
-            RTC_OutputConfig() function.                
-        (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
-            To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
-            function.                
-  
- ***Original Digital Calibration configuration ***
- =================================    
-    [..] Configure the RTC Original Digital Calibration Value and the corresponding
-         calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
-         function.
-  
- ***TimeStamp configuration ***
- ==============================
-    [..]  
-        (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp 
-            using the RTC_TimeStampCmd() function.
-        (+) To read the RTC TimeStamp Time and Date register, use the 
-            RTC_GetTimeStamp() function.
-        (+) To read the RTC TimeStamp SubSecond register, use the 
-            RTC_GetTimeStampSubSecond() function.
-  
- ***Tamper configuration ***
- ===========================
-    [..]   
-        (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
-            function. 
-        (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper 
-            filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function
-        (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
-            function.
-        (+) Configure the Tamper precharge or discharge duration using 
-            RTC_TamperPinsPrechargeDuration() function.
-        (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
-        (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
-        (+) Enable the Time stamp on Tamper detection event using  
-            RTC_TSOnTamperDetecCmd() function.     
-  
- ***Backup Data Registers configuration ***
- ==========================================
-    [..]  
-        (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
-            function.  
-        (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
-            function.  
-  
-                       ##### RTC and low power modes #####
- ===============================================================================
-    [..] The MCU can be woken up from a low power mode by an RTC alternate 
-         function.
-    [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper 
-         event detection and RTC time stamp event detection.
-         These RTC alternate functions can wake up the system from the Stop 
-         and Standby lowpower modes.
-         The system can also wake up from low power modes without depending 
-         on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
-    [..] The RTC provides a programmable time base for waking up from the 
-         Stop or Standby mode at regular intervals.
-         Wakeup from STOP and Standby modes is possible only when the RTC 
-         clock source is LSE or LSI.
-  
-               ##### Selection of RTC_AF1 alternate functions #####
- ===============================================================================
-    [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
-         (+) AFO_ALARM output
-         (+) AFO_CALIB output
-         (+) AFI_TAMPER
-         (+) AFI_TIMESTAMP
-  
-   +------------------------------------------------------------------------------------------+
-   |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2  |ALARMOUTTYPE  |
-   |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |ENABLED |  AFO_ALARM   |
-   |  and function   |          |          |           |              |        |Configuration |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |   Alarm out     |          |          |           |              | Don't  |              |
-   |   output OD     |     1    |    0     |Don't care | Don't care   | care   |      0       |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |   Alarm out     |          |          |           |              | Don't  |              |
-   |   output PP     |     1    |    0     |Don't care | Don't care   | care   |      1       |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   | Calibration out |          |          |           |              | Don't  |              |
-   |   output PP     |     0    |    1     |Don't care | Don't care   | care   |  Don't care  |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |  TAMPER input   |          |          |           |              | Don't  |              |
-   |   floating      |     0    |    0     |     1     |      0       | care   |  Don't care  |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |  TIMESTAMP and  |          |          |           |              | Don't  |              |
-   |  TAMPER input   |     0    |    0     |     1     |      1       | care   |  Don't care  |
-   |   floating      |          |          |           |              |        |              |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   | TIMESTAMP input |          |          |           |              | Don't  |              |
-   |    floating     |     0    |    0     |     0     |      1       | care   |  Don't care  |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |  Wakeup Pin 2   |     0    |    0     |     0     |      0       |   1    |  Don't care  |
-   |-----------------|----------|----------|-----------|--------------|--------|--------------|
-   |  Standard GPIO  |     0    |    0     |     0     |      0       |   0    |  Don't care  |
-   +------------------------------------------------------------------------------------------+
-  
- @endverbatim
- 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rtc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup RTC 
-  * @brief RTC driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
-                                            RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
-                                            RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \
-                                            RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
-
-#define INITMODE_TIMEOUT         ((uint32_t) 0x00004000)
-#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00008000)
-#define RECALPF_TIMEOUT          ((uint32_t) 0x00001000)
-#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
-  * @{
-  */ 
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
- ===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-
-    [..] This section provide functions allowing to initialize and configure the RTC
-         Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
-         Write protection, enter and exit the RTC initialization mode, RTC registers
-         synchronization check and reference clock detection enable.
-  
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the
-                  asynchronous prescaler to a high value to minimize consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To Configure the RTC Calendar, user application should enter
-             initialization mode. In this mode, the calendar counter is stopped
-             and its value can be updated. When the initialization sequence is
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar
-             initialization, calendar update or after wakeup from low power modes
-             the software must first clear the RSF flag. The software must then
-             wait until it is set again before reading the calendar, which means
-             that the calendar registers have been correctly copied into the
-             RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
-             implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the RTC registers to their default reset values.
-  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
-  *         registers.       
-  * @param  None
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are deinitialized
-  *          - ERROR: RTC registers are not deinitialized
-  */
-ErrorStatus RTC_DeInit(void)
-{
-  __IO uint32_t wutcounter = 0x00;
-  ErrorStatus status = ERROR;
-  
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode() == ERROR)
-  {
-    status = ERROR;
-  }  
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    RTC->TR        = (uint32_t)0x00000000;
-    RTC->DR        = (uint32_t)0x00002101;
-    RTC->CR        &= (uint32_t)0x00000000;
-    RTC->PRER      = (uint32_t)0x007F00FF;
-    RTC->ALRMAR    = (uint32_t)0x00000000;
-    RTC->SHIFTR    = (uint32_t)0x00000000;
-    RTC->CAL       = (uint32_t)0x00000000;
-    RTC->ALRMASSR  = (uint32_t)0x00000000;
-
-    /* Reset ISR register and exit initialization mode */
-    RTC->ISR = (uint32_t)0x00000000;
-    
-    /* Reset Tamper and alternate functions configuration register */
-    RTC->TAFCR = 0x00000000;
-      
-    /* Wait till the RTC RSF flag is set */
-    if (RTC_WaitForSynchro() == ERROR)
-    {
-      status = ERROR;
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-
-  }
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;  
-
-  return status;
-}
-
-/**
-  * @brief  Initializes the RTC registers according to the specified parameters 
-  *         in RTC_InitStruct.
-  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
-  *         the configuration information for the RTC peripheral.
-  * @note   The RTC Prescaler register is write protected and can be written in 
-  *         initialization mode only.  
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are initialized
-  *          - ERROR: RTC registers are not initialized  
-  */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode() == ERROR)
-  {
-    status = ERROR;
-  }
-  else
-  {
-    /* Clear RTC CR FMT Bit */
-    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
-    /* Set RTC_CR register */
-    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-  
-    /* Configure the RTC PRER */
-    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
-    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
-    /* Exit Initialization mode */
-    RTC_ExitInitMode();
-
-    status = SUCCESS;
-  }
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-
-  return status;
-}
-
-/**
-  * @brief  Fills each RTC_InitStruct member with its default value.
-  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
-  *         initialized.
-  * @retval None
-  */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
-  /* Initialize the RTC_HourFormat member */
-  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
-  /* Initialize the RTC_AsynchPrediv member */
-  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
-  /* Initialize the RTC_SynchPrediv member */
-  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
-}
-
-/**
-  * @brief  Enables or disables the RTC registers write protection.
-  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
-  *         RTC_TAFCR and RTC_BKPxR.
-  * @note   Writing a wrong key reactivates the write protection.
-  * @note   The protection mechanism is not affected by system reset.
-  * @param  NewState: new state of the write protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the write protection for RTC registers */
-    RTC->WPR = 0xFF;
-  }
-  else
-  {
-    /* Disable the write protection for RTC registers */
-    RTC->WPR = 0xCA;
-    RTC->WPR = 0x53;
-  }
-}
-
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the 
-  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.
-  * @param  None
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC is in Init mode
-  *          - ERROR: RTC is not in Init mode
-  */
-ErrorStatus RTC_EnterInitMode(void)
-{
-  __IO uint32_t initcounter = 0x00;
-  ErrorStatus status = ERROR;
-  uint32_t initstatus = 0x00;
-
-  /* Check if the Initialization mode is set */
-  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-  {
-    /* Set the Initialization mode */
-    RTC->ISR = (uint32_t)RTC_INIT_MASK;
-    
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    do
-    {
-      initstatus = RTC->ISR & RTC_ISR_INITF;
-      initcounter++;  
-    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-    
-    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
-    {
-      status = SUCCESS;
-    }
-    else
-    {
-      status = ERROR;
-    }
-  }
-  else
-  {
-    status = SUCCESS;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Exits the RTC Initialization mode.
-  * @note   When the initialization sequence is complete, the calendar restarts 
-  *         counting after 4 RTCCLK cycles.  
-  * @note   The RTC Initialization mode is write protected, use the 
-  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
-  * @param  None
-  * @retval None
-  */
-void RTC_ExitInitMode(void)
-{
-  /* Exit Initialization mode */
-  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
-  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the 
-  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
-  * @note   To read the calendar through the shadow registers after Calendar 
-  *         initialization, calendar update or after wakeup from low power modes 
-  *         the software must first clear the RSF flag. 
-  *         The software must then wait until it is set again before reading 
-  *         the calendar, which means that the calendar registers have been 
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
-  * @param  None
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC registers are synchronised
-  *          - ERROR: RTC registers are not synchronised
-  */
-ErrorStatus RTC_WaitForSynchro(void)
-{
-  __IO uint32_t synchrocounter = 0;
-  ErrorStatus status = ERROR;
-  uint32_t synchrostatus = 0x00;
-
-  if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
-  {
-    /* Bypass shadow mode */
-    status = SUCCESS;
-  }
-  else
-  {
-    /* Disable the write protection for RTC registers */
-    RTC->WPR = 0xCA;
-    RTC->WPR = 0x53;
-
-    /* Clear RSF flag */
-    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
-    /* Wait the registers to be synchronised */
-    do
-    {
-      synchrostatus = RTC->ISR & RTC_ISR_RSF;
-      synchrocounter++;  
-    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
-    if ((RTC->ISR & RTC_ISR_RSF) != RESET)
-    {
-      status = SUCCESS;
-    }
-    else
-    {
-      status = ERROR;
-    }
-
-    /* Enable the write protection for RTC registers */
-    RTC->WPR = 0xFF;
-  }
-
-  return (status);
-}
-
-/**
-  * @brief  Enables or disables the RTC reference clock detection.
-  * @param  NewState: new state of the RTC reference clock.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC reference clock detection is enabled
-  *          - ERROR: RTC reference clock detection is disabled  
-  */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode() == ERROR)
-  {
-    status = ERROR;
-  }
-  else
-  {
-    if (NewState != DISABLE)
-    {
-      /* Enable the RTC reference clock detection */
-      RTC->CR |= RTC_CR_REFCKON;
-    }
-    else
-    {
-      /* Disable the RTC reference clock detection */
-      RTC->CR &= ~RTC_CR_REFCKON;
-    }
-    /* Exit Initialization mode */
-    RTC_ExitInitMode();
-
-    status = SUCCESS;
-  }
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-
-  return status;
-}
-
-/**
-  * @brief  Enables or Disables the Bypass Shadow feature.
-  * @note   When the Bypass Shadow is enabled the calendar value are taken 
-  *         directly from the Calendar counter.
-  * @param  NewState: new state of the Bypass Shadow feature.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  if (NewState != DISABLE)
-  {
-    /* Set the BYPSHAD bit */
-    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
-  }
-  else
-  {
-    /* Reset the BYPSHAD bit */
-    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
-  }
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- *  @brief   Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
-               ##### Time and Date configuration functions #####
- ===============================================================================
-    [..]  This section provide functions allowing to program and read the RTC
-          Calendar (Time and Date).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set the RTC current time.
-  * @param  RTC_Format: specifies the format of the entered parameters.
-  *   This parameter can be  one of the following values:
-  *     @arg RTC_Format_BIN:  Binary data format 
-  *     @arg RTC_Format_BCD:  BCD data format
-  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
-  *                        the time configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Time register is configured
-  *          - ERROR: RTC Time register is not configured
-  */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
-  uint32_t tmpreg = 0;
-  ErrorStatus status = ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-  
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
-      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
-    }
-    else
-    {
-      RTC_TimeStruct->RTC_H12 = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
-    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
-  }
-  else
-  {
-    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
-    } 
-    else
-    {
-      RTC_TimeStruct->RTC_H12 = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
-  }
-  
-  /* Check the input parameters format */
-  if (RTC_Format != RTC_Format_BIN)
-  {
-    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
-             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
-             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
-             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
-  }
-  else
-  {
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
-                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
-                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
-                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
-  } 
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode() == ERROR)
-  {
-    status = ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_TR register */
-    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    RTC_ExitInitMode(); 
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if (RTC_WaitForSynchro() == ERROR)
-      {
-        status = ERROR;
-      }
-      else
-      {
-        status = SUCCESS;
-      }
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-  
-  }
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-    
-  return status;
-}
-
-/**
-  * @brief  Fills each RTC_TimeStruct member with its default value
-  *         (Time = 00h:00min:00sec).
-  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
-  *         initialized.
-  * @retval None
-  */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
-  /* Time = 00h:00min:00sec */
-  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
-  RTC_TimeStruct->RTC_Hours = 0;
-  RTC_TimeStruct->RTC_Minutes = 0;
-  RTC_TimeStruct->RTC_Seconds = 0; 
-}
-
-/**
-  * @brief  Get the RTC current Time.
-  * @param  RTC_Format: specifies the format of the returned parameters.
-  *   This parameter can be  one of the following values:
-  *     @arg RTC_Format_BIN:  Binary data format 
-  *     @arg RTC_Format_BCD:  BCD data format
-  * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
-  *                        contain the returned current time configuration.
-  * @retval None
-  */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-
-  /* Get the RTC_TR register */
-  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
-  
-  /* Fill the structure fields with the read parameters */
-  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
-  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
-
-  /* Check the input parameters format */
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    /* Convert the structure parameters to Binary format */
-    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
-    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
-    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
-  }
-}
-
-/**
-  * @brief  Gets the RTC current Calendar Subseconds value.
-  * @note   This function freeze the Time and Date registers after reading the 
-  *         SSR register.
-  * @param  None
-  * @retval RTC current Calendar Subseconds value.
-  */
-uint32_t RTC_GetSubSecond(void)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Get subseconds values from the correspondent registers*/
-  tmpreg = (uint32_t)(RTC->SSR);
-  
-  /* Read DR register to unfroze calendar registers */
-  (void) (RTC->DR);
-  
-  return (tmpreg);
-}
-
-/**
-  * @brief  Set the RTC current date.
-  * @param  RTC_Format: specifies the format of the entered parameters.
-  *   This parameter can be  one of the following values:
-  *     @arg RTC_Format_BIN:  Binary data format 
-  *     @arg RTC_Format_BCD:  BCD data format
-  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
-  *                         the date configuration information for the RTC.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Date register is configured
-  *          - ERROR: RTC Date register is not configured
-  */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
-  uint32_t tmpreg = 0;
-  ErrorStatus status = ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-
-  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
-  {
-    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
-  }  
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
-    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
-    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
-  }
-  else
-  {
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
-    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
-    assert_param(IS_RTC_MONTH(tmpreg));
-    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
-    assert_param(IS_RTC_DATE(tmpreg));
-  }
-  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
-  /* Check the input parameters format */
-  if (RTC_Format != RTC_Format_BIN)
-  {
-    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
-              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
-              ((uint32_t)RTC_DateStruct->RTC_Date) | \
-              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
-  }  
-  else
-  {
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
-              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
-  }
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Set Initialization mode */
-  if (RTC_EnterInitMode() == ERROR)
-  {
-    status = ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_DR register */
-    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
-    /* Exit Initialization mode */
-    RTC_ExitInitMode(); 
-
-    /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-    if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
-    {
-      if (RTC_WaitForSynchro() == ERROR)
-      {
-        status = ERROR;
-      }
-      else
-      {
-        status = SUCCESS;
-      }
-    }
-    else
-    {
-      status = SUCCESS;
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-  
-  return status;
-}
-
-/**
-  * @brief  Fills each RTC_DateStruct member with its default value
-  *         (Monday, January 01 xx00).
-  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
-  *         initialized.
-  * @retval None
-  */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
-  /* Monday, January 01 xx00 */
-  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
-  RTC_DateStruct->RTC_Date = 1;
-  RTC_DateStruct->RTC_Month = RTC_Month_January;
-  RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
-  * @brief  Get the RTC current date.
-  * @param  RTC_Format: specifies the format of the returned parameters.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Format_BIN: Binary data format 
-  *     @arg RTC_Format_BCD: BCD data format
-  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
-  *                        contain the returned current date configuration.
-  * @retval None
-  */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-  
-  /* Get the RTC_TR register */
-  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
-
-  /* Fill the structure fields with the read parameters */
-  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
-  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
-  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
-
-  /* Check the input parameters format */
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    /* Convert the structure parameters to Binary format */
-    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
-    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
-    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
-    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);   
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- *  @brief   Alarms (Alarm A) configuration functions 
- *
-@verbatim
- ===============================================================================
-         ##### Alarms (Alarm A and Alarm B) configuration functions #####
- ===============================================================================
-    [..] This section provide functions allowing to program and read the RTC 
-         Alarms.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set the specified RTC Alarm.
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
-  * @param  RTC_Format: specifies the format of the returned parameters.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Format_BIN: Binary data format 
-  *     @arg RTC_Format_BCD: BCD data format
-  * @param  RTC_Alarm: specifies the alarm to be configured.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Alarm_A: to select Alarm A
-  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
-  *                          contains the alarm configuration parameters.
-  * @retval None
-  */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-  assert_param(IS_RTC_ALARM(RTC_Alarm));
-  assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
-      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
-    } 
-    else
-    {
-      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
-    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-    
-    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
-    }
-  }
-  else
-  {
-    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
-    } 
-    else
-    {
-      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
-    }
-    
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-    
-    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
-    {
-      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }    
-  }
-
-  /* Check the input parameters format */
-  if (RTC_Format != RTC_Format_BIN)
-  {
-    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
-              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
-              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
-              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
-              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
-              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
-              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
-  }  
-  else
-  {
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
-              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
-              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
-              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
-  }
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Configure the Alarm register */
-  RTC->ALRMAR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @brief  Fills each RTC_AlarmStruct member with its default value
-  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
-  *         all fields are masked).
-  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
-  *         will be initialized.
-  * @retval None
-  */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
-  /* Alarm Time Settings : Time = 00h:00mn:00sec */
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
-  /* Alarm Date Settings : Date = 1st day of the month */
-  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
-  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
-  /* Alarm Masks Settings : Mask =  all fields are not masked */
-  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
-  * @brief  Get the RTC Alarm value and masks.
-  * @param  RTC_Format: specifies the format of the output parameters.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Format_BIN: Binary data format 
-  *     @arg RTC_Format_BCD: BCD data format
-  * @param  RTC_Alarm: specifies the alarm to be read.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Alarm_A: to select Alarm A
-  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
-  *                          contains the output alarm configuration values.
-  * @retval None
-  */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
-
-  /* Get the RTC_ALRMAR register */
-  tmpreg = (uint32_t)(RTC->ALRMAR);
-
-  /* Fill the structure with the read parameters */
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
-                                                     RTC_ALRMAR_HU)) >> 16);
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
-                                                     RTC_ALRMAR_MNU)) >> 8);
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
-                                                     RTC_ALRMAR_SU));
-  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
-  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
-  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
-                                                        RTC_AlarmTime.RTC_Hours);
-    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
-                                                        RTC_AlarmTime.RTC_Minutes);
-    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
-                                                        RTC_AlarmTime.RTC_Seconds);
-    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
-  }  
-}
-
-/**
-  * @brief  Enables or disables the specified RTC Alarm.
-  * @param  RTC_Alarm: specifies the alarm to be configured.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_Alarm_A: to select Alarm A
-  * @param  NewState: new state of the specified alarm.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Alarm is enabled/disabled
-  *          - ERROR: RTC Alarm is not enabled/disabled  
-  */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
-  __IO uint32_t alarmcounter = 0x00;
-  uint32_t alarmstatus = 0x00;
-  ErrorStatus status = ERROR;
-    
-  /* Check the parameters */
-  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Configure the Alarm state */
-  if (NewState != DISABLE)
-  {
-    RTC->CR |= (uint32_t)RTC_Alarm;
-
-    status = SUCCESS;    
-  }
-  else
-  { 
-    /* Disable the Alarm in RTC_CR register */
-    RTC->CR &= (uint32_t)~RTC_Alarm;
-   
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    do
-    {
-      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
-      alarmcounter++;  
-    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-    
-    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
-    {
-      status = ERROR;
-    } 
-    else
-    {
-      status = SUCCESS;
-    }        
-  } 
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-  
-  return status;
-}
-
-/**
-  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.
-  * @note   This function is performed only when the Alarm is disabled. 
-  * @param  RTC_Alarm: specifies the alarm to be configured.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Alarm_A: to select Alarm A
-  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
-  *   This parameter can be a value from 0 to 0x00007FFF.
-  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
-  *                                          There is no comparison on sub seconds for Alarm.
-  *     @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
-  *                                         Only SS[0] is compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
-  *                                         Only SS[1:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
-  *                                         Only SS[2:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
-  *                                         Only SS[3:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
-  *                                         Only SS[4:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
-  *                                         Only SS[5:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
-  *                                         Only SS[6:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
-  *                                         Only SS[7:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
-  *                                         Only SS[8:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
-  *                                          Only SS[9:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
-  *                                          Only SS[10:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
-  *                                          Only SS[11:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
-  *                                          Only SS[12:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
-  *                                       Only SS[13:0] are compared
-  *     @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match
-  *                                       to activate alarm
-  * @retval None
-  */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALARM(RTC_Alarm));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-  
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  /* Configure the Alarm A or Alarm B SubSecond registers */
-  tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));
-  
-  /* Configure the AlarmA SubSecond register */
-  RTC->ALRMASSR = tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-
-}
-
-/**
-  * @brief  Gets the RTC Alarm Subseconds value.
-  * @param  RTC_Alarm: specifies the alarm to be read.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Alarm_A: to select Alarm A
-  * @param  None
-  * @retval RTC Alarm Subseconds value.
-  */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Get the RTC_ALRMAR register */
-  tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
-
-  return (tmpreg);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group4 Daylight Saving configuration functions
- *  @brief   Daylight Saving configuration functions 
- *
-@verbatim   
- ===============================================================================
-               ##### WakeUp Timer configuration functions #####
- ===============================================================================
-    [..] This section provide functions allowing to program and read the RTC WakeUp. 
-
-  This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Adds or substract one hour from the current time.
-  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
-  *   This parameter can be one of the following values:
-  *     @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
-  *     @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
-  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
-  *                             in CR register to store the operation.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_StoreOperation_Reset
-  *     @arg RTC_StoreOperation_Set
-  * @retval None
-  */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Clear the bits to be configured */
-  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
-  /* Configure the RTC_CR register */
-  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @brief  Returns the RTC Day Light Saving stored operation.
-  * @param  None
-  * @retval RTC Day Light Saving stored operation.
-  *          - RTC_StoreOperation_Reset
-  *          - RTC_StoreOperation_Set
-  */
-uint32_t RTC_GetStoreOperation(void)
-{
-  return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group5 Output pin Configuration function
- *  @brief   Output pin Configuration function 
- *
-@verbatim   
- ===============================================================================
-                  ##### Output pin Configuration function #####
- ===============================================================================
-    [..] This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the RTC output source (AFO_ALARM).
-  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Output_Disable: No output selected
-  *     @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
-  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
-  *   This parameter can be one of the following:
-  *     @arg RTC_OutputPolarity_High: The output pin is high when the 
-  *                                 ALRAF is high (depending on OSEL)
-  *     @arg RTC_OutputPolarity_Low: The output pin is low when the 
-  *                                 ALRAF is high (depending on OSEL)
-  * @retval None
-  */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_OUTPUT(RTC_Output));
-  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Clear the bits to be configured */
-  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
-  /* Configure the output selection and polarity */
-  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- *  @brief   Digital Calibration configuration functions 
- *
-@verbatim   
- ===============================================================================
-          ##### Digital Calibration configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the RTC clock to be output through the relative 
-  *         pin.
-  * @param  NewState: new state of the digital calibration Output.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the RTC clock output */
-    RTC->CR |= (uint32_t)RTC_CR_COE;
-  }
-  else
-  { 
-    /* Disable the RTC clock output */
-    RTC->CR &= (uint32_t)~RTC_CR_COE;
-  }
-  
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF; 
-}
-
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  RTC_CalibOutput : Select the Calibration output Selection .
-  *   This parameter can be one of the following values:
-  *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
-  *     @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
-  * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  /*clear flags before config*/
-  RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);
-
-  /* Configure the RTC_CR register */
-  RTC->CR |= (uint32_t)RTC_CalibOutput;
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @brief  Configures the Smooth Calibration Settings.
-  * @param  RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
-  *   This parameter can be can be one of the following values:
-  *     @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
-  *     @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
-  *     @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
-  * @param  RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
-  *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
-  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
-  *   This parameter can be one any value from 0 to 0x000001FF.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Calib registers are configured
-  *          - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
-                                  uint32_t RTC_SmoothCalibPlusPulses,
-                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
-  ErrorStatus status = ERROR;
-  uint32_t recalpfcount = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  /* check if a calibration is pending*/
-  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
-  {
-    /* wait until the Calibration is completed*/
-    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
-    {
-      recalpfcount++;
-    }
-  }
-
-  /* check if the calibration pending is completed or if there is no calibration operation at all*/
-  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
-  {
-    /* Configure the Smooth calibration settings */
-    RTC->CAL = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
-    status = SUCCESS;
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-  
-  return (ErrorStatus)(status);
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Group7 TimeStamp configuration functions
- *  @brief   TimeStamp configuration functions 
- *
-@verbatim   
- ===============================================================================
-          ##### TimeStamp configuration functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
-  *         specified time stamp pin stimulating edge.
-  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
-  *         activated.
-  *   This parameter can be one of the following:
-  *     @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
-  *                                    edge of the related pin.
-  *     @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
-  *                                     falling edge of the related pin.
-  * @param  NewState: new state of the TimeStamp.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Get the new configuration */
-  if (NewState != DISABLE)
-  {
-    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
-  }
-  else
-  {
-    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
-  }
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  RTC->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-}
-
-/**
-  * @brief  Get the RTC TimeStamp value and masks.
-  * @param  RTC_Format: specifies the format of the output parameters.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_Format_BIN: Binary data format 
-  *     @arg RTC_Format_BCD: BCD data format
-  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
-  *                             contains the TimeStamp time values. 
-  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
-  *                             contains the TimeStamp date values.     
-  * @retval None
-  */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
-                                      RTC_DateTypeDef* RTC_StampDateStruct)
-{
-  uint32_t tmptime = 0, tmpdate = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(RTC_Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
-  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
-
-  /* Fill the Date structure fields with the read parameters */
-  RTC_StampDateStruct->RTC_Year = 0;
-  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
-  /* Check the input parameters format */
-  if (RTC_Format == RTC_Format_BIN)
-  {
-    /* Convert the Time structure parameters to Binary format */
-    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
-    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
-    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
-    /* Convert the Date structure parameters to Binary format */
-    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
-    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
-    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
-  }
-}
-
-/**
-  * @brief  Get the RTC timestamp Subseconds value.
-  * @param  None
-  * @retval RTC current timestamp Subseconds value.
-  */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
-  /* Get timestamp subseconds values from the correspondent registers */
-  return (uint32_t)(RTC->TSSSR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group8 Tampers configuration functions
- *  @brief   Tampers configuration functions 
- *
-@verbatim   
- ===============================================================================
-          ##### Tampers configuration functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the select Tamper pin edge.
-  * @param  RTC_Tamper: Selected tamper pin.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_Tamper_1: Select Tamper 1.
-  *     @arg RTC_Tamper_2: Select Tamper 2.
-  *     @arg RTC_Tamper_3: Select Tamper 3.
-  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
-  *                            stimulates tamper event. 
-  *   This parameter can be one of the following values:
-  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
-  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
-  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
-  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
-  * @retval None
-  */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
-  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
- 
-  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
-  {  
-    /* Configure the RTC_TAFCR register */
-    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
-  }
-  else
-  { 
-    /* Configure the RTC_TAFCR register */
-    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
-  }  
-}
-
-/**
-  * @brief  Enables or Disables the Tamper detection.
-  * @param  RTC_Tamper: Selected tamper pin.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_Tamper_1: Select Tamper 1.
-  *     @arg RTC_Tamper_2: Select Tamper 2.
-  *     @arg RTC_Tamper_3: Select Tamper 3.
-  * @param  NewState: new state of the tamper pin.
-  *         This parameter can be: ENABLE or DISABLE.                   
-  * @retval None
-  */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected Tamper pin */
-    RTC->TAFCR |= (uint32_t)RTC_Tamper;
-  }
-  else
-  {
-    /* Disable the selected Tamper pin */
-    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
-  }  
-}
-
-/**
-  * @brief  Configures the Tampers Filter.
-  * @param  RTC_TamperFilter: Specifies the tampers filter.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
-  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
-  *                                    samples at the active level 
-  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
-  *                                    samples at the active level
-  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
-  *                                    samples at the active level 
-  * @retval None
-  */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-   
-  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
-  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
-  /* Configure the RTC_TAFCR register */
-  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
-  * @brief  Configures the Tampers Sampling Frequency.
-  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 32768
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 16384
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 8192
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 4096
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 2048
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 1024
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 512  
-  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
-  *                                           with a frequency =  RTCCLK / 256  
-  * @retval None
-  */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
- 
-  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
-  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
-  /* Configure the RTC_TAFCR register */
-  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
-  * @brief  Configures the Tampers Pins input Precharge Duration.
-  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
-  *         Precharge Duration.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
-  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
-  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
-  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
-  * @retval None
-  */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-   
-  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
-  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
-  /* Configure the RTC_TAFCR register */
-  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
-  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
-  * @note   The timestamp is valid even the TSE bit in tamper control register 
-  *         is reset.   
-  * @param  NewState: new state of the timestamp on tamper event.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-   
-  if (NewState != DISABLE)
-  {
-    /* Save timestamp on tamper detection event */
-    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
-  }
-  else
-  {
-    /* Tamper detection does not cause a timestamp to be saved */
-    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
-  }
-}
-
-/**
-  * @brief  Enables or Disables the Precharge of Tamper pin.
-  * @param  NewState: new state of tamper pull up.
-  *   This parameter can be: ENABLE or DISABLE.                   
-  * @retval None
-  */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
- if (NewState != DISABLE)
-  {
-    /* Enable precharge of the selected Tamper pin */
-    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
-  }
-  else
-  {
-    /* Disable precharge of the selected Tamper pin */
-    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
-  } 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group9 Backup Data Registers configuration functions
- *  @brief   Backup Data Registers configuration functions  
- *
-@verbatim   
- ===============================================================================
-          ##### Backup Data Registers configuration functions ##### 
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @param  RTC_BKP_DR: RTC Backup data Register number.
-  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to 
-  *                          specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.                     
-  * @retval None
-  */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
-  tmp = RTC_BASE + 0x50;
-  tmp += (RTC_BKP_DR * 4);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  RTC_BKP_DR: RTC Backup data Register number.
-  *   This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                          specify the register.                   
-  * @retval None
-  */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
-  tmp = RTC_BASE + 0x50;
-  tmp += (RTC_BKP_DR * 4);
-  
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group10 Output Type Config configuration functions
- *  @brief   Output Type Config configuration functions  
- *
-@verbatim   
- ===============================================================================
-             ##### Output Type Config configuration functions ##### 
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the RTC Output Pin mode. 
-  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
-  *                                    Open Drain mode.
-  *     @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
-  *                                    Push Pull mode.    
-  * @retval None
-  */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-  
-  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
-  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group11 Shift control synchronisation functions
- *  @brief   Shift control synchronisation functions 
- *
-@verbatim   
- ===============================================================================
-            ##### Shift control synchronisation functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register 
-  * @param  RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
-  *   This parameter can be one of the following values :
-  *     @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. 
-  *     @arg RTC_ShiftAdd1S_Reset: No effect.
-  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
-  *         This parameter can be one any value from 0 to 0x7FFF.
-  * @retval An ErrorStatus enumeration value:
-  *          - SUCCESS: RTC Shift registers are configured
-  *          - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
-  ErrorStatus status = ERROR;
-  uint32_t shpfcount = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-  
-  /* Check if a Shift is pending*/
-  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
-  {
-    /* Wait until the shift is completed*/
-    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
-    {
-      shpfcount++;
-    }
-  }
-
-  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
-  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
-  {
-    /* check if the reference clock detection is disabled */
-    if((RTC->CR & RTC_CR_REFCKON) == RESET)
-    {
-      /* Configure the Shift settings */
-      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-    
-      if(RTC_WaitForSynchro() == ERROR)
-      {
-        status = ERROR;
-      }
-      else
-      {
-        status = SUCCESS;
-      }
-    }
-    else
-    {
-      status = ERROR;
-    }
-  }
-  else
-  {
-    status = ERROR;
-  }
-
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF;
-  
-  return (ErrorStatus)(status);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Group12 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions  
- *
-@verbatim   
- ===============================================================================
-            ##### Interrupts and flags management functions #####
- ===============================================================================  
-    [..] All RTC interrupts are connected to the EXTI controller.
- 
-         (+) To enable the RTC Alarm interrupt, the following sequence is required:
-             (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising 
-                  edge sensitivity using the EXTI_Init() function.
-             (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
-                  function.
-             (++) Configure the RTC to generate RTC alarms (Alarm A) using
-                  the RTC_SetAlarm() and RTC_AlarmCmd() functions.
-
-         (+) To enable the RTC Tamper interrupt, the following sequence is required:
-             (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising 
-                  edge sensitivity using the EXTI_Init() function.
-             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
-                  function.
-             (++) Configure the RTC to detect the RTC tamper event using the 
-                  RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
-
-         (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
-             (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising 
-                  edge sensitivity using the EXTI_Init() function.
-             (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
-                  function.
-             (++) Configure the RTC to detect the RTC time-stamp event using the 
-                  RTC_TimeStampCmd() functions.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified RTC interrupts.
-  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_TS:  Time Stamp interrupt mask
-  *     @arg RTC_IT_ALRA:  Alarm A interrupt mask
-  *     @arg RTC_IT_TAMP: Tamper event interrupt mask
-  * @param  NewState: new state of the specified RTC interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  /* Disable the write protection for RTC registers */
-  RTC->WPR = 0xCA;
-  RTC->WPR = 0x53;
-
-  if (NewState != DISABLE)
-  {
-    /* Configure the Interrupts in the RTC_CR register */
-    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
-    /* Configure the Tamper Interrupt in the RTC_TAFCR */
-    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
-  }
-  else
-  {
-    /* Configure the Interrupts in the RTC_CR register */
-    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
-    /* Configure the Tamper Interrupt in the RTC_TAFCR */
-    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
-  }
-  /* Enable the write protection for RTC registers */
-  RTC->WPR = 0xFF; 
-}
-
-/**
-  * @brief  Checks whether the specified RTC flag is set or not.
-  * @param  RTC_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_FLAG_RECALPF: RECALPF event flag
-  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
-  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag   
-  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
-  *     @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
-  *     @arg RTC_FLAG_TSF: Time Stamp event flag
-  *     @arg RTC_FLAG_ALRAF: Alarm A flag
-  *     @arg RTC_FLAG_INITF: Initialization mode flag
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
-  *     @arg RTC_FLAG_INITS: Registers Configured flag
-  * @retval The new state of RTC_FLAG (SET or RESET).
-  */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-  
-  /* Get all the flags */
-  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-  
-  /* Return the status of the flag */
-  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's pending flags.
-  * @param  RTC_FLAG: specifies the RTC flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_FLAG_TAMP3F: Tamper 3 event flag
-  *     @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
-  *     @arg RTC_FLAG_TAMP1F: Tamper 1 event flag 
-  *     @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
-  *     @arg RTC_FLAG_TSF: Time Stamp event flag
-  *     @arg RTC_FLAG_ALRAF: Alarm A flag
-  *     @arg RTC_FLAG_RSF: Registers Synchronized flag
-  * @retval None
-  */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
-  /* Clear the Flags in the RTC_ISR register */
-  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));    
-}
-
-/**
-  * @brief  Checks whether the specified RTC interrupt has occurred or not.
-  * @param  RTC_IT: specifies the RTC interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg RTC_IT_TS: Time Stamp interrupt 
-  *     @arg RTC_IT_ALRA: Alarm A interrupt 
-  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt 
-  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt 
-  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt
-  * @retval The new state of RTC_IT (SET or RESET).
-  */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint32_t tmpreg = 0, enablestatus = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_RTC_GET_IT(RTC_IT));
-  
-  /* Get the TAMPER Interrupt enable bit and pending bit */
-  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
- 
-  /* Get the Interrupt enable Status */
-  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
-  
-  /* Get the Interrupt pending bit */
-  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-  
-  /* Get the status of the Interrupt */
-  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the RTC's interrupt pending bits.
-  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg RTC_IT_TS: Time Stamp interrupt 
-  *     @arg RTC_IT_ALRA: Alarm A interrupt 
-  *     @arg RTC_IT_TAMP1: Tamper1 event interrupt
-  *     @arg RTC_IT_TAMP2: Tamper2 event interrupt
-  *     @arg RTC_IT_TAMP3: Tamper3 event interrupt 
-  * @retval None
-  */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
-  /* Get the RTC_ISR Interrupt pending bits mask */
-  tmpreg = (uint32_t)(RTC_IT >> 4);
-
-  /* Clear the interrupt pending bits in the RTC_ISR register */
-  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted.
-  * @retval Converted byte
-  */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint8_t bcdhigh = 0;
-  
-  while (Value >= 10)
-  {
-    bcdhigh++;
-    Value -= 10;
-  }
-  
-  return  ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
-  * @brief  Convert from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted.
-  * @retval Converted word
-  */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint8_t tmp = 0;
-  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
-  return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c

@@ -1,1296 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_spi.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Serial peripheral interface (SPI):
-  *           + Initialization and Configuration
-  *           + Data transfers functions
-  *           + Hardware CRC Calculation
-  *           + DMA transfers management
-  *           + Interrupts and flags management
-  *
-  *  @verbatim
-
- ===============================================================================
-                       ##### How to use this driver #####
- ===============================================================================
-    [..]
-        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
-            function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
-            function for SPI2.
-  
-        (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using 
-            RCC_AHBPeriphClockCmd() function. 
-  
-        (#) Peripherals alternate function: 
-            (++) Connect the pin to the desired peripherals' Alternate 
-                 Function (AF) using GPIO_PinAFConfig() function.
-            (++) Configure the desired pin in alternate function by:
-                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
-            (++) Select the type, pull-up/pull-down and output speed via 
-                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
-            (++) Call GPIO_Init() function.
-  
-        (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
-            Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
-            function.In I2S mode, program the Mode, Standard, Data Format, MCLK 
-            Output, Audio frequency and Polarity using I2S_Init() function.
-  
-        (#) Enable the NVIC and the corresponding interrupt using the function 
-            SPI_ITConfig() if you need to use interrupt mode. 
-  
-        (#) When using the DMA mode 
-            (++) Configure the DMA using DMA_Init() function.
-            (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
-   
-        (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
-            I2S_Cmd().
-   
-        (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. 
-  
-        (#) Optionally, you can enable/configure the following parameters without
-            re-initialization (i.e there is no need to call again SPI_Init() function):
-            (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
-                 is programmed as Data direction parameter using the SPI_Init() 
-                 function it can be possible to switch between SPI_Direction_Tx 
-                 or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
-            (++) When SPI_NSS_Soft is selected as Slave Select Management parameter 
-                 using the SPI_Init() function it can be possible to manage the 
-                 NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
-            (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
-            (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.  
-  
-        (#) To use the CRC Hardware calculation feature refer to the Peripheral 
-            CRC hardware Calculation subsection.
-  
-    @endverbatim 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_spi.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup SPI
-  * @brief SPI driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK       ((uint16_t)0x3040)
-#define CR1_CLEAR_MASK2      ((uint16_t)0xFFFB)
-#define CR2_LDMA_MASK        ((uint16_t)0x9FFF)
-
-#define I2SCFGR_CLEAR_Mask   ((uint16_t)0xF040)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
-  * @{
-  */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
- ===============================================================================
-           ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..] This section provides a set of functions allowing to initialize the SPI Direction,
-         SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
-         Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
-    [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
-         and Slave mode (details for these procedures are available in reference manual).
-         
-    [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
-         use the following function to manage the NSS bit:
-         void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-
-    [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
-         is selected, use the follwoing function to enable the NSS output feature.
-         void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-    [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:
-         void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-         And it can be managed by software in the SPI Motorola mode using this function: 
-         void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-    [..] This section provides also functions to initialize the I2S Mode, Standard, 
-         Data Format, MCLK Output, Audio frequency and Polarity.
-  
-    [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
-         and Slave mode.
-  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the SPIx peripheral registers to their default
-  *         reset values.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  if (SPIx == SPI1)
-  {
-    /* Enable SPI1 reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
-    /* Release SPI1 from reset state */
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
-  }
-  else
-  {
-    if (SPIx == SPI2)
-    {
-      /* Enable SPI2 reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
-      /* Release SPI2 from reset state */
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Fills each SPI_InitStruct member with its default value.
-  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
-  /* Initialize the SPI_Direction member */
-  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
-  /* Initialize the SPI_Mode member */
-  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
-  /* Initialize the SPI_DataSize member */
-  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
-  /* Initialize the SPI_CPOL member */
-  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
-  /* Initialize the SPI_CPHA member */
-  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
-  /* Initialize the SPI_NSS member */
-  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
-  /* Initialize the SPI_BaudRatePrescaler member */
-  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
-  /* Initialize the SPI_FirstBit member */
-  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
-  /* Initialize the SPI_CRCPolynomial member */
-  SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *         parameters in the SPI_InitStruct.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
-  *         contains the configuration information for the specified SPI peripheral.
-  * @retval None
-  */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
-  uint16_t tmpreg = 0;
-
-  /* check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  /* Check the SPI parameters */
-  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
-  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
-  assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
-  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
-  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
-  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
-  /*---------------------------- SPIx CR1 Configuration ------------------------*/
-  /* Get the SPIx CR1 value */
-  tmpreg = SPIx->CR1;
-  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
-  tmpreg &= CR1_CLEAR_MASK;
-  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
-  master/slave mode, CPOL and CPHA */
-  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
-  /* Set SSM, SSI bit according to SPI_NSS values */
-  /* Set LSBFirst bit according to SPI_FirstBit value */
-  /* Set BR bits according to SPI_BaudRatePrescaler value */
-  /* Set CPOL bit according to SPI_CPOL value */
-  /* Set CPHA bit according to SPI_CPHA value */
-  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
-                      SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
-                      SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);  
-  /* Write to SPIx CR1 */
-  SPIx->CR1 = tmpreg;
-  /*-------------------------Data Size Configuration -----------------------*/
-  /* Get the SPIx CR2 value */
-  tmpreg = SPIx->CR2;
-  /* Clear DS[3:0] bits */
-  tmpreg &=(uint16_t)~SPI_CR2_DS;
-  /* Configure SPIx: Data Size */
-  tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
-  /* Write to SPIx CR2 */
-  SPIx->CR2 = tmpreg;
-  
-  /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
-  /* Write to SPIx CRCPOLY */
-  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-  
-  /*---------------------------- SPIx CR1 Configuration ------------------------*/
-  /* Get the SPIx CR1 value */
-  tmpreg = SPIx->CR1;
-  /* Clear MSTR bit */
-  tmpreg &= CR1_CLEAR_MASK2;
-  /* Configure SPIx: master/slave mode */  
-  /* Set MSTR bit according to SPI_Mode */
-  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);  
-  /* Write to SPIx CR1 */
-  SPIx->CR1 = tmpreg;  
-  
-  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
-  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-}
-
-/**
-  * @brief  Fills each I2S_InitStruct member with its default value.
-  * @param  I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
-  * @retval None
-  */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
-  /* Initialize the I2S_Mode member */
-  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
-  /* Initialize the I2S_Standard member */
-  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
-  /* Initialize the I2S_DataFormat member */
-  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
-  /* Initialize the I2S_MCLKOutput member */
-  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
-  /* Initialize the I2S_AudioFreq member */
-  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
-  /* Initialize the I2S_CPOL member */
-  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
-  * @brief  Initializes the SPIx peripheral according to the specified 
-  *   parameters in the I2S_InitStruct.
-  * @param  SPIx: where x can be 1 to select the SPI peripheral.
-  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
-  *   contains the configuration information for the specified SPI peripheral
-  *   configured in I2S mode.
-  * @note
-  *  The function calculates the optimal prescaler needed to obtain the most 
-  *  accurate audio frequency (depending on the I2S clock source, the PLL values 
-  *  and the product configuration). But in case the prescaler value is greater 
-  *  than 511, the default value (0x02) will be configured instead.     
-  * @retval None
-  */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
-  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0;
-  RCC_ClocksTypeDef RCC_Clocks;
-  uint32_t sourceclock = 0;
-
-  /* Check the I2S parameters */
-  assert_param(IS_SPI_1_PERIPH(SPIx));
-  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
-  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
-  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
-  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; 
-  SPIx->I2SPR = 0x0002;
-
-  /* Get the I2SCFGR register value */
-  tmpreg = SPIx->I2SCFGR;
-
-  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
-  {
-    i2sodd = (uint16_t)0;
-    i2sdiv = (uint16_t)2;   
-  }
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  else
-  {
-    /* Check the frame length (For the Prescaler computing) */
-    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 1;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2;
-    }
-
-    /* I2S Clock source is System clock: Get System Clock frequency */
-    RCC_GetClocksFreq(&RCC_Clocks);      
-
-    /* Get the source clock value: based on System Clock value */
-    sourceclock = RCC_Clocks.SYSCLK_Frequency;    
-
-    /* Compute the Real divider depending on the MCLK output state with a floating point */
-    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
-    }
-    
-    /* Remove the floating point */
-    tmp = tmp / 10;
-
-    /* Check the parity of the divider */
-    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint16_t) (i2sodd << 8);
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
-  {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
-  }
-
-  /* Write to SPIx I2SPR register the computed value */
-  SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
-  /* Configure the I2S with the SPI_InitStruct values */
-  tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
-                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
-                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
-  /* Write to SPIx I2SCFGR */
-  SPIx->I2SCFGR = tmpreg;
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral */
-    SPIx->CR1 |= SPI_CR1_SPE;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral */
-    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
-  }
-}
-
-/**
-  * @brief  Enables or disables the TI Mode.
-  * @note     This function can be called only after the SPI_Init() function has 
-  *           been called. 
-  * @note     When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
-  *           are not taken into consideration and are configured by hardware 
-  *           respectively to the TI mode requirements.  
-  * @param  SPIx: where x can be 1 to select the SPI peripheral.
-  * @param  NewState: new state of the selected SPI TI communication mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_1_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the TI mode for the selected SPI peripheral */
-    SPIx->CR2 |= SPI_CR2_FRF;
-  }
-  else
-  {
-    /* Disable the TI mode for the selected SPI peripheral */
-    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
-  }
-}
-
-/**
-  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
-  * @param  SPIx: where x can be 1 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx peripheral. 
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_1_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI peripheral in I2S mode */
-    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
-  }
-  else
-  {
-    /* Disable the selected SPI peripheral in I2S mode */
-    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
-  }
-}
-
-/**
-  * @brief  Configures the data size for the selected SPI.
-  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.
-  * @param  SPI_DataSize: specifies the SPI data size.
-  *   For the SPIx peripheral this parameter can be one of the following values:
-  *     @arg SPI_DataSize_4b: Set data size to 4 bits
-  *     @arg SPI_DataSize_5b: Set data size to 5 bits
-  *     @arg SPI_DataSize_6b: Set data size to 6 bits
-  *     @arg SPI_DataSize_7b: Set data size to 7 bits
-  *     @arg SPI_DataSize_8b: Set data size to 8 bits
-  *     @arg SPI_DataSize_9b: Set data size to 9 bits
-  *     @arg SPI_DataSize_10b: Set data size to 10 bits
-  *     @arg SPI_DataSize_11b: Set data size to 11 bits
-  *     @arg SPI_DataSize_12b: Set data size to 12 bits
-  *     @arg SPI_DataSize_13b: Set data size to 13 bits
-  *     @arg SPI_DataSize_14b: Set data size to 14 bits
-  *     @arg SPI_DataSize_15b: Set data size to 15 bits
-  *     @arg SPI_DataSize_16b: Set data size to 16 bits
-  * @retval None
-  */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
-  uint16_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
-  /* Read the CR2 register */
-  tmpreg = SPIx->CR2;
-  /* Clear DS[3:0] bits */
-  tmpreg &= (uint16_t)~SPI_CR2_DS;
-  /* Set new DS[3:0] bits value */
-  tmpreg |= SPI_DataSize;
-  SPIx->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Configures the FIFO reception threshold for the selected SPI.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO 
-  *          level is greater or equal to 1/2. 
-  *     @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO 
-  *          level is greater or equal to 1/4. 
-  * @retval None
-  */
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
-
-  /* Clear FRXTH bit */
-  SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
-
-  /* Set new FRXTH bit value */
-  SPIx->CR2 |= SPI_RxFIFOThreshold;
-}
-
-/**
-  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
-  * @param  SPIx: where x can be 1 or 2  to select the SPI peripheral.
-  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_Direction_Tx: Selects Tx transmission direction
-  *     @arg SPI_Direction_Rx: Selects Rx receive direction
-  * @retval None
-  */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_DIRECTION(SPI_Direction));
-  if (SPI_Direction == SPI_Direction_Tx)
-  {
-    /* Set the Tx only mode */
-    SPIx->CR1 |= SPI_Direction_Tx;
-  }
-  else
-  {
-    /* Set the Rx only mode */
-    SPIx->CR1 &= SPI_Direction_Rx;
-  }
-}
-
-/**
-  * @brief  Configures internally by software the NSS pin for the selected SPI.
-  * @note   - This function can be called only after the SPI_Init() function has 
-  *           been called.  
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
-  *     @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
-  * @retval None
-  */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-
-  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
-  {
-    /* Set NSS pin internally by software */
-    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
-  }
-  else
-  {
-    /* Reset NSS pin internally by software */
-    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
-  }
-}
-
-/**
-  * @brief  Enables or disables the SS output for the selected SPI.
-  * @note   - This function can be called only after the SPI_Init() function has 
-  *           been called and the NSS hardware management mode is selected. 
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx SS output. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI SS output */
-    SPIx->CR2 |= SPI_CR2_SSOE;
-  }
-  else
-  {
-    /* Disable the selected SPI SS output */
-    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
-  }
-}
-
-/**
-  * @brief  Enables or disables the NSS pulse management mode.
-  * @note     This function can be called only after the SPI_Init() function has 
-  *           been called. 
-  * @note     When TI mode is selected, the control bits NSSP is not taken into 
-  *           consideration and are configured by hardware respectively to the 
-  *           TI mode requirements. 
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  NewState: new state of the NSS pulse management mode.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the NSS pulse management mode */
-    SPIx->CR2 |= SPI_CR2_NSSP;
-  }
-  else
-  {
-    /* Disable the NSS pulse management mode */
-    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);    
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Group2 Data transfers functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                    ##### Data transfers functions #####
- ===============================================================================
-    [..] This section provides a set of functions allowing to manage the SPI or I2S
-         data transfers.
-
-    [..] In reception, data are received and then stored into an internal Rx buffer while 
-         In transmission, data are first stored into an internal Tx buffer before being 
-         transmitted.
-
-    [..] The read access of the SPI_DR register can be done using 
-         SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.
-         SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function
-         and returns the Rx buffered value. Whereas a write access to the SPI_DR 
-         can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)
-         and SPI_I2S_SendData16() (when data size is superior than 8bits) function 
-         and stores the written data into Tx buffer.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
-  * @param  Data: Data to be transmitted.
-  * @retval None
-  */
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
-{
-  uint32_t spixbase = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  spixbase = (uint32_t)SPIx; 
-  spixbase += 0x0C;
-  
-  *(__IO uint8_t *) spixbase = Data;
-}
-
-/**
-  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral. 
-  * @param  Data: Data to be transmitted.
-  * @retval None
-  */
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  
-  SPIx->DR = (uint16_t)Data;
-}
-
-/**
-  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
-  * @param  SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral. 
-  * @retval The value of the received data.
-  */
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
-{
-  uint32_t spixbase = 0x00;
-  
-  spixbase = (uint32_t)SPIx; 
-  spixbase += 0x0C;
-  
-  return *(__IO uint8_t *) spixbase;
-}
-
-/**
-  * @brief  Returns the most recent received data by the SPIx peripheral. 
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral.  
-  * @retval The value of the received data.
-  */
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
-{
-  return SPIx->DR;
-}
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- *  @brief   Hardware CRC Calculation functions
- *
-@verbatim   
- ===============================================================================
-                ##### Hardware CRC Calculation functions #####
- ===============================================================================
-    [..] This section provides a set of functions allowing to manage the SPI CRC hardware 
-         calculation.SPI communication using CRC is possible through the following procedure:
-
-         (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
-             Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
-             function.
-         (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
-         (#) Enable the SPI using the SPI_Cmd() function
-         (#) Before writing the last data to the TX buffer, set the CRCNext bit using the 
-             SPI_TransmitCRC() function to indicate that after transmission of the last 
-             data, the CRC should be transmitted.
-         (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
-             bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
-             value. 
-             If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
-             can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
-    -@-
-       (+@) It is advised to don't read the calculate CRC values during the communication.
-       (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
-       when the clock is stable, that is, when the clock is in the steady state. 
-       If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
-       to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
-       the value of the SPE bit.
-       (+@) With high bitrate frequencies, be careful when transmitting the CRC.
-       As the number of used CPU cycles has to be as low as possible in the CRC 
-       transfer phase, it is forbidden to call software functions in the CRC 
-       transmission sequence to avoid errors in the last data and CRC reception. 
-       In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
-       of the last data.
-       (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
-       degradation of the SPI speed performance due to CPU accesses impacting the 
-       SPI bandwidth.
-       (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is 
-       used, the NSS pin needs to be kept low between the data phase and the CRC 
-       phase.
-       (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
-       calculation takes place even if a high level is applied on the NSS pin. 
-       This may happen for example in case of a multislave environment where the 
-       communication master addresses slaves alternately.
-       (+@) Between a slave deselection (high level on NSS) and a new slave selection
-       (low level on NSS), the CRC value should be cleared on both master and slave
-       sides in order to resynchronize the master and slave for their respective 
-       CRC calculation.
-
-    -@- To clear the CRC, follow the procedure below:
-       (#@) Disable SPI using the SPI_Cmd() function
-       (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
-       (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
-       (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the CRC calculation length for the selected SPI.
-  * @note   - This function can be called only after the SPI_Init() function has 
-  *           been called.  
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_CRCLength: specifies the SPI CRC calculation length.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
-  *     @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
-  * @retval None
-  */
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
-
-  /* Clear CRCL bit */
-  SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
-
-  /* Set new CRCL bit value */
-  SPIx->CR1 |= SPI_CRCLength;
-}
-
-/**
-  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
-  * @note   - This function can be called only after the SPI_Init() function has 
-  *           been called.   
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  NewState: new state of the SPIx CRC value calculation.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI CRC calculation */
-    SPIx->CR1 |= SPI_CR1_CRCEN;
-  }
-  else
-  {
-    /* Disable the selected SPI CRC calculation */
-    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
-  }
-}
-
-/**
-  * @brief  Transmit the SPIx CRC value.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @retval None
-  */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  /* Enable the selected SPI CRC transmission */
-  SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
-  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_CRC: specifies the CRC register to be read.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_CRC_Tx: Selects Tx CRC register
-  *     @arg SPI_CRC_Rx: Selects Rx CRC register
-  * @retval The selected CRC register value..
-  */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
-  uint16_t crcreg = 0;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_CRC(SPI_CRC));
-
-  if (SPI_CRC != SPI_CRC_Rx)
-  {
-    /* Get the Tx CRC register */
-    crcreg = SPIx->TXCRCR;
-  }
-  else
-  {
-    /* Get the Rx CRC register */
-    crcreg = SPIx->RXCRCR;
-  }
-  /* Return the selected CRC register */
-  return crcreg;
-}
-
-/**
-  * @brief  Returns the CRC Polynomial register value for the specified SPI.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @retval The CRC Polynomial register value.
-  */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
-  /* Return the CRC polynomial register */
-  return SPIx->CRCPR;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- *  @brief   DMA transfers management functions
-  *
-@verbatim   
- ===============================================================================
-                ##### DMA transfers management functions #####
- ===============================================================================
-    [..] This section provides two functions that can be used only in DMA mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral.
-  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
-  *   This parameter can be any combination of the following values:
-  *     @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
-  *     @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
-  * @param  NewState: new state of the selected SPI DMA transfer request.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI DMA requests */
-    SPIx->CR2 |= SPI_I2S_DMAReq;
-  }
-  else
-  {
-    /* Disable the selected SPI DMA requests */
-    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
-  }
-}
-
-/**
-  * @brief  Configures the number of data to transfer type(Even/Odd) for the DMA
-  *         last transfers and for the selected SPI.
-  * @note   - This function have a meaning only if DMA mode is selected and if 
-  *         the packing mode is used (data length <= 8 and DMA transfer size halfword)  
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
-  *   This parameter can be one of the following values:
-  *     @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
-  *          and number of data for reception Even.
-  *     @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
-  *          and number of data for reception Even.
-  *     @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
-  *          and number of data for reception Odd.
-  *     @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
-  *          and number of data for reception Odd.
-  * @retval None
-  */
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
-
-  /* Clear LDMA_TX and LDMA_RX bits */
-  SPIx->CR2 &= CR2_LDMA_MASK;
-
-  /* Set new LDMA_TX and LDMA_RX bits value */
-  SPIx->CR2 |= SPI_LastDMATransfer; 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions
-  *
-@verbatim   
- ===============================================================================
-             ##### Interrupts and flags management functions #####
- ===============================================================================
-    [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts 
-         sources and check or clear the flags or pending bits status.
-         The user should identify which mode will be used in his application to manage 
-         the communication: Polling mode, Interrupt mode or DMA mode. 
-
-  *** Polling Mode ***
-  ====================
-    [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
-        (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
-        (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
-        (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
-        (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
-        (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
-        (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
-        (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
-        (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
-        (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
-    [..]
-        (@)Do not use the BSY flag to handle each data transmission or reception. It is better 
-           to use the TXE and RXNE flags instead.
-
-    [..] In this Mode it is advised to use the following functions:
-        (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-        (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
-  *** Interrupt Mode ***
-  ======================
-    [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
-         and 5 pending bits: 
-    [..] Pending Bits:
-        (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
-        (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
-        (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
-        (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
-        (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
-
-    [..] Interrupt Source:
-        (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
-            interrupt.  
-        (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
-            empty interrupt.
-        (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
-    [..] In this Mode it is advised to use the following functions:
-         (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-         (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-  *** FIFO Status ***
-  ===================
-    [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
-         following function:
-         (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction); 
-
-  *** DMA Mode ***
-  ================
-    [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel 
-         requests:
-        (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
-        (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
-
-    [..] In this Mode it is advised to use the following function:
-        (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified SPI/I2S interrupts.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral.  
-  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
-  *     @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
-  *     @arg SPI_I2S_IT_ERR: Error interrupt mask
-  * @param  NewState: new state of the specified SPI interrupt.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
-  uint16_t itpos = 0, itmask = 0 ;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
-  /* Get the SPI IT index */
-  itpos = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = (uint16_t)1 << (uint16_t)itpos;
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected SPI interrupt */
-    SPIx->CR2 |= itmask;
-  }
-  else
-  {
-    /* Disable the selected SPI interrupt */
-    SPIx->CR2 &= (uint16_t)~itmask;
-  }
-}
-
-/**
-  * @brief  Returns the current SPIx Transmission FIFO filled level.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @retval The Transmission FIFO filling state.
-  *   - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
-  *   - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
-  *   - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
-  *   - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
-  */
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
-{
-  /* Get the SPIx Transmission FIFO level bits */
-  return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
-}
-
-/**
-  * @brief  Returns the current SPIx Reception FIFO filled level.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @retval The Reception FIFO filling state.
-  *   - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
-  *   - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
-  *   - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
-  *   - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
-  */
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
-{
-  /* Get the SPIx Reception FIFO level bits */
-  return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
-}
-
-/**
-  * @brief  Checks whether the specified SPI flag is set or not.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral.    
-  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
-  *     @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
-  *     @arg SPI_I2S_FLAG_BSY: Busy flag.
-  *     @arg SPI_I2S_FLAG_OVR: Overrun flag.
-  *     @arg SPI_I2S_FLAG_MODF: Mode Fault flag.
-  *     @arg SPI_I2S_FLAG_CRCERR: CRC Error flag.
-  *     @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
-  *     @arg I2S_FLAG_UDR: Underrun Error flag.
-  *     @arg I2S_FLAG_CHSIDE: Channel Side flag.   
-  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
-  */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
-  /* Check the status of the specified SPI flag */
-  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
-  {
-    /* SPI_I2S_FLAG is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_FLAG is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_FLAG status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
-  * @param  SPIx: where x can be 1 or 2 to select the SPI peripheral.
-  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
-  *   This function clears only CRCERR flag.
-  * @note     OVR (OverRun error) flag is cleared by software sequence: a read 
-  *           operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by  
-  *           a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
-  * @note     MODF (Mode Fault) flag is cleared by software sequence: a read/write 
-  *           operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
-  *           a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
-  * @retval None
-  */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
-
-  /* Clear the selected SPI CRC Error (CRCERR) flag */
-  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified SPI/I2S interrupt has occurred or not.
-  * @param  SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select 
-  *   the SPI peripheral.
-  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
-  *     @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
-  *     @arg SPI_IT_MODF: Mode Fault interrupt.
-  *     @arg SPI_I2S_IT_OVR: Overrun interrupt.
-  *     @arg I2S_IT_UDR: Underrun interrupt.  
-  *     @arg SPI_I2S_IT_FRE: Format Error interrupt.  
-  * @retval The new state of SPI_I2S_IT (SET or RESET).
-  */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
-  ITStatus bitstatus = RESET;
-  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_PERIPH(SPIx));
-  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
-  /* Get the SPI_I2S_IT index */
-  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
-  /* Get the SPI_I2S_IT IT mask */
-  itmask = SPI_I2S_IT >> 4;
-
-  /* Set the IT mask */
-  itmask = 0x01 << itmask;
-
-  /* Get the SPI_I2S_IT enable bit status */
-  enablestatus = (SPIx->CR2 & itmask) ;
-
-  /* Check the status of the specified SPI interrupt */
-  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
-  {
-    /* SPI_I2S_IT is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SPI_I2S_IT is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SPI_I2S_IT status */
-  return bitstatus;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c

@@ -1,304 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_syscfg.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the SYSCFG peripheral:
-  *           + Remapping the memory mapped at 0x00000000  
-  *           + Remapping the DMA channels
-  *           + Enabling I2C fast mode plus driving capability for I2C pins   
-  *           + Configuring the EXTI lines connection to the GPIO port
-  *           + Configuring the CFGR2 features (Connecting some internal signal
-  *             to the break input of TIM1)
-  *   
-  *  @verbatim
- ===============================================================================
-                     ##### How to use this driver #####
- ===============================================================================
-    [..] 
-               The SYSCFG registers can be accessed only when the SYSCFG 
-               interface APB clock is enabled.
-               To enable SYSCFG APB clock use:
-               RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_syscfg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup SYSCFG 
-  * @brief SYSCFG driver modules
-  * @{
-  */ 
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
-  * @{
-  */ 
-
-/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
- *  @brief   SYSCFG Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-        ##### SYSCFG Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the SYSCFG registers to their default reset values.
-  * @param  None
-  * @retval None
-  * @note   MEM_MODE bits are not affected by APB reset.
-  *         MEM_MODE bits took the value from the user option bytes.
-  * @note   CFGR2 register is not affected by APB reset.
-  *         CLABBB configuration bits are locked when set.
-  *         To unlock the configuration, perform a system reset.
-  */
-void SYSCFG_DeInit(void)
-{
-  /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
-  SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
-  /* Set EXTICRx registers to reset value */
-  SYSCFG->EXTICR[0] = 0;
-  SYSCFG->EXTICR[1] = 0;
-  SYSCFG->EXTICR[2] = 0;
-  SYSCFG->EXTICR[3] = 0;
-  /* Set CFGR2 register to reset value: clear SRAM parity error flag */
-  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
-}
-
-/**
-  * @brief  Configures the memory mapping at address 0x00000000.
-  * @param  SYSCFG_MemoryRemap: selects the memory remapping.
-  *   This parameter can be one of the following values:
-  *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000  
-  *     @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
-  *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
-  * @retval None
-  */
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
-{
-  uint32_t tmpctrl = 0;
-
-  /* Check the parameter */
-  assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
-
-  /* Get CFGR1 register value */
-  tmpctrl = SYSCFG->CFGR1;
-
-  /* Clear MEM_MODE bits */
-  tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
-
-  /* Set the new MEM_MODE bits value */
-  tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
-
-  /* Set CFGR1 register with the new memory remap configuration */
-  SYSCFG->CFGR1 = tmpctrl;
-}
-
-/**
-  * @brief  Configure the DMA channels remapping.
-  * @param  SYSCFG_DMARemap: selects the DMA channels remap.
-  *   This parameter can be one of the following values:
-  *     @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
-  *     @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
-  *     @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
-  *     @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
-  *     @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
-  * @param  NewState: new state of the DMA channel remapping. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When enabled, DMA channel of the selected peripheral is remapped
-  * @note   When disabled, Default DMA channel is mapped to the selected peripheral
-  * @note 
-  *           By default TIM17 DMA requests is mapped to channel 1
-  *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
-  *           to remap TIM17 DMA requests to channel 2
-  *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
-  *           to map TIM17 DMA requests to channel 1 (default mapping)
-  * @retval None
-  */
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Remap the DMA channel */
-    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
-  }
-  else
-  {
-    /* use the default DMA channel mapping */
-    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
-  }
-}
-
-/**
-  * @brief  Configure the I2C fast mode plus driving capability.
-  * @param  SYSCFG_I2CFastModePlus: selects the pin.
-  *   This parameter can be one of the following values:
-  *     @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
-  *     @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
-  *     @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
-  *     @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
-  * @param  NewState: new state of the DMA channel remapping. 
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   ENABLE:  Enable fast mode plus driving capability for selected pin
-  * @note   DISABLE: Disable fast mode plus driving capability for selected pin
-  * @retval None
-  */
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable fast mode plus driving capability for selected pin */
-    SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
-  }
-  else
-  {
-    /* Disable fast mode plus driving capability for selected pin */
-    SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
-  }
-}
-
-/**
-  * @brief  Selects the GPIO pin used as EXTI Line.
-  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source 
-  *                                for EXTI lines where x can be (A, B, C, D or F).
-  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
-  *         This parameter can be EXTI_PinSourcex where x can be (0..15)
-  * @retval None
-  */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
-  uint32_t tmp = 0x00;
-
-  /* Check the parameters */
-  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
-  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-  
-  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
-  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
-  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
-  * @brief  Connect the selected parameter to the break input of TIM1.
-  * @note   The selected configuration is locked and can be unlocked by system reset
-  * @param  SYSCFG_Break: selects the configuration to be connected to break
-  *         input of TIM1
-  *   This parameter can be any combination of the following values:
-  *     @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1.
-  *     @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
-  *     @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
-  * @retval None
-  */
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
-{
-  /* Check the parameter */
-  assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
-
-  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
-}
-
-/**
-  * @brief  Checks whether the specified SYSCFG flag is set or not.
-  * @param  SYSCFG_Flag: specifies the SYSCFG flag to check. 
-  *   This parameter can be one of the following values:
-  *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
-  * @retval The new state of SYSCFG_Flag (SET or RESET).
-  */
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
-{
-  FlagStatus bitstatus = RESET;
-
-  /* Check the parameter */
-  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
-  /* Check the status of the specified SPI flag */
-  if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
-  {
-    /* SYSCFG_Flag is set */
-    bitstatus = SET;
-  }
-  else
-  {
-    /* SYSCFG_Flag is reset */
-    bitstatus = RESET;
-  }
-  /* Return the SYSCFG_Flag status */
-  return  bitstatus;
-}
-
-/**
-  * @brief  Clear the selected SYSCFG flag.
-  * @param  SYSCFG_Flag: selects the flag to be cleared.
-  *   This parameter can be any combination of the following values:
-  *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
-  * @retval None
-  */
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
-{
-  /* Check the parameter */
-  assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
-  SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c

@@ -1,3208 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_tim.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the TIM peripheral:
-  *            + TimeBase management
-  *            + Output Compare management
-  *            + Input Capture management
-  *            + Interrupts, DMA and flags management
-  *            + Clocks management
-  *            + Synchronization management
-  *            + Specific interface management
-  *            + Specific remapping management      
-  *              
-  *  @verbatim
-  
- ===============================================================================
-                    ##### How to use this driver #####
- ===============================================================================
-    [..] This driver provides functions to configure and program the TIM 
-         of all STM32F0xx devices These functions are split in 8 groups: 
-         (#) TIM TimeBase management: this group includes all needed functions 
-             to configure the TM Timebase unit:
-             (++) Set/Get Prescaler.
-             (++) Set/Get Autoreload.
-             (++) Counter modes configuration.
-             (++) Set Clock division.
-             (++) Select the One Pulse mode.
-             (++) Update Request Configuration.
-             (++) Update Disable Configuration.
-             (++) Auto-Preload Configuration.
-             (++) Enable/Disable the counter.
-  
-         (#) TIM Output Compare management: this group includes all needed 
-             functions to configure the Capture/Compare unit used in Output 
-             compare mode: 
-             (++) Configure each channel, independently, in Output Compare mode.
-             (++) Select the output compare modes.
-             (++) Select the Polarities of each channel.
-             (++) Set/Get the Capture/Compare register values.
-             (++) Select the Output Compare Fast mode. 
-             (++) Select the Output Compare Forced mode.  
-             (++) Output Compare-Preload Configuration. 
-             (++) Clear Output Compare Reference.
-             (++) Select the OCREF Clear signal.
-             (++) Enable/Disable the Capture/Compare Channels.    
-  
-         (#) TIM Input Capture management: this group includes all needed 
-             functions to configure the Capture/Compare unit used in 
-             Input Capture mode:
-             (++) Configure each channel in input capture mode.
-             (++) Configure Channel1/2 in PWM Input mode.
-             (++) Set the Input Capture Prescaler.
-             (++) Get the Capture/Compare values.  
-             
-        (#) Advanced-control timers (TIM1) specific features
-            (++) Configures the Break input, dead time, Lock level, the OSSI,
-                 the OSSR State and the AOE(automatic output enable)
-            (++) Enable/Disable the TIM peripheral Main Outputs
-            (++) Select the Commutation event
-            (++) Set/Reset the Capture Compare Preload Control bit     
-  
-         (#) TIM interrupts, DMA and flags management.
-             (++) Enable/Disable interrupt sources.
-             (++) Get flags status.
-             (++) Clear flags/ Pending bits.
-             (++) Enable/Disable DMA requests. 
-             (++) Configure DMA burst mode.
-             (++) Select CaptureCompare DMA request.  
-  
-         (#) TIM clocks management: this group includes all needed functions 
-             to configure the clock controller unit:
-             (++) Select internal/External clock.
-             (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
-  
-         (#) TIM synchronization management: this group includes all needed. 
-             functions to configure the Synchronization unit:
-             (++) Select Input Trigger.  
-             (++) Select Output Trigger.  
-             (++) Select Master Slave Mode. 
-             (++) ETR Configuration when used as external trigger.   
-  
-         (#) TIM specific interface management, this group includes all 
-             needed functions to use the specific TIM interface:
-             (++) Encoder Interface Configuration.
-             (++) Select Hall Sensor.   
-  
-         (#) TIM specific remapping management includes the Remapping 
-             configuration of specific timers
-  
-@endverbatim
-  *    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_tim.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup TIM 
-  * @brief TIM driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK               ((uint16_t)0x00FF) 
-#define CCMR_OFFSET                 ((uint16_t)0x0018)
-#define CCER_CCE_SET                ((uint16_t)0x0001)
-#define CCER_CCNE_SET               ((uint16_t)0x0004) 
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
-  * @{
-  */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- *  @brief   TimeBase management functions 
- *
-@verbatim
- ===============================================================================
-                 ##### TimeBase management functions #####
- ===============================================================================
-  
-        *** TIM Driver: how to use it in Timing(Time base) Mode ***
- ===============================================================================
-    [..] To use the Timer in Timing(Time base) mode, the following steps are 
-         mandatory:
-         (#) Enable TIM clock using 
-             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
-         (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
-         (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure 
-             the Time Base unit with the corresponding configuration.
-         (#) Enable the NVIC if you need to generate the update interrupt. 
-         (#) Enable the corresponding interrupt using the function 
-             TIM_ITConfig(TIMx, TIM_IT_Update). 
-         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-    [..]
-        (@) All other functions can be used seperatly to modify, if needed,
-            a specific feature of the Timer. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @retval None
-  *   
-  */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
-
-  if (TIMx == TIM1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
-  }     
-  else if (TIMx == TIM2)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
-  }
-  else if (TIMx == TIM3)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
-  }
-  else if (TIMx == TIM6)
-  {
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
-  } 
-  else if (TIMx == TIM14) 
-  {       
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
-    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
-  }        
-  else if (TIMx == TIM15)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
-  } 
-  else if (TIMx == TIM16)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
-  } 
-  else
-  {
-    if (TIMx == TIM17)
-    {
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
-      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
-    }  
-  }
-     
-}
-
-/**
-  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
-  *         the specified parameters in the TIM_TimeBaseInitStruct.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
-  *         structure that contains the configuration information for
-  *         the specified TIM peripheral.
-  * @retval None
-  */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  uint16_t tmpcr1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
-  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
-  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
-  tmpcr1 = TIMx->CR1;  
-
-  if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
-  }
- 
-  if(TIMx != TIM6)
-  {
-    /* Set the clock division */
-    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
-    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
- 
-  /* Set the Prescaler value */
-  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-    
-  if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))  
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
-  }
-
-  /* Generate an update event to reload the Prescaler and the Repetition counter
-     values immediately */
-  TIMx->EGR = TIM_PSCReloadMode_Immediate;           
-}
-
-/**
-  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
-  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
-  *         structure which will be initialized.
-  * @retval None
-  */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
-  /* Set the default configuration */
-  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
-  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
-  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
-  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
-  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
-  * @brief  Configures the TIMx Prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @param  Prescaler: specifies the Prescaler Register value
-  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
-  *   This parameter can be one of the following values:
-  *     @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
-  *     @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
-  * @retval None
-  */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-  
-  /* Set the Prescaler value */
-  TIMx->PSC = Prescaler;
-  /* Set or reset the UG Bit */
-  TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
-  * @brief  Specifies the TIMx Counter Mode to be used.
-  * @param  TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.
-  * @param  TIM_CounterMode: specifies the Counter Mode to be used
-  *   This parameter can be one of the following values:
-  *     @arg TIM_CounterMode_Up: TIM Up Counting Mode
-  *     @arg TIM_CounterMode_Down: TIM Down Counting Mode
-  *     @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
-  *     @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
-  *     @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
-  * @retval None
-  */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
-  uint16_t tmpcr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-  
-  tmpcr1 = TIMx->CR1;
-  /* Reset the CMS and DIR Bits */
-  tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
-  /* Set the Counter Mode */
-  tmpcr1 |= TIM_CounterMode;
-  /* Write to TIMx CR1 register */
-  TIMx->CR1 = tmpcr1;
-}
-
-/**
-  * @brief  Sets the TIMx Counter Register value
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *          peripheral.
-  * @param  Counter: specifies the Counter register new value.
-  * @retval None
-  */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
-  /* Check the parameters */
-   assert_param(IS_TIM_ALL_PERIPH(TIMx));
-   
-  /* Set the Counter Register value */
-  TIMx->CNT = Counter;
-}
-
-/**
-  * @brief  Sets the TIMx Autoreload Register value
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @param  Autoreload: specifies the Autoreload register new value.
-  * @retval None
-  */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  
-  /* Set the Autoreload Register value */
-  TIMx->ARR = Autoreload;
-}
-
-/**
-  * @brief  Gets the TIMx Counter value.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @retval Counter Register value.
-  */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  
-  /* Get the Counter Register value */
-  return TIMx->CNT;
-}
-
-/**
-  * @brief  Gets the TIMx Prescaler value.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @retval Prescaler Register value.
-  */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  
-  /* Get the Prescaler Register value */
-  return TIMx->PSC;
-}
-
-/**
-  * @brief  Enables or Disables the TIMx Update event.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @param  NewState: new state of the TIMx UDIS bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Set the Update Disable Bit */
-    TIMx->CR1 |= TIM_CR1_UDIS;
-  }
-  else
-  {
-    /* Reset the Update Disable Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
-  }
-}
-
-/**
-  * @brief  Configures the TIMx Update Request Interrupt source.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @param  TIM_UpdateSource: specifies the Update source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
-                                       or the setting of UG bit, or an update generation
-                                       through the slave mode controller.
-  *     @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
-  * @retval None
-  */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-  
-  if (TIM_UpdateSource != TIM_UpdateSource_Global)
-  {
-    /* Set the URS Bit */
-    TIMx->CR1 |= TIM_CR1_URS;
-  }
-  else
-  {
-    /* Reset the URS Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
-  }
-}
-
-/**
-  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
-  * @param  TIMx: where x can be  1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @param  NewState: new state of the TIMx peripheral Preload register
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Set the ARR Preload Bit */
-    TIMx->CR1 |= TIM_CR1_ARPE;
-  }
-  else
-  {
-    /* Reset the ARR Preload Bit */
-    TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
-  }
-}
-
-/**
-  * @brief  Selects the TIMx's One Pulse Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17 to select the TIM 
-  *         peripheral.
-  * @param  TIM_OPMode: specifies the OPM Mode to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OPMode_Single
-  *     @arg TIM_OPMode_Repetitive
-  * @retval None
-  */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-  
-  /* Reset the OPM Bit */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
-  /* Configure the OPM Mode */
-  TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
-  * @brief  Sets the TIMx Clock Division value.
-  * @param  TIMx: where x can be  1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @param  TIM_CKD: specifies the clock division value.
-  *   This parameter can be one of the following value:
-  *     @arg TIM_CKD_DIV1: TDTS = Tck_tim
-  *     @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
-  *     @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
-  * @retval None
-  */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-  
-  /* Reset the CKD Bits */
-  TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
-  /* Set the CKD value */
-  TIMx->CR1 |= TIM_CKD;
-}
-
-/**
-  * @brief  Enables or disables the specified TIM peripheral.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 and 17to select the TIMx
-  *         peripheral.
-  * @param  NewState: new state of the TIMx peripheral.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Counter */
-    TIMx->CR1 |= TIM_CR1_CEN;
-  }
-  else
-  {
-    /* Disable the TIM Counter */
-    TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features
- *  @brief   Advanced-control timers (TIM1) specific features
- *
-@verbatim   
- ===============================================================================
-      ##### Advanced-control timers (TIM1) specific features #####
- ===============================================================================  
-  
-       ===================================================================      
-              *** TIM Driver: how to use the Break feature ***
-       =================================================================== 
-       [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: 
-                         
-           (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
-               Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
-               AOE(automatic output enable).
-               
-           (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-          
-           (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
-          
-           (#) Once the break even occurs, the Timer's output signals are put in reset
-               state or in a known state (according to the configuration made in
-               TIM_BDTRConfig() function).
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
-  *   the OSSR State and the AOE(automatic output enable).
-  * @param  TIMx: where x can be  1, 15, 16 or 17 to select the TIM 
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
-  *   contains the BDTR Register configuration  information for the TIM peripheral.
-  * @retval None
-  */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
-  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
-  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
-  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
-  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
-  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
-  /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
-     the OSSI State, the dead time value and the Automatic Output Enable Bit */
-  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
-             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
-             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
-             TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
-  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
-  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
-  *   will be initialized.
-  * @retval None
-  */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
-  /* Set the default configuration */
-  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
-  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
-  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
-  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
-  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
-  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
-  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
-  * @brief  Enables or disables the TIM peripheral Main Outputs.
-  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.
-  * @param  NewState: new state of the TIM peripheral Main Outputs.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the TIM Main Output */
-    TIMx->BDTR |= TIM_BDTR_MOE;
-  }
-  else
-  {
-    /* Disable the TIM Main Output */
-    TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
-  }  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group3 Output Compare management functions
- *  @brief    Output Compare management functions 
- *
-@verbatim
- ===============================================================================
-                ##### Output Compare management functions #####
- ===============================================================================
-        *** TIM Driver: how to use it in Output Compare Mode ***
- ===============================================================================
-    [..] To use the Timer in Output Compare mode, the following steps are mandatory:
-         (#) Enable TIM clock using 
-             RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
-         (#) Configure the TIM pins by configuring the corresponding GPIO pins
-         (#) Configure the Time base unit as described in the first part of this 
-             driver, if needed, else the Timer will run with the default 
-             configuration:
-             (++) Autoreload value = 0xFFFF.
-             (++) Prescaler value = 0x0000.
-             (++) Counter mode = Up counting.
-             (++) Clock Division = TIM_CKD_DIV1.
-         (#) Fill the TIM_OCInitStruct with the desired parameters including:
-             (++) The TIM Output Compare mode: TIM_OCMode.
-             (++) TIM Output State: TIM_OutputState.
-             (++) TIM Pulse value: TIM_Pulse.
-             (++) TIM Output Compare Polarity : TIM_OCPolarity.
-         (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired 
-             channel with the corresponding configuration.
-         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-    [..]
-        (@) All other functions can be used separately to modify, if needed,
-          a specific feature of the Timer.
-        (@) In case of PWM mode, this function is mandatory:
-            TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
-        (@) If the corresponding interrupt or DMA request are needed, the user should:
-            (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
-            (#@) Enable the corresponding interrupt (or DMA request) using the function
-                 TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIMx Channel1 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
- /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-  
-  /* Set the Output State */
-  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-    
-  if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
-    /* Set the Output N Polarity */
-    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
-    /* Set the Output N State */
-    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-    
-    /* Reset the Ouput Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
-    /* Set the Output N Idle state */
-    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
- 
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel2 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-   /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-  
-  /* Get the TIMx CCER register value */  
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-    
-  if(TIMx == TIM1)
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-    
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-    
-    /* Reset the Ouput Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-    
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel3 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-    
-  if(TIMx == TIM1)
-  {
-    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
-    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
-    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    
-    /* Reset the Output N Polarity level */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
-    /* Set the Output N Polarity */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
-    /* Reset the Output N State */
-    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-    
-    /* Set the Output N State */
-    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
-    /* Reset the Ouput Compare and Output Compare N IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
-    /* Set the Output N Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Initializes the TIMx Channel4 according to the specified
-  *         parameters in the TIM_OCInitStruct.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
-  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
-  /* Disable the Channel 2: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-  
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-    
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
-  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-  
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-  
-  /* Reset the Output Polarity level */
-  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
-  /* Set the Output Compare Polarity */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-  
-  /* Set the Output State */
-  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-    
-  if(TIMx == TIM1)
-  {
-    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-    /* Reset the Ouput Compare IDLE State */
-    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
-    /* Set the Output Idle state */
-    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
-  }
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-  
-  /* Write to TIMx CCMR2 */  
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-  
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Fills each TIM_OCInitStruct member with its default value.
-  * @param  TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
-  /* Set the default configuration */
-  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
-  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
-  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
-  TIM_OCInitStruct->TIM_Pulse = 0x0000000;
-  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
-  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
-  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
-  * @brief  Selects the TIM Output Compare Mode.
-  * @note   This function disables the selected channel before changing the Output
-  *         Compare Mode.
-  *         User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCMode_Timing
-  *     @arg TIM_OCMode_Active
-  *     @arg TIM_OCMode_Toggle
-  *     @arg TIM_OCMode_PWM1
-  *     @arg TIM_OCMode_PWM2
-  *     @arg TIM_ForcedAction_Active
-  *     @arg TIM_ForcedAction_InActive
-  * @retval None
-  */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
-  uint32_t tmp = 0;
-  uint16_t tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));  
-  assert_param(IS_TIM_OCM(TIM_OCMode));
-  
-  tmp = (uint32_t) TIMx;
-  tmp += CCMR_OFFSET;
-
-  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
-  /* Disable the Channel: Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp1;
-
-  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
-  {
-    tmp += (TIM_Channel>>1);
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-   
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= TIM_OCMode;
-  }
-  else
-  {
-    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
-    /* Reset the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-    
-    /* Configure the OCxM bits in the CCMRx register */
-    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
-  }
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare1 Register value
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  Compare1: specifies the Capture Compare1 register new value.
-  * @retval None
-  */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  
-  /* Set the Capture Compare1 Register value */
-  TIMx->CCR1 = Compare1;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare2 Register value
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  Compare2: specifies the Capture Compare2 register new value.
-  * @retval None
-  */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  
-  /* Set the Capture Compare2 Register value */
-  TIMx->CCR2 = Compare2;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare3 Register value
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  Compare3: specifies the Capture Compare3 register new value.
-  * @retval None
-  */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  
-  /* Set the Capture Compare3 Register value */
-  TIMx->CCR3 = Compare3;
-}
-
-/**
-  * @brief  Sets the TIMx Capture Compare4 Register value
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  Compare4: specifies the Capture Compare4 register new value.
-  * @retval None
-  */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  
-  /* Set the Capture Compare4 Register value */
-  TIMx->CCR4 = Compare4;
-}
-
-/**
-  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC1REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
-  * @retval None
-  */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
- 
-/**
-  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM 
-  *   peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC2REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
-  * @retval None
-  */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2M Bits */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
-  /* Configure The Forced output Mode */
-  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC3REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
-  * @retval None
-  */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC1M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= TIM_ForcedAction;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ForcedAction_Active: Force active level on OC4REF
-  *     @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
-  * @retval None
-  */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
-  uint16_t tmpccmr2 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC2M Bits */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
-  /* Configure The Forced output Mode */
-  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
-  * @param  TIMx: where x can be   1, 2, 3 or 15 
-  *         to select the TIMx peripheral
-  * @param  NewState: new state of the Capture Compare Preload Control bit
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the CCPC Bit */
-    TIMx->CR2 |= TIM_CR2_CCPC;
-  }
-  else
-  {
-    /* Reset the CCPC Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
-  }
-}
-
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= TIM_OCPreload;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
-  * @param  TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr1 = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2PE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= TIM_OCPreload;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCPreload_Enable
-  *     @arg TIM_OCPreload_Disable
-  * @retval None
-  */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4PE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
-  /* Enable or Disable the Output Compare Preload feature */
-  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 1 Fast feature.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= TIM_OCFast;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 2 Fast feature.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2FE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 3 Fast feature.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= TIM_OCFast;
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx Output Compare 4 Fast feature.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCFast_Enable: TIM output compare fast enable
-  *     @arg TIM_OCFast_Disable: TIM output compare fast disable
-  * @retval None
-  */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-  
-  /* Get the TIMx CCMR2 register value */
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4FE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
-  /* Enable or Disable the Output Compare Fast Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF1 signal on an external event
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC1CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= TIM_OCClear;
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF2 signal on an external event
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr1 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  
-  tmpccmr1 = TIMx->CCMR1;
-  /* Reset the OC2CE Bit */
-  tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR1 register */
-  TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF3 signal on an external event
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC3CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= TIM_OCClear;
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Clears or safeguards the OCREF4 signal on an external event
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCClear_Enable: TIM Output clear enable
-  *     @arg TIM_OCClear_Disable: TIM Output clear disable
-  * @retval None
-  */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
-  uint16_t tmpccmr2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-  
-  tmpccmr2 = TIMx->CCMR2;
-  /* Reset the OC4CE Bit */
-  tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
-  /* Enable or Disable the Output Compare Clear Bit */
-  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
-  /* Write to TIMx CCMR2 register */
-  TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
-  * @brief  Configures the TIMx channel 1 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC1 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
-  tmpccer |= TIM_OCPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 1N polarity.
-  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-   
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC1NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
-  tmpccer |= TIM_OCNPolarity;
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 2 polarity.
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC2 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 2N polarity.
-  * @param  TIMx: where x can be 1 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC2NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx channel 3 polarity.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC3 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configures the TIMx Channel 3N polarity.
-  * @param  TIMx: where x can be 1 to select the TIM peripheral.
-  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCNPolarity_High: Output Compare active high
-  *     @arg TIM_OCNPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
-  uint16_t tmpccer = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
-  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-    
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC3NP Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
-  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-
-/**
-  * @brief  Configures the TIMx channel 4 polarity.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCPolarity: specifies the OC4 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_OCPolarity_High: Output Compare active high
-  *     @arg TIM_OCPolarity_Low: Output Compare active low
-  * @retval None
-  */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
-  uint16_t tmpccer = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-  
-  tmpccer = TIMx->CCER;
-  /* Set or Reset the CC4P Bit */
-  tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
-  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
-  /* Write to TIMx CCER register */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Selects the OCReference Clear source.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_OCReferenceClear: specifies the OCReference Clear source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
-  *     @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.  
-  * @retval None
-  */
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
-
-  /* Set the TIM_OCReferenceClear source */
-  TIMx->SMCR &=  (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
-  TIMx->SMCR |=  TIM_OCReferenceClear;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parameter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  *     @arg TIM_Channel_4: TIM Channel 4
-  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
-  *   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
-  * @retval None
-  */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 
-  assert_param(IS_TIM_CCX(TIM_CCx));
-
-  tmp = CCER_CCE_SET << TIM_Channel;
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= (uint16_t)~ tmp;
-
-  /* Set or reset the CCxE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel xN.
-  * @param  TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_Channel: specifies the TIM Channel
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_Channel_1: TIM Channel 1
-  *     @arg TIM_Channel_2: TIM Channel 2
-  *     @arg TIM_Channel_3: TIM Channel 3
-  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
-  *   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
-  * @retval None
-  */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
-  uint16_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
-  assert_param(IS_TIM_CCXN(TIM_CCxN));
-
-  tmp = CCER_CCNE_SET << TIM_Channel;
-
-  /* Reset the CCxNE Bit */
-  TIMx->CCER &= (uint16_t) ~tmp;
-
-  /* Set or reset the CCxNE Bit */ 
-  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
-  * @brief  Selects the TIM peripheral Commutation event.
-  * @param  TIMx: where x can be  1, 15, 16 or 17 to select the TIMx peripheral
-  * @param  NewState: new state of the Commutation event.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Set the COM Bit */
-    TIMx->CR2 |= TIM_CR2_CCUS;
-  }
-  else
-  {
-    /* Reset the COM Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group4 Input Capture management functions
- *  @brief    Input Capture management functions 
- *
-@verbatim
- ===============================================================================
-               ##### Input Capture management functions #####
- ===============================================================================
-   
-          *** TIM Driver: how to use it in Input Capture Mode ***
- ===============================================================================
-    [..] To use the Timer in Input Capture mode, the following steps are mandatory:
-         (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) 
-             function.
-         (#) Configure the TIM pins by configuring the corresponding GPIO pins.
-         (#) Configure the Time base unit as described in the first part of this 
-             driver, if needed, else the Timer will run with the default configuration:
-             (++) Autoreload value = 0xFFFF.
-             (++) Prescaler value = 0x0000.
-             (++) Counter mode = Up counting.
-             (++) Clock Division = TIM_CKD_DIV1.
-         (#) Fill the TIM_ICInitStruct with the desired parameters including:
-             (++) TIM Channel: TIM_Channel.
-             (++) TIM Input Capture polarity: TIM_ICPolarity.
-             (++) TIM Input Capture selection: TIM_ICSelection.
-             (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
-             (++) TIM Input CApture filter value: TIM_ICFilter.
-         (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired 
-             channel with the corresponding configuration and to measure only 
-             frequency or duty cycle of the input signal,or, Call 
-             TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired 
-             channels with the corresponding configuration and to measure the 
-             frequency and the duty cycle of the input signal.
-         (#) Enable the NVIC or the DMA to read the measured frequency.
-         (#) Enable the corresponding interrupt (or DMA request) to read 
-             the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
-             (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
-         (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
-         (#) Use TIM_GetCapturex(TIMx); to read the captured value.
-    [..]
-        (@) All other functions can be used separately to modify, if needed,
-            a specific feature of the Timer. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));  
-  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
-  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
-
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
-  {
-    assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI3 Configuration */
-    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  {
-    assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-    /* TI4 Configuration */
-    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
-               TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Fills each TIM_ICInitStruct member with its default value.
-  * @param  TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will
-  *         be initialized.
-  * @retval None
-  */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  /* Set the default configuration */
-  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
-  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
-  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
-  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
-  TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
-  * @brief  Configures the TIM peripheral according to the specified
-  *         parameters in the TIM_ICInitStruct to measure an external PWM signal.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
-  *         that contains the configuration information for the specified TIM 
-  *         peripheral.
-  * @retval None
-  */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
-  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
-  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Select the Opposite Input Polarity */
-  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
-  {
-    icoppositepolarity = TIM_ICPolarity_Falling;
-  }
-  else
-  {
-    icoppositepolarity = TIM_ICPolarity_Rising;
-  }
-  /* Select the Opposite Input */
-  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
-  {
-    icoppositeselection = TIM_ICSelection_IndirectTI;
-  }
-  else
-  {
-    icoppositeselection = TIM_ICSelection_DirectTI;
-  }
-  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
-  {
-    /* TI1 Configuration */
-    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI2 Configuration */
-    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-  else
-  { 
-    /* TI2 Configuration */
-    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
-               TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-    /* TI1 Configuration */
-    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
-    /* Set the Input Capture Prescaler value */
-    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
-  }
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 1 value.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @retval Capture Compare 1 Register value.
-  */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  
-  /* Get the Capture 1 Register value */
-  return TIMx->CCR1;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 2 value.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @retval Capture Compare 2 Register value.
-  */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  
-  /* Get the Capture 2 Register value */
-  return TIMx->CCR2;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 3 value.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @retval Capture Compare 3 Register value.
-  */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
-  
-  /* Get the Capture 3 Register value */
-  return TIMx->CCR3;
-}
-
-/**
-  * @brief  Gets the TIMx Input Capture 4 value.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @retval Capture Compare 4 Register value.
-  */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  
-  /* Get the Capture 4 Register value */
-  return TIMx->CCR4;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 1 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  
-  /* Reset the IC1PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
-  /* Set the IC1PSC value */
-  TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 2 prescaler.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  
-  /* Reset the IC2PSC Bits */
-  TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
-  /* Set the IC2PSC value */
-  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 3 prescaler.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  
-  /* Reset the IC3PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
-  /* Set the IC3PSC value */
-  TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
-  * @brief  Sets the TIMx Input Capture 4 prescaler.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPSC_DIV1: no prescaler
-  *     @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *     @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *     @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-  
-  /* Reset the IC4PSC Bits */
-  TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
-  /* Set the IC4PSC value */
-  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- *  @brief    Interrupts, DMA and flags management functions 
- *
-@verbatim
- ===============================================================================
-          ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified TIM interrupts.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIMx peripheral.
-  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note 
-  *   - TIM6 can only generate an update interrupt.
-  *   - TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
-  *     TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.    
-  * @param  NewState: new state of the TIM interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Interrupt sources */
-    TIMx->DIER |= TIM_IT;
-  }
-  else
-  {
-    /* Disable the Interrupt sources */
-    TIMx->DIER &= (uint16_t)~TIM_IT;
-  }
-}
-
-/**
-  * @brief  Configures the TIMx event to be generate by software.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the 
-  *         TIM peripheral.
-  * @param  TIM_EventSource: specifies the event source.
-  *   This parameter can be one or more of the following values:  
-  *     @arg TIM_EventSource_Update: Timer update Event source
-  *     @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-  *     @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-  *     @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-  *     @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-  *     @arg TIM_EventSource_COM: Timer COM event source  
-  *     @arg TIM_EventSource_Trigger: Timer Trigger Event source
-  *     @arg TIM_EventSource_Break: Timer Break event source
-  * @note 
-  *   - TIM6 can only generate an update event. 
-  *   - TIM9 can only generate an update event, Capture Compare 1 event, 
-  *     Capture Compare 2 event and TIM_EventSource_Trigger.  
-  *   - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.          
-  * @retval None
-  */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); 
-  /* Set the event sources */
-  TIMx->EGR = TIM_EventSource;
-}
-
-/**
-  * @brief  Checks whether the specified TIM flag is set or not.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 can have only one update flag. 
-  *   - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or 
-  *     TIM_FLAG_Trigger. 
-  *   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.        
-  * @retval The new state of TIM_FLAG (SET or RESET).
-  */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{ 
-  ITStatus bitstatus = RESET; 
-   
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-  
-  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's pending flags.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_FLAG: specifies the flag bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_FLAG_Update: TIM update Flag
-  *     @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
-  *     @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
-  *     @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
-  *     @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
-  *     @arg TIM_FLAG_COM: TIM Commutation Flag
-  *     @arg TIM_FLAG_Trigger: TIM Trigger Flag
-  *     @arg TIM_FLAG_Break: TIM Break Flag
-  *     @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
-  *     @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
-  *     @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
-  *     @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
-  * @note
-  *   - TIM6 can have only one update flag. 
-  *   - TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or 
-  *     TIM_FLAG_Trigger. 
-  *   - TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.   
-  *   - TIM_FLAG_Break is used only with TIM1 and TIM15. 
-  *   - TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
-  * @retval None
-  */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-   
-  /* Clear the flags */
-  TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
-  * @brief  Checks whether the TIM interrupt has occurred or not.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the TIM interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_IT_Update: TIM update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 can generate only an update interrupt.
-  *   - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
-  * @retval The new state of the TIM_IT(SET or RESET).
-  */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  ITStatus bitstatus = RESET;  
-  uint16_t itstatus = 0x0, itenable = 0x0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_GET_IT(TIM_IT));
-   
-  itstatus = TIMx->SR & TIM_IT;
-  
-  itenable = TIMx->DIER & TIM_IT;
-  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the TIMx's interrupt pending bits.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_IT: specifies the pending bit to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_IT_Update: TIM1 update Interrupt source
-  *     @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
-  *     @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
-  *     @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
-  *     @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
-  *     @arg TIM_IT_COM: TIM Commutation Interrupt source
-  *     @arg TIM_IT_Trigger: TIM Trigger Interrupt source
-  *     @arg TIM_IT_Break: TIM Break Interrupt source
-  * @note
-  *   - TIM6 can generate only an update interrupt.
-  *   - TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
-  *   - TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.   
-  *   - TIM_IT_Break is used only with TIM1 and TIM15. 
-  *   - TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
-  * @retval None
-  */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_ALL_PERIPH(TIMx));
-  assert_param(IS_TIM_IT(TIM_IT));
-   
-  /* Clear the IT pending Bit */
-  TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
-  * @brief  Configures the TIMx's DMA interface.
-  * @param  TIMx: where x can be 1, 2, 3, 15, 16 or 17  to select the TIM peripheral.
-  * @param  TIM_DMABase: DMA Base address.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_DMABase_CR1, TIM_DMABase_CR2, TIM_DMABase_SMCR,
-  *          TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR,
-  *          TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
-  *          TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
-  *          TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, 
-  *          TIM_DMABase_CCR4, TIM_DMABase_DCR, TIM_DMABase_OR.
-  * @param  TIM_DMABurstLength: DMA Burst length.
-  *   This parameter can be one value between:
-  *   TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval None
-  */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
-  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
-  /* Set the DMA Base and the DMA Burst Length */
-  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
-  * @brief  Enables or disables the TIMx's DMA Requests.
-  * @param  TIMx: where x can be 1, 2, 3, 6, 15, 16 or 17 to select the TIM peripheral. 
-  * @param  TIM_DMASource: specifies the DMA Request sources.
-  *   This parameter can be any combination of the following values:
-  *     @arg TIM_DMA_Update: TIM update Interrupt source
-  *     @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *     @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *     @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *     @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *     @arg TIM_DMA_COM: TIM Commutation DMA source
-  *     @arg TIM_DMA_Trigger: TIM Trigger DMA source
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{ 
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST10_PERIPH(TIMx));
-  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA sources */
-    TIMx->DIER |= TIM_DMASource; 
-  }
-  else
-  {
-    /* Disable the DMA sources */
-    TIMx->DIER &= (uint16_t)~TIM_DMASource;
-  }
-}
-
-/**
-  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
-  * @param  TIMx: where x can be 1, 2, 3, 15, 16 or 17  to select the TIM peripheral.
-  * @param  NewState: new state of the Capture Compare DMA source
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Set the CCDS Bit */
-    TIMx->CR2 |= TIM_CR2_CCDS;
-  }
-  else
-  {
-    /* Reset the CCDS Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group6 Clocks management functions
- *  @brief    Clocks management functions
- *
-@verbatim
- ===============================================================================
-                     ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the TIMx internal Clock
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @retval None
-  */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  /* Disable slave mode to clock the prescaler directly with the internal clock */
-  TIMx->SMCR &=  (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
-  * @brief  Configures the TIMx Internal Trigger as External Clock
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @param  TIM_ITRSource: Trigger source.
-  *   This parameter can be one of the following values:
-  *   @arg  TIM_TS_ITR0: Internal Trigger 0
-  *   @arg  TIM_TS_ITR1: Internal Trigger 1
-  *   @arg  TIM_TS_ITR2: Internal Trigger 2
-  *   @arg  TIM_TS_ITR3: Internal Trigger 3
-  * @retval None
-  */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
-  /* Select the Internal Trigger */
-  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the TIMx Trigger as External Clock
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @param  TIM_TIxExternalCLKSource: Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
-  *     @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
-  *     @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
-  * @param  TIM_ICPolarity: specifies the TIx Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  ICFilter : specifies the filter value.
-  *   This parameter must be a value between 0x0 and 0xF.
-  * @retval None
-  */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
-                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
-  assert_param(IS_TIM_IC_FILTER(ICFilter));
-  
-  /* Configure the Timer Input Clock Source */
-  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
-  {
-    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  else
-  {
-    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
-  }
-  /* Select the Trigger source */
-  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
-  /* Select the External clock mode1 */
-  TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
-  * @brief  Configures the External clock Mode1
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                             uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the SMS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  /* Select the External clock mode1 */
-  tmpsmcr |= TIM_SlaveMode_External1;
-  /* Select the Trigger selection : ETRF */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  tmpsmcr |= TIM_TS_ETRF;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Configures the External clock Mode2
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
-                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  
-  /* Configure the ETR Clock source */
-  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-  /* Enable the External clock mode2 */
-  TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- *  @brief    Synchronization management functions 
- *
-@verbatim
- ===============================================================================
-               ##### Synchronization management functions #####
- ===============================================================================
-        *** TIM Driver: how to use it in synchronization Mode ***
- ===============================================================================
-    [..] Case of two/several Timers
-         (#) Configure the Master Timers using the following functions:
-             (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
-                  uint16_t TIM_TRGOSource).
-             (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
-                  uint16_t TIM_MasterSlaveMode);  
-         (#) Configure the Slave Timers using the following functions: 
-             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, 
-                  uint16_t TIM_InputTriggerSource);  
-             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-    [..] Case of Timers and external trigger(ETR pin)
-         (#) Configure the Etrenal trigger using this function:
-             (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
-                  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-         (#) Configure the Slave Timers using the following functions:
-             (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
-                  uint16_t TIM_InputTriggerSource);
-             (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_InputTriggerSource: The Input Trigger source.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_TS_ITR0: Internal Trigger 0
-  *     @arg TIM_TS_ITR1: Internal Trigger 1
-  *     @arg TIM_TS_ITR2: Internal Trigger 2
-  *     @arg TIM_TS_ITR3: Internal Trigger 3
-  *     @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *     @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *     @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *     @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
-  uint16_t tmpsmcr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
-  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the TS Bits */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
-  /* Set the Input Trigger source */
-  tmpsmcr |= TIM_InputTriggerSource;
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Selects the TIMx Trigger Output Mode.
-  * @param  TIMx: where x can be 1, 2, 3, 6, or 15 to select the TIM peripheral.
-  * @param  TIM_TRGOSource: specifies the Trigger Output source.
-  *   This paramter can be one of the following values:
-  *
-  *   For all TIMx
-  *     @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
-  *
-  *   For all TIMx except TIM6 
-  *     @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
-  *                              is to be set, as soon as a capture or compare match occurs (TRGO).
-  *     @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
-  *     @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
-  *
-  * @retval None
-  */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST9_PERIPH(TIMx));
-  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
-  /* Reset the MMS Bits */
-  TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
-  /* Select the TRGO source */
-  TIMx->CR2 |=  TIM_TRGOSource;
-}
-
-/**
-  * @brief  Selects the TIMx Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
-  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
-  *   This paramter can be one of the following values:
-  *     @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
-  *                               the counter and triggers an update of the registers.
-  *     @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high.
-  *     @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI.
-  *     @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
-  * @retval None
-  */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 
-  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-  
-  /* Reset the SMS Bits */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
-  /* Select the Slave Mode */
-  TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
-  * @brief  Sets or Resets the TIMx Master/Slave Mode.
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
-  *   This paramter can be one of the following values:
-  *     @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
-  *                                      and its slaves (through TRGO).
-  *     @arg TIM_MasterSlaveMode_Disable: No action
-  * @retval None
-  */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-  
-  /* Reset the MSM Bit */
-  TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-  
-  /* Set or Reset the MSM Bit */
-  TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
-  *     @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
-  *     @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
-  *     @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
-  *     @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *   This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
-                   uint16_t ExtTRGFilter)
-{
-  uint16_t tmpsmcr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
-  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
-  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-  
-  tmpsmcr = TIMx->SMCR;
-  /* Reset the ETR Bits */
-  tmpsmcr &= SMCR_ETR_MASK;
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- *  @brief    Specific interface management functions 
- *
-@verbatim
- ===============================================================================
-             ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the TIMx Encoder Interface.
-  * @param  TIMx: where x can be  1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
-  *     @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
-  *     @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
-  *                                on the level of the other input.
-  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
-  *   This parmeter can be one of the following values:
-  *     @arg TIM_ICPolarity_Falling: IC Falling edge.
-  *     @arg TIM_ICPolarity_Rising: IC Rising edge.
-  * @retval None
-  */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
-                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
-  uint16_t tmpsmcr = 0;
-  uint16_t tmpccmr1 = 0;
-  uint16_t tmpccer = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-  
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = TIMx->CCMR1;
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Set the encoder Mode */
-  tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-  tmpsmcr |= TIM_EncoderMode;
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
-  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
-  /* Set the TI1 and the TI2 Polarities */
-  //tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
-  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
-  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmr1;
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Enables or disables the TIMx's Hall sensor interface.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  NewState: new state of the TIMx Hall sensor interface.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Set the TI1S Bit */
-    TIMx->CR2 |= TIM_CR2_TI1S;
-  }
-  else
-  {
-    /* Reset the TI1S Bit */
-    TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- *  @brief   Specific remapping management function
- *
-@verbatim
- ===============================================================================
-               ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Configures the TIM14 Remapping input Capabilities.
-  * @param TIMx: where x can be 14 to select the TIM peripheral.
-  * @param TIM_Remap: specifies the TIM input reampping source.
-  *   This parameter can be one of the following values:
-  *   @arg TIM14_GPIO     : TIM14 Channel 1 is connected to GPIO.
-  *   @arg TIM14_RTC_CLK  : TIM14 Channel 1 is connected to RTC input clock.
-  *                       RTC input clock can be LSE, LSI or HSE/div128.
-  *   @arg TIM14_HSE_DIV32 : TIM14 Channel 1 is connected to HSE/32 clock.  
-  *   @arg TIM14_MCO : TIM14 Channel 1 is connected to MCO clock.  
-  *                  MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2.  
-  * @retval : None
-  */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
-  assert_param(IS_TIM_LIST11_PERIPH(TIMx));
-  assert_param(IS_TIM_REMAP(TIM_Remap));
-
-  /* Set the Timer remapping configuration */
-  TIMx->OR =  TIM_Remap;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0;
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
- 
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
-  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
-  *     @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 4);
-  /* Select the Input and set the filter */
-  tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
-  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
-  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
-  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);  
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 8);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
-  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);  
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICPolarity_Rising
-  *     @arg TIM_ICPolarity_Falling
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
-  *     @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
-  *     @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *   This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
-                       uint16_t TIM_ICFilter)
-{
-  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
-   /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-  tmp = (uint16_t)(TIM_ICPolarity << 12);
-  /* Select the Input and set the filter */
-  tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
-  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
-  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);  
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
-  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c

@@ -1,2014 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_usart.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Universal synchronous asynchronous receiver
-  *          transmitter (USART):
-  *           + Initialization and Configuration
-  *           + STOP Mode
-  *           + AutoBaudRate
-  *           + Data transfers
-  *           + Multi-Processor Communication
-  *           + LIN mode
-  *           + Half-duplex mode
-  *           + Smartcard mode
-  *           + IrDA mode
-  *           + RS485 mode  
-  *           + DMA transfers management
-  *           + Interrupts and flags management
-  *           
-  *  @verbatim
- ===============================================================================
-                       ##### How to use this driver #####
- ===============================================================================
-    [..]
-        (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
-            function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
-            function for USART2 and USART3.
-        (#) According to the USART mode, enable the GPIO clocks using 
-            RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
-            or and SCLK). 
-        (#) Peripheral's alternate function: 
-            (++) Connect the pin to the desired peripherals' Alternate 
-                 Function (AF) using GPIO_PinAFConfig() function.
-            (++) Configure the desired pin in alternate function by:
-                 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
-            (++) Select the type, pull-up/pull-down and output speed via 
-                 GPIO_PuPd, GPIO_OType and GPIO_Speed members.
-            (++) Call GPIO_Init() function.        
-        (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
-            flow control and Mode(Receiver/Transmitter) using the SPI_Init()
-            function.  
-        (#) For synchronous mode, enable the clock and program the polarity,
-            phase and last bit using the USART_ClockInit() function.  
-        (#) Enable the NVIC and the corresponding interrupt using the function 
-            USART_ITConfig() if you need to use interrupt mode.   
-        (#) When using the DMA mode: 
-            (++) Configure the DMA using DMA_Init() function.
-            (++) Active the needed channel Request using USART_DMACmd() function.   
-        (#) Enable the USART using the USART_Cmd() function.   
-        (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.   
-    [..]
-            Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
-            for more details.
-            
-@endverbatim
-       
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_usart.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup USART 
-  * @brief USART driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
-#define CR1_CLEAR_MASK            ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
-                                              USART_CR1_PS | USART_CR1_TE | \
-                                              USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK      ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
-                                              USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
-#define CR3_CLEAR_MASK            ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK                   ((uint32_t)0x000000FF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
-  * @{
-  */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- *  @brief   Initialization and Configuration functions 
- *
-@verbatim   
- ===============================================================================
-          ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-        This subsection provides a set of functions allowing to initialize the USART 
-        in asynchronous and in synchronous modes.
-        (+) For the asynchronous mode only these parameters can be configured: 
-          (++) Baud Rate.
-          (++) Word Length.
-          (++) Stop Bit.
-          (++) Parity: If the parity is enabled, then the MSB bit of the data written
-               in the data register is transmitted but is changed by the parity bit.
-               Depending on the frame length defined by the M bit (8-bits or 9-bits),
-               the possible USART frame formats are as listed in the following table:
-
-   +-------------------------------------------------------------+     
-   |   M bit |  PCE bit  |            USART frame                |
-   |---------------------|---------------------------------------|             
-   |    0    |    0      |    | SB | 8 bit data | STB |          |
-   |---------|-----------|---------------------------------------|  
-   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-   |---------|-----------|---------------------------------------|  
-   |    1    |    0      |    | SB | 9 bit data | STB |          |
-   |---------|-----------|---------------------------------------|  
-   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-   +-------------------------------------------------------------+            
-
-          (++) Hardware flow control.
-          (++) Receiver/transmitter modes.
-    [..] The USART_Init() function follows the USART  asynchronous configuration 
-         procedure(details for the procedure are available in reference manual.
-        (+) For the synchronous mode in addition to the asynchronous mode parameters
-            these parameters should be also configured:
-            (++) USART Clock Enabled.
-            (++) USART polarity.
-            (++) USART phase.
-            (++) USART LastBit.
-    [..] These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @retval None
-  */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-
-  if (USARTx == USART1)
-  {
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
-    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
-  }
-  else 
-  {
-    if  (USARTx == USART2)
-    {
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
-      RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
-    }
-  }
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral according to the specified
-  *   parameters in the USART_InitStruct .
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *   that contains the configuration information for the specified USART peripheral.
-  * @retval None
-  */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
-  uint32_t tmpreg = 0, apbclock = 0;
-  uint32_t integerdivider = 0;
-  uint32_t fractionaldivider = 0;
-  RCC_ClocksTypeDef RCC_ClocksStatus;
-
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
-  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
-  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
-  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
-  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
-  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-  
-  /* Disable USART */
-  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
-  
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear STOP[13:12] bits */
-  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
-  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
-  /* Set STOP[13:12] bits according to USART_StopBits value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-  
-  /* Write to USART CR2 */
-  USARTx->CR2 = tmpreg;
-
-/*---------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = USARTx->CR1;
-  /* Clear M, PCE, PS, TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
-  /* Configure the USART Word Length, Parity and mode ----------------------- */
-  /* Set the M bits according to USART_WordLength value */
-  /* Set PCE and PS bits according to USART_Parity value */
-  /* Set TE and RE bits according to USART_Mode value */
-  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
-            USART_InitStruct->USART_Mode;
-
-  /* Write to USART CR1 */
-  USARTx->CR1 = tmpreg;
-
-/*---------------------------- USART CR3 Configuration -----------------------*/  
-  tmpreg = USARTx->CR3;
-  /* Clear CTSE and RTSE bits */
-  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
-  /* Configure the USART HFC -------------------------------------------------*/
-  /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
-  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
-  /* Write to USART CR3 */
-  USARTx->CR3 = tmpreg;
-
-/*---------------------------- USART BRR Configuration -----------------------*/
-  /* Configure the USART Baud Rate -------------------------------------------*/
-  RCC_GetClocksFreq(&RCC_ClocksStatus);
-  
-  if (USARTx == USART1)
-  {
-    apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
-  }
-  else
-  {
-    apbclock = RCC_ClocksStatus.PCLK_Frequency;
-  }
-  /* Determine the integer part */
-  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
-  {
-    /* Integer part computing in case Oversampling mode is 8 Samples */
-    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    /* Integer part computing in case Oversampling mode is 16 Samples */
-    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
-  }
-  tmpreg = (integerdivider / 100) << 4;
-
-  /* Determine the fractional part */
-  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
-
-  /* Implement the fractional part in the register */
-  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
-  {
-    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
-  }
-  else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
-  {
-    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
-  }
- 
-  /* Write to USART BRR */
-  USARTx->BRR = (uint16_t)tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_InitStruct member with its default value.
-  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure
-  *   which will be initialized.
-  * @retval None
-  */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
-  /* USART_InitStruct members default value */
-  USART_InitStruct->USART_BaudRate = 9600;
-  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
-  USART_InitStruct->USART_StopBits = USART_StopBits_1;
-  USART_InitStruct->USART_Parity = USART_Parity_No ;
-  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
-}
-
-/**
-  * @brief  Initializes the USARTx peripheral Clock according to the 
-  *   specified parameters in the USART_ClockInitStruct.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *   structure that contains the configuration information for the specified 
-  *   USART peripheral.  
-  * @retval None
-  */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
-  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
-  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
-  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-/*---------------------------- USART CR2 Configuration -----------------------*/
-  tmpreg = USARTx->CR2;
-  /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
-  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
-  /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
-  /* Set CLKEN bit according to USART_Clock value */
-  /* Set CPOL bit according to USART_CPOL value */
-  /* Set CPHA bit according to USART_CPHA value */
-  /* Set LBCL bit according to USART_LastBit value */
-  tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
-                       USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
-  /* Write to USART CR2 */
-  USARTx->CR2 = tmpreg;
-}
-
-/**
-  * @brief  Fills each USART_ClockInitStruct member with its default value.
-  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
-  *   structure which will be initialized.
-  * @retval None
-  */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
-  /* USART_ClockInitStruct members default value */
-  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
-  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
-  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
-  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
-  * @brief  Enables or disables the specified USART peripheral.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the USARTx peripheral.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected USART by setting the UE bit in the CR1 register */
-    USARTx->CR1 |= USART_CR1_UE;
-  }
-  else
-  {
-    /* Disable the selected USART by clearing the UE bit in the CR1 register */
-    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's transmitter or receiver.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_Direction: specifies the USART direction.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_Mode_Tx: USART Transmitter
-  *     @arg USART_Mode_Rx: USART Receiver
-  * @param  NewState: new state of the USART transfer direction.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_MODE(USART_DirectionMode));
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the USART's transfer interface by setting the TE and/or RE bits 
-       in the USART CR1 register */
-    USARTx->CR1 |= USART_DirectionMode;
-  }
-  else
-  {
-    /* Disable the USART's transfer interface by clearing the TE and/or RE bits
-       in the USART CR3 register */
-    USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's 8x oversampling mode.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param NewState: new state of the USART 8x oversampling mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *   This function has to be called before calling USART_Init()
-  *   function in order to have correct baudrate Divider value.
-  * @retval None
-  */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
-    USARTx->CR1 |= USART_CR1_OVER8;
-  }
-  else
-  {
-    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
-    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
-  }
-}  
-
-/**
-  * @brief  Enables or disables the USART's one bit sampling method.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the USART one bit sampling method.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_ONEBIT;
-  }
-  else
-  {
-    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's most significant bit first 
-  *         transmitted/received following the start bit.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the USART most significant bit first
-  *         transmitted/received following the start bit.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the most significant bit first transmitted/received following the 
-       start bit by setting the MSBFIRST bit in the CR2 register */
-    USARTx->CR2 |= USART_CR2_MSBFIRST;
-  }
-  else
-  {
-    /* Disable the most significant bit first transmitted/received following the 
-       start bit by clearing the MSBFIRST bit in the CR2 register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
-  }
-}
-
-/**
-  * @brief  Enables or disables the binary data inversion.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param NewState: new defined levels for the USART data.
-  *   This parameter can be: ENABLE or DISABLE.
-  *   - ENABLE: Logical data from the data register are send/received in negative
-  *             logic. (1=L, 0=H). The parity bit is also inverted.
-  *   - DISABLE: Logical data from the data register are send/received in positive
-  *              logic. (1=H, 0=L) 
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the binary data inversion feature by setting the DATAINV bit in 
-       the CR2 register */
-    USARTx->CR2 |= USART_CR2_DATAINV;
-  }
-  else
-  {
-    /* Disable the binary data inversion feature by clearing the DATAINV bit in 
-       the CR2 register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
-  }
-}
-
-/**
-  * @brief  Enables or disables the Pin(s) active level inversion.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_InvPin: specifies the USART pin(s) to invert.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_InvPin_Tx: USART Tx pin active level inversion.
-  *     @arg USART_InvPin_Rx: USART Rx pin active level inversion.
-  * @param NewState: new active level status for the USART pin(s).
-  *   This parameter can be: ENABLE or DISABLE.
-  *   - ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
-  *   - DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the active level inversion for selected pins by setting the TXINV 
-       and/or RXINV bits in the USART CR2 register */
-    USARTx->CR2 |= USART_InvPin;
-  }
-  else
-  {
-    /* Disable the active level inversion for selected requests by clearing the 
-       TXINV and/or RXINV bits in the USART CR2 register */
-    USARTx->CR2 &= (uint32_t)~USART_InvPin;
-  }
-}
-
-/**
-  * @brief  Enables or disables the swap Tx/Rx pins.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param NewState: new state of the USARTx TX/RX pins pinout.
-  *   This parameter can be: ENABLE or DISABLE.
-  *   - ENABLE: The TX and RX pins functions are swapped.
-  *   - DISABLE: TX/RX pins are used as defined in standard pinout
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
-    USARTx->CR2 |= USART_CR2_SWAP;
-  }
-  else
-  {
-    /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
-  }
-}
-
-/**
-  * @brief  Enables or disables the receiver Time Out feature.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param NewState: new state of the USARTx receiver Time Out.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the receiver time out feature by setting the RTOEN bit in the CR2 
-       register */
-    USARTx->CR2 |= USART_CR2_RTOEN;
-  }
-  else
-  {
-    /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2 
-       register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
-  }
-}
-
-/**
-  * @brief  Sets the receiver Time Out value.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_ReceiverTimeOut: specifies the Receiver Time Out value.
-  * @retval None
-  */
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
-
-  /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
-     register  */
-  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
-  /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
-     register  */
-  USARTx->RTOR |= USART_ReceiverTimeOut;
-}
-
-/**
-  * @brief  Sets the system clock prescaler.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_Prescaler: specifies the prescaler clock.
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.    
-  * @retval None
-  */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{ 
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  
-  /* Clear the USART prescaler */
-  USARTx->GTPR &= USART_GTPR_GT;
-  /* Set the USART prescaler */
-  USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Group2 STOP Mode functions
- *  @brief   STOP Mode functions
- *
-@verbatim
- ===============================================================================
-                        ##### STOP Mode functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage 
-         WakeUp from STOP mode.
-
-    [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
-         or LSI.
-         
-    [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
-         function.
-         
-    [..] After configuring the source of WakeUp and before entering in Stop Mode 
-         USART_STOPModeCmd() function should be called to allow USART WakeUp.
-                           
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified USART peripheral in STOP Mode.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  NewState: new state of the USARTx peripheral state in stop mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @note
-  *   This function has to be called when USART clock is set to HSI or LSE. 
-  * @retval None
-  */
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
-       register */
-    USARTx->CR1 |= USART_CR1_UESM;
-  }
-  else
-  {
-    /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
-       register */
-    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
-  }
-}
-
-/**
-  * @brief  Selects the USART WakeUp method form stop mode.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_WakeUp: specifies the selected USART wakeup method.
-  *   This parameter can be one of the following values:
-  *     @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
-  *     @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
-  *     @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.   
-  * @retval None
-  */
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
-
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
-  USARTx->CR3 |= USART_WakeUpSource;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Group3 AutoBaudRate functions
- *  @brief   AutoBaudRate functions 
- *
-@verbatim
- ===============================================================================
-                       ##### AutoBaudRate functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage 
-         the AutoBaudRate detections.
-         
-    [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
-         The character patterns used to calculate baudrate must be chosen by calling 
-         USART_AutoBaudRateConfig() function. These function take as parameter :
-        (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
-        (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern. 
-                          
-    [..] At any later time, another request for AutoBaudRate detection can be performed
-         using USART_AutoBaudRateNewRequest() function.
-         
-    [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
-         that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
-         indicate that this procedure is completed without success. USART_GetFlagStatus () 
-         function should be used to monitor the status of these flags.  
-             
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the Auto Baud Rate.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param NewState: new state of the USARTx auto baud rate.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the auto baud rate feature by setting the ABREN bit in the CR2 
-       register */
-    USARTx->CR2 |= USART_CR2_ABREN;
-  }
-  else
-  {
-    /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2 
-       register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
-  }
-}
-
-/**
-  * @brief  Selects the USART auto baud rate method.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_AutoBaudRate: specifies the selected USART auto baud rate method.
-  *   This parameter can be one of the following values:
-  *     @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
-  *     @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
-  * @note
-  *   This function has to be called before calling USART_Cmd() function.  
-  * @retval None
-  */
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
-
-  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
-  USARTx->CR2 |= USART_AutoBaudRate;
-}
-
-/**
-  * @brief  Requests a new AutoBaudRate detection.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @retval None
-  */
-void USART_AutoBaudRateNewRequest(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-
-  USARTx->ISR &= (uint32_t)~((uint32_t)USART_FLAG_ABRF);
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Group4 Data transfers functions
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                    ##### Data transfers functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage 
-         the USART data transfers.
-    [..] During an USART reception, data shifts in least significant bit first 
-         through the RX pin. When a transmission is taking place, a write instruction to 
-         the USART_TDR register stores the data in the shift register.
-    [..] The read access of the USART_RDR register can be done using 
-         the USART_ReceiveData() function and returns the RDR value.
-         Whereas a write access to the USART_TDR can be done using USART_SendData()
-         function and stores the written data into TDR.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits single data through the USARTx peripheral.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  Data: the data to transmit.
-  * @retval None
-  */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DATA(Data)); 
-    
-  /* Transmit Data */
-  USARTx->TDR = (Data & (uint16_t)0x01FF);
-}
-
-/**
-  * @brief  Returns the most recent received data by the USARTx peripheral.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @retval The received data.
-  */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Receive Data */
-  return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group5 MultiProcessor Communication functions
- *  @brief   Multi-Processor Communication functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Multi-Processor Communication functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART
-         multiprocessor communication.
-    [..] For instance one of the USARTs can be the master, its TX output is
-         connected to the RX input of the other USART. The others are slaves,
-         their respective TX outputs are logically ANDed together and connected 
-         to the RX input of the master. USART multiprocessor communication is 
-         possible through the following procedure:
-         (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, 
-             Mode transmitter or Mode receiver and hardware flow control values 
-             using the USART_Init() function.
-         (#) Configures the USART address using the USART_SetAddress() function.
-         (#) Configures the wake up methode (USART_WakeUp_IdleLine or 
-             USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only 
-             for the slaves.
-         (#) Enable the USART using the USART_Cmd() function.
-         (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() 
-             function.
-    [..] The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the address of the USART node.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_Address: Indicates the address of the USART node.
-  * @retval None
-  */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  
-  /* Clear the USART address */
-  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
-  /* Set the USART address node */
-  USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
-}
-
-/**
-  * @brief  Enables or disables the USART's mute mode.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the USART mute mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the USART mute mode by setting the MME bit in the CR1 register */
-    USARTx->CR1 |= USART_CR1_MME;
-  }
-  else
-  {
-    /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
-    USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
-  }
-}
-
-/**
-  * @brief  Selects the USART WakeUp method from mute mode.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_WakeUp: specifies the USART wakeup method.
-  *   This parameter can be one of the following values:
-  *     @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
-  *     @arg USART_WakeUp_AddressMark: WakeUp by an address mark
-  * @retval None
-  */
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
-
-  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
-  USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
-  * @brief  Configure the the USART Address detection length.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_AddressLength: specifies the USART address length detection.
-  *   This parameter can be one of the following values:
-  *     @arg USART_AddressLength_4b: 4-bit address length detection 
-  *     @arg USART_AddressLength_7b: 7-bit address length detection 
-  * @retval None
-  */
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
-
-  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
-  USARTx->CR2 |= USART_AddressLength;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group6 LIN mode functions
- *  @brief   LIN mode functions 
- *
-@verbatim   
- ===============================================================================
-                       ##### LIN mode functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART 
-         LIN Mode communication.
-    [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance 
-         with the LIN standard.
-    [..] Only this LIN Feature is supported by the USART IP:
-         (+) LIN Master Synchronous Break send capability and LIN slave break 
-             detection capability :  13-bit break generation and 10/11 bit break 
-             detection.
-    [..] USART LIN Master transmitter communication is possible through the 
-         following procedure:
-         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
-             Mode transmitter or Mode receiver and hardware flow control values 
-             using the USART_Init() function.
-         (#) Enable the LIN mode using the USART_LINCmd() function.
-         (#) Enable the USART using the USART_Cmd() function.
-         (#) Send the break character using USART_SendBreak() function.
-    [..] USART LIN Master receiver communication is possible through the 
-         following procedure:
-         (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
-             Mode transmitter or Mode receiver and hardware flow control values 
-             using the USART_Init() function.
-         (#) Configures the break detection length 
-             using the USART_LINBreakDetectLengthConfig() function.
-         (#) Enable the LIN mode using the USART_LINCmd() function.
-         -@- In LIN mode, the following bits must be kept cleared:
-             (+@) CLKEN in the USART_CR2 register.
-             (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
-         (#) Enable the USART using the USART_Cmd() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the USART LIN Break detection length.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
-  *   This parameter can be one of the following values:
-  *     @arg USART_LINBreakDetectLength_10b: 10-bit break detection
-  *     @arg USART_LINBreakDetectLength_11b: 11-bit break detection
-  * @retval None
-  */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
-  USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
-  USARTx->CR2 |= USART_LINBreakDetectLength;  
-}
-
-/**
-  * @brief  Enables or disables the USART's LIN mode.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  NewState: new state of the USART LIN mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-    USARTx->CR2 |= USART_CR2_LINEN;
-  }
-  else
-  {
-    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
-    USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group7 Halfduplex mode function
- *  @brief   Half-duplex mode function 
- *
-@verbatim   
- ===============================================================================
-                   ##### Half-duplex mode function #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART
-         Half-duplex communication.
-    [..] The USART can be configured to follow a single-wire half-duplex protocol 
-         where the TX and RX lines are internally connected.
-    [..] USART Half duplex communication is possible through the following procedure:
-         (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
-             or Mode receiver and hardware flow control values using the USART_Init()
-            function.
-         (#) Configures the USART address using the USART_SetAddress() function.
-         (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
-         (#) Enable the USART using the USART_Cmd() function.
-         -@- The RX pin is no longer used.
-         -@- In Half-duplex mode the following bits must be kept cleared:
-             (+@) LINEN and CLKEN bits in the USART_CR2 register.
-             (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the USART's Half Duplex communication.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the USART Communication.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  if (NewState != DISABLE)
-  {
-    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_HDSEL;
-  }
-  else
-  {
-    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
-  }
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup USART_Group8 Smartcard mode functions
- *  @brief   Smartcard mode functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Smartcard mode functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART
-         Smartcard communication.
-    [..] The Smartcard interface is designed to support asynchronous protocol 
-         Smartcards as defined in the ISO 7816-3 standard. The USART can provide 
-         a clock to the smartcard through the SCLK output. In smartcard mode, 
-         SCLK is not associated to the communication but is simply derived from 
-         the internal peripheral input clock through a 5-bit prescaler.
-    [..] Smartcard communication is possible through the following procedure:
-         (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler() 
-             function.
-         (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() 
-             function.
-         (#) Program the USART clock using the USART_ClockInit() function as following:
-             (++) USART Clock enabled.
-             (++) USART CPOL Low.
-             (++) USART CPHA on first edge.
-             (++) USART Last Bit Clock Enabled.
-         (#) Program the Smartcard interface using the USART_Init() function as 
-             following:
-             (++) Word Length = 9 Bits.
-             (++) 1.5 Stop Bit.
-             (++) Even parity.
-             (++) BaudRate = 12096 baud.
-             (++) Hardware flow control disabled (RTS and CTS signals).
-             (++) Tx and Rx enabled
-         (#) Optionally you can enable the parity error interrupt using 
-             the USART_ITConfig() function.
-         (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
-         (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
-         (#) Enable the USART using the USART_Cmd() function.
-    [..] 
-  Please refer to the ISO 7816-3 specification for more details.
-    [..] 
-         (@) It is also possible to choose 0.5 stop bit for receiving but it is 
-             recommended to use 1.5 stop bits for both transmitting and receiving 
-             to avoid switching between the two configurations.
-         (@) In smartcard mode, the following bits must be kept cleared:
-             (+@) LINEN bit in the USART_CR2 register.
-             (+@) HDSEL and IREN bits in the USART_CR3 register.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets the specified USART guard time.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_GuardTime: specifies the guard time.
-  * @retval None
-  */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-
-  /* Clear the USART Guard time */
-  USARTx->GTPR &= USART_GTPR_PSC;
-  /* Set the USART guard time */
-  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
-  * @brief  Enables or disables the USART's Smart Card mode.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  NewState: new state of the Smart Card mode.
-  *   This parameter can be: ENABLE or DISABLE.      
-  * @retval None
-  */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_SCEN;
-  }
-  else
-  {
-    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
-  }
-}
-
-/**
-  * @brief  Enables or disables NACK transmission.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  NewState: new state of the NACK transmission.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx)); 
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_NACK;
-  }
-  else
-  {
-    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
-  }
-}
-
-/**
-  * @brief  Sets the Smart Card number of retries in transmit and receive.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_AutoCount: specifies the Smart Card auto retry count.
-  * @retval None
-  */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
-  /* Clear the USART auto retry count */
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
-  /* Set the USART auto retry count*/
-  USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
-}
-
-/**
-  * @brief  Sets the Smart Card Block length.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_BlockLength: specifies the Smart Card block length.
-  * @retval None
-  */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
-{    
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-
-  /* Clear the Smart card block length */
-  USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
-  /* Set the Smart Card block length */
-  USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group9 IrDA mode functions
- *  @brief   IrDA mode functions 
- *
-@verbatim   
- ===============================================================================
-                        ##### IrDA mode functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART
-         IrDA communication.
-    [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, 
-         any data on the IrDA receive line will be ignored by the IrDA decoder 
-         and if the Receiver is busy, data on the TX from the USART to IrDA will 
-         not be encoded by IrDA. While receiving data, transmission should be 
-         avoided as the data to be transmitted could be corrupted.
-    [..] IrDA communication is possible through the following procedure:
-         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
-             Transmitter/Receiver modes and hardware flow control values using 
-             the USART_Init() function.
-         (#) Configures the IrDA pulse width by configuring the prescaler using  
-             the USART_SetPrescaler() function.
-         (#) Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal 
-             mode using the USART_IrDAConfig() function.
-         (#) Enable the IrDA using the USART_IrDACmd() function.
-         (#) Enable the USART using the USART_Cmd() function.         
-    [..]
-    (@) A pulse of width less than two and greater than one PSC period(s) may or 
-        may not be rejected.
-    (@) The receiver set up time should be managed by software. The IrDA physical 
-        layer specification specifies a minimum of 10 ms delay between 
-        transmission and reception (IrDA is a half duplex protocol).
-    (@) In IrDA mode, the following bits must be kept cleared:
-        (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
-        (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the USART's IrDA interface.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  USART_IrDAMode: specifies the IrDA mode.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IrDAMode_LowPower
-  *     @arg USART_IrDAMode_Normal
-  * @retval None
-  */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
-  USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
-  * @brief  Enables or disables the USART's IrDA interface.
-  * @param  USARTx: where x can be 1 to select the USART peripheral.
-  * @param  NewState: new state of the IrDA mode.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_1_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_IREN;
-  }
-  else
-  {
-    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
-  }
-}
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group10 RS485 mode function
- *  @brief  RS485 mode function 
- *
-@verbatim  
- ===============================================================================
-                        ##### RS485 mode functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to manage the USART
-         RS485 flow control.
-    [..] RS485 flow control (Driver enable feature) handling is possible through
-         the following procedure:
-         (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, 
-             Transmitter/Receiver modes and hardware flow control values using 
-             the USART_Init() function.
-         (#) Enable the Driver Enable using the USART_DECmd() function.
-         (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
-             function.
-         (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime() 
-             function and deassertion time using the USART_SetDEDeassertionTime()
-             function.    
-         (#) Enable the USART using the USART_Cmd() function.
-      -@-  
-       (+@) The assertion and dessertion times are expressed in sample time units (1/8 or 
-            1/16 bit time, depending on the oversampling rate).
-       
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the USART's DE functionality.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  NewState: new state of the driver enable mode.
-  *   This parameter can be: ENABLE or DISABLE.      
-  * @retval None
-  */
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  if (NewState != DISABLE)
-  {
-    /* Enable the DE functionality by setting the DEM bit in the CR3 register */
-    USARTx->CR3 |= USART_CR3_DEM;
-  }
-  else
-  {
-    /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
-    USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
-  }
-}
-
-/**
-  * @brief  Configures the USART's DE polarity
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_DEPolarity: specifies the DE polarity.
-  *   This parameter can be one of the following values:
-  *     @arg USART_DEPolarity_Low
-  *     @arg USART_DEPolarity_High
-  * @retval None
-  */
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
-
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
-  USARTx->CR3 |= USART_DEPolarity;
-}
-
-/**
-  * @brief  Sets the specified RS485 DE assertion time
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  *  @param  USART_AssertionTime: specifies the time between the activation of the DE
-  *  signal and the beginning of the start bit
-  * @retval None
-  */
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime)); 
-
-  /* Clear the DE assertion time */
-  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
-  /* Set the new value for the DE assertion time */
-  USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
-}
-
-/**
-  * @brief  Sets the specified RS485 DE deassertion time
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  *  @param  USART_DeassertionTime: specifies the time between the middle of the last 
-  *   stop bit in a transmitted message and the de-activation of the DE signal
-  * @retval None
-  */
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime)); 
-
-  /* Clear the DE deassertion time */
-  USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
-  /* Set the new value for the DE deassertion time */
-  USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Group11 DMA transfers management functions
- *  @brief   DMA transfers management functions
- *
-@verbatim   
- ===============================================================================
-               ##### DMA transfers management functions #####
- ===============================================================================
-    [..] This section provides two functions that can be used only in DMA mode.
-    [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel 
-         requests:
-         (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
-         (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
-    [..] In this Mode it is advised to use the following function:
-         (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, 
-             FunctionalState NewState).
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the USART's DMA interface.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_DMAReq: specifies the DMA request.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_DMAReq_Tx: USART DMA transmit request
-  *     @arg USART_DMAReq_Rx: USART DMA receive request
-  * @param  NewState: new state of the DMA Request sources.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 |= USART_DMAReq;
-  }
-  else
-  {
-    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
-       DMAR bits in the USART CR3 register */
-    USARTx->CR3 &= (uint32_t)~USART_DMAReq;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's DMA interface when reception error occurs.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_DMAOnError: specifies the DMA status in case of reception error.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA  
-  *          reception error is asserted.
-  *     @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA 
-  *          reception error is asserted.
-  * @retval None
-  */
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_DMAONERROR(USART_DMAOnError)); 
-  
-  /* Clear the DMA Reception error detection bit */
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
-  /* Set the new value for the DMA Reception error detection bit */
-  USARTx->CR3 |= USART_DMAOnError;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup USART_Group12 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions 
- *
-@verbatim   
- ===============================================================================
-            ##### Interrupts and flags management functions #####
- ===============================================================================
-    [..] This subsection provides a set of functions allowing to configure the 
-         USART Interrupts sources, Requests and check or clear the flags or pending bits status. 
-         The user should identify which mode will be used in his application to 
-         manage the communication: Polling mode, Interrupt mode.
-
- *** Polling Mode ***
- ====================
-    [..] In Polling Mode, the SPI communication can be managed by these flags:
-         (#) USART_FLAG_REACK: to indicate the status of the Receive Enable 
-             acknowledge flag
-         (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable 
-             acknowledge flag.
-         (#) USART_FLAG_WUF: to indicate the status of the Wake up flag.
-         (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
-         (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
-         (#) USART_FLAG_CMF: to indicate the status of the Character match flag.
-         (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
-         (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
-         (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
-         (#) USART_FLAG_EOBF: to indicate the status of the End of block flag.
-         (#) USART_FLAG_RTOF: to indicate the status of the Receive time out flag.
-         (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input 
-             bit status.
-         (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
-         (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
-         (#) USART_FLAG_TC: to indicate the status of the transmit operation.
-         (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
-         (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
-         (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
-         (#) USART_FLAG_NE: to indicate if a noise error occur.
-         (#) USART_FLAG_FE: to indicate if a frame error occur.
-         (#) USART_FLAG_PE: to indicate if a parity error occur.
-         (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
-    [..] In this Mode it is advised to use the following functions:
-         (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
-         (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
-
- *** Interrupt Mode ***
- ======================
-    [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt 
-         sources and 10 pending bits:
-         (+) Pending Bits:
-             (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
-             (##) USART_IT_CM: to indicate the status of Character match interrupt.
-             (##) USART_IT_EOB: to indicate the status of End of block interrupt.
-             (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
-             (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
-             (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
-             (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
-             (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
-             (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
-             (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
-             (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
-             (##) USART_IT_PE: to indicate the status of Parity Error interrupt.  
-
-         (+) Interrupt Source:
-             (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
-             (##) USART_IT_CM: specifies the interrupt source for Character match 
-                  interrupt.
-             (##) USART_IT_EOB: specifies the interrupt source for End of block
-                  interrupt.
-             (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
-                  interrupt.
-             (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
-             (##) USART_IT_LBD: specifies the interrupt source for LIN Break 
-                  detection interrupt.
-             (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data 
-                  Register empty interrupt.
-             (##) USART_IT_TC: specifies the interrupt source for Transmission 
-                  complete interrupt.
-             (##) USART_IT_RXNE: specifies the interrupt source for Receive Data 
-                  register not empty interrupt.
-             (##) USART_IT_IDLE: specifies the interrupt source for Idle line 
-                  detection interrupt.
-             (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
-             (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
-                  (Frame error, noise error, overrun error)
-             -@@- Some parameters are coded in order to use them as interrupt 
-                 source or as pending bits.
-    [..] In this Mode it is advised to use the following functions:
-         (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
-         (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
-         (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables or disables the specified USART interrupts.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_WU:  Wake up interrupt.
-  *     @arg USART_IT_CM:  Character match interrupt.
-  *     @arg USART_IT_EOB:  End of block interrupt.
-  *     @arg USART_IT_RTO:  Receive time out interrupt.
-  *     @arg USART_IT_CTS:  CTS change interrupt.
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt.
-  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
-  *     @arg USART_IT_TC:  Transmission complete interrupt.
-  *     @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
-  *     @arg USART_IT_IDLE:  Idle line detection interrupt.
-  *     @arg USART_IT_PE:  Parity Error interrupt.
-  *     @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @param  NewState: new state of the specified USARTx interrupts.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
-{
-  uint32_t usartreg = 0, itpos = 0, itmask = 0;
-  uint32_t usartxbase = 0;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CONFIG_IT(USART_IT));
-  assert_param(IS_FUNCTIONAL_STATE(NewState));
-  
-  usartxbase = (uint32_t)USARTx;
-  
-  /* Get the USART register index */
-  usartreg = (((uint16_t)USART_IT) >> 0x08);
-  
-  /* Get the interrupt position */
-  itpos = USART_IT & IT_MASK;
-  itmask = (((uint32_t)0x01) << itpos);
-  
-  if (usartreg == 0x02) /* The IT is in CR2 register */
-  {
-    usartxbase += 0x04;
-  }
-  else if (usartreg == 0x03) /* The IT is in CR3 register */
-  {
-    usartxbase += 0x08;
-  }
-  else /* The IT is in CR1 register */
-  {
-  }
-  if (NewState != DISABLE)
-  {
-    *(__IO uint32_t*)usartxbase  |= itmask;
-  }
-  else
-  {
-    *(__IO uint32_t*)usartxbase &= ~itmask;
-  }
-}
-
-/**
-  * @brief  Enables the specified USART's Request.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_Request: specifies the USART request.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_Request_TXFRQ: Transmit data flush ReQuest
-  *     @arg USART_Request_RXFRQ: Receive data flush ReQuest
-  *     @arg USART_Request_MMRQ: Mute Mode ReQuest
-  *     @arg USART_Request_SBKRQ: Send Break ReQuest
-  *     @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
-  * @param  NewState: new state of the DMA interface when reception error occurs.
-  *   This parameter can be: ENABLE or DISABLE.  
-  * @retval None
-  */
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_REQUEST(USART_Request));
-  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
-
-  if (NewState != DISABLE)
-  {
-    /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
-       register.*/
-      USARTx->RQR |= USART_Request;
-  }
-  else
-  {
-    /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
-       register.*/
-    USARTx->RQR &= (uint32_t)~USART_Request;
-  }
-}
-
-/**
-  * @brief  Enables or disables the USART's Overrun detection.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_OVRDetection: specifies the OVR detection status in case of OVR error.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_OVRDetection_Enable: OVR error detection enabled when the USART OVR error 
-  *          is asserted.
-  *     @arg USART_OVRDetection_Disable: OVR error detection disabled when the USART OVR error 
-  *          is asserted.
-  * @retval None
-  */
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
-  
-  /* Clear the OVR detection bit */
-  USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
-  /* Set the new value for the OVR detection bit */
-  USARTx->CR3 |= USART_OVRDetection;
-}
-
-/**
-  * @brief  Checks whether the specified USART flag is set or not.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_FLAG: specifies the flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_FLAG_REACK:  Receive Enable acknowledge flag.
-  *     @arg USART_FLAG_TEACK:  Transmit Enable acknowledge flag.
-  *     @arg USART_FLAG_WUF:  Wake up flag.
-  *     @arg USART_FLAG_RWU:  Receive Wake up flag.
-  *     @arg USART_FLAG_SBK:  Send Break flag.
-  *     @arg USART_FLAG_CMF:  Character match flag.
-  *     @arg USART_FLAG_BUSY:  Busy flag.
-  *     @arg USART_FLAG_ABRF:  Auto baud rate flag.
-  *     @arg USART_FLAG_ABRE:  Auto baud rate error flag.
-  *     @arg USART_FLAG_EOBF:  End of block flag.
-  *     @arg USART_FLAG_RTOF:  Receive time out flag.
-  *     @arg USART_FLAG_nCTSS:  Inverted nCTS input bit status.
-  *     @arg USART_FLAG_CTS:  CTS Change flag.
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
-  *     @arg USART_FLAG_TXE:  Transmit data register empty flag.
-  *     @arg USART_FLAG_TC:  Transmission Complete flag.
-  *     @arg USART_FLAG_RXNE:  Receive data register not empty flag.
-  *     @arg USART_FLAG_IDLE:  Idle Line detection flag.
-  *     @arg USART_FLAG_ORE:  OverRun Error flag.
-  *     @arg USART_FLAG_NE:  Noise Error flag.
-  *     @arg USART_FLAG_FE:  Framing Error flag.
-  *     @arg USART_FLAG_PE:  Parity Error flag.
-  * @retval The new state of USART_FLAG (SET or RESET).
-  */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
-  FlagStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_FLAG(USART_FLAG));
-  
-  if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears the USARTx's pending flags.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_FLAG: specifies the flag to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg USART_FLAG_WUF:  Wake up flag.
-  *     @arg USART_FLAG_CMF:  Character match flag.
-  *     @arg USART_FLAG_EOBF:  End of block flag.
-  *     @arg USART_FLAG_RTOF:  Receive time out flag.
-  *     @arg USART_FLAG_CTS:  CTS Change flag.
-  *     @arg USART_FLAG_LBD:  LIN Break detection flag.
-  *     @arg USART_FLAG_TC:  Transmission Complete flag.
-  *     @arg USART_FLAG_IDLE:  IDLE line detected flag.
-  *     @arg USART_FLAG_ORE:  OverRun Error flag.
-  *     @arg USART_FLAG_NE: Noise Error flag.
-  *     @arg USART_FLAG_FE: Framing Error flag.
-  *     @arg USART_FLAG_PE:   Parity Errorflag.
-  *   
-  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
-  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
-  *           USART_RQR (USART_RequestCmd()).
-  * @note     TC flag can be also cleared by software sequence: a read operation
-  *           to USART_SR register (USART_GetFlagStatus()) followed by a write 
-  *           operation to USART_TDR register (USART_SendData()).
-  * @note     TXE flag is cleared by a write to the USART_TDR register (USART_SendData())
-  *           or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()).
-  * @note     SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
-  *           (USART_RequestCmd()).
-  * @retval None
-  */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-     
-  USARTx->ICR = USART_FLAG;
-}
-
-/**
-  * @brief  Checks whether the specified USART interrupt has occurred or not.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_IT: specifies the USART interrupt source to check.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_WU:  Wake up interrupt.
-  *     @arg USART_IT_CM:  Character match interrupt.
-  *     @arg USART_IT_EOB:  End of block interrupt.
-  *     @arg USART_IT_RTO:  Receive time out interrupt.
-  *     @arg USART_IT_CTS:  CTS change interrupt.
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt.
-  *     @arg USART_IT_TXE:  Tansmit Data Register empty interrupt.
-  *     @arg USART_IT_TC:  Transmission complete interrupt.
-  *     @arg USART_IT_RXNE:  Receive Data register not empty interrupt.
-  *     @arg USART_IT_IDLE:  Idle line detection interrupt.
-  *     @arg USART_IT_ORE:  OverRun Error interrupt.
-  *     @arg USART_IT_NE:  Noise Error interrupt.
-  *     @arg USART_IT_FE:  Framing Error interrupt.
-  *     @arg USART_IT_PE:  Parity Error interrupt.
-  * @retval The new state of USART_IT (SET or RESET).
-  */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
-  uint32_t bitpos = 0, itmask = 0, usartreg = 0;
-  ITStatus bitstatus = RESET;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_GET_IT(USART_IT)); 
-  
-  /* Get the USART register index */
-  usartreg = (((uint16_t)USART_IT) >> 0x08);
-  /* Get the interrupt position */
-  itmask = USART_IT & IT_MASK;
-  itmask = (uint32_t)0x01 << itmask;
-  
-  if (usartreg == 0x01) /* The IT  is in CR1 register */
-  {
-    itmask &= USARTx->CR1;
-  }
-  else if (usartreg == 0x02) /* The IT  is in CR2 register */
-  {
-    itmask &= USARTx->CR2;
-  }
-  else /* The IT  is in CR3 register */
-  {
-    itmask &= USARTx->CR3;
-  }
-  
-  bitpos = USART_IT >> 0x10;
-  bitpos = (uint32_t)0x01 << bitpos;
-  bitpos &= USARTx->ISR;
-  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  
-  return bitstatus;  
-}
-
-/**
-  * @brief  Clears the USARTx's interrupt pending bits.
-  * @param  USARTx: where x can be 1 or 2 to select the USART peripheral.
-  * @param  USART_IT: specifies the interrupt pending bit to clear.
-  *   This parameter can be one of the following values:
-  *     @arg USART_IT_WU:  Wake up interrupt.
-  *     @arg USART_IT_CM:  Character match interrupt.
-  *     @arg USART_IT_EOB:  End of block interrupt.
-  *     @arg USART_IT_RTO:  Receive time out interrupt.
-  *     @arg USART_IT_CTS:  CTS change interrupt.
-  *     @arg USART_IT_LBD:  LIN Break detection interrupt.
-  *     @arg USART_IT_TC:  Transmission complete interrupt.
-  *     @arg USART_IT_IDLE:  IDLE line detected interrupt.
-  *     @arg USART_IT_ORE:  OverRun Error interrupt.
-  *     @arg USART_IT_NE:  Noise Error interrupt.
-  *     @arg USART_IT_FE:  Framing Error interrupt.
-  *     @arg USART_IT_PE:  Parity Error interrupt.
-  *
-  * @note     RXNE pending bit is cleared by a read to the USART_RDR register 
-  *           (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register 
-  *           USART_RQR (USART_RequestCmd()).
-  * @note     TC pending bit can be also cleared by software sequence: a read 
-  *           operation to USART_SR register (USART_GetITStatus()) followed by  
-  *           a write operation to USART_TDR register (USART_SendData()).
-  * @note     TXE pending bit is cleared by a write to the USART_TDR register 
-  *           (USART_SendData()) or by writing 1 to the TXFRQ in the register 
-  *           USART_RQR (USART_RequestCmd()).
-  * @retval None
-  */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
-  uint32_t bitpos = 0, itmask = 0;
-  /* Check the parameters */
-  assert_param(IS_USART_ALL_PERIPH(USARTx));
-  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
-  
-  bitpos = USART_IT >> 0x10;
-  itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
-  USARTx->ICR = (uint32_t)itmask;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c

@@ -1,303 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_wwdg.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Window watchdog (WWDG) peripheral:
-  *           + Prescaler, Refresh window and Counter configuration
-  *           + WWDG activation
-  *           + Interrupts and flags management
-  *             
-  *  @verbatim
-  *    
-  ============================================================================== 
-                           ##### WWDG features ##### 
-  ============================================================================== 
-    [..] Once enabled the WWDG generates a system reset on expiry of a programmed
-        time period, unless the program refreshes the counter (downcounter) 
-        before to reach 0x3F value (i.e. a reset is generated when the counter
-        value rolls over from 0x40 to 0x3F). 
-    [..] An MCU reset is also generated if the counter value is refreshed
-         before the counter has reached the refresh window value. This 
-         implies that the counter must be refreshed in a limited window.
-
-    [..] Once enabled the WWDG cannot be disabled except by a system reset.
-
-    [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
-         reset occurs.
-
-    [..] The WWDG counter input clock is derived from the APB clock divided 
-         by a programmable prescaler.
-
-    [..] WWDG counter clock = PCLK1 / Prescaler.
-    [..] WWDG timeout = (WWDG counter clock) * (counter value).
-
-    [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.
-
-                       ##### How to use this driver ##### 
-  ==============================================================================
-    [..]
-        (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 
-            function.
-              
-        (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
-                             
-        (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
-              
-        (#) Set the WWDG counter value and start it using WWDG_Enable() function.
-            When the WWDG is enabled the counter value should be configured to 
-            a value greater than 0x40 to prevent generating an immediate reset.
-              
-        (#) Optionally you can enable the Early wakeup interrupt which is 
-            generated when the counter reach 0x40.
-            Once enabled this interrupt cannot be disabled except by a system reset.
-                   
-        (#) Then the application program must refresh the WWDG counter at regular
-            intervals during normal operation to prevent an MCU reset, using
-            WWDG_SetCounter() function. This operation must occur only when
-            the counter value is lower than the refresh window value, 
-            programmed using WWDG_SetWindowValue().
-  
-  *  @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_wwdg.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @defgroup WWDG 
-  * @brief WWDG driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------------------- WWDG registers bit mask ---------------------------- */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
-#define BIT_MASK          ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
-  * @{
-  */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- *  @brief   Prescaler, Refresh window and Counter configuration functions 
- *
-@verbatim   
-  ==============================================================================
-    ##### Prescaler, Refresh window and Counter configuration functions #####
-  ==============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
-  * @param  None
-  * @retval None
-  */
-void WWDG_DeInit(void)
-{
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
-  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
-  * @brief  Sets the WWDG Prescaler.
-  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
-  *   This parameter can be one of the following values:
-  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
-  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
-  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
-  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
-  * @retval None
-  */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
-  uint32_t tmpreg = 0;
-  /* Check the parameters */
-  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
-  /* Clear WDGTB[1:0] bits */
-  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
-  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
-  tmpreg |= WWDG_Prescaler;
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Sets the WWDG window value.
-  * @param  WindowValue: specifies the window value to be compared to the downcounter.
-  *   This parameter value must be lower than 0x80.
-  * @retval None
-  */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
-  __IO uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
-  /* Clear W[6:0] bits */
-
-  tmpreg = WWDG->CFR & CFR_W_MASK;
-
-  /* Set W[6:0] bits according to WindowValue value */
-  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
-  /* Store the new value */
-  WWDG->CFR = tmpreg;
-}
-
-/**
-  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset. 
-  * @param  None
-  * @retval None
-  */
-void WWDG_EnableIT(void)
-{
-  WWDG->CFR |= WWDG_CFR_EWI;
-}
-
-/**
-  * @brief  Sets the WWDG counter value.
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
-  *   an immediate reset).
-  * @retval None
-  */
-void WWDG_SetCounter(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  /* Write to T[6:0] bits to configure the counter value, no need to do
-     a read-modify-write; writing a 0 to WDGA bit does nothing */
-  WWDG->CR = Counter & BIT_MASK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- *  @brief   WWDG activation functions 
- *
-@verbatim   
-  ==============================================================================
-                     ##### WWDG activation function #####
-  ==============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables WWDG and load the counter value.                  
-  * @param  Counter: specifies the watchdog counter value.
-  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
-  *   an immediate reset).
-  * @retval None
-  */
-void WWDG_Enable(uint8_t Counter)
-{
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- *  @brief   Interrupts and flags management functions 
- *
-@verbatim   
-  ==============================================================================
-                ##### Interrupts and flags management functions #####
-  ==============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
-  * @param  None
-  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
-  */
-FlagStatus WWDG_GetFlagStatus(void)
-{
-  FlagStatus bitstatus = RESET;
-    
-  if ((WWDG->SR) != (uint32_t)RESET)
-  {
-    bitstatus = SET;
-  }
-  else
-  {
-    bitstatus = RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Clears Early Wakeup interrupt flag.
-  * @param  None
-  * @retval None
-  */
-void WWDG_ClearFlag(void)
-{
-  WWDG->SR = (uint32_t)RESET;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/SConscript

@@ -1,14 +0,0 @@
-# for module compiling
-import os
-Import('RTT_ROOT')
-
-cwd = str(Dir('#'))
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')

bsp/stm32f0x/SConstruct

@@ -1,34 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread-stm32f0xx.' + rtconfig.TARGET_EXT
-
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-if rtconfig.PLATFORM == 'iar':
-	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-	env.Replace(ARFLAGS = [''])
-	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
-
-# make a building
-DoBuilding(TARGET, objs)

bsp/stm32f0x/applications/SConscript

@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/stm32f0x/applications/application.c

@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2009-01-05     Bernard      the first version
- * 2013-11-15     bright       add init thread and components initial
- */
-
-/**
- * @addtogroup STM32
- */
-/*@{*/
-
-#include <stdio.h>
-
-#include <board.h>
-#include <rtthread.h>
-
-#include "led.h"
-
-/* led thread entry */
-static void led_thread_entry(void* parameter)
-{
-	while(1)
-	{
-        rt_hw_led_on();
-        rt_thread_delay(RT_TICK_PER_SECOND);
-
-        rt_hw_led_off();
-        rt_thread_delay(RT_TICK_PER_SECOND);
-	}
-}
-
-static void rt_init_thread_entry(void* parameter)
-{
-	rt_thread_t led_thread;
-
-/* Initialization RT-Thread Components */
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_init();
-#endif
-
-/* Set finsh device */
-#ifdef  RT_USING_FINSH
-    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif  /* RT_USING_FINSH */
-
-    /* Create led thread */
-    led_thread = rt_thread_create("led",
-    		led_thread_entry, RT_NULL,
-    		256, 20, 20);
-    if(led_thread != RT_NULL)
-    	rt_thread_startup(led_thread);
-}
-
-int rt_application_init()
-{
-	rt_thread_t init_thread;
-
-#if (RT_THREAD_PRIORITY_MAX == 32)
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   512, 8, 20);
-#else
-    init_thread = rt_thread_create("init",
-                                   rt_init_thread_entry, RT_NULL,
-                                   512, 80, 20);
-#endif
-    if(init_thread != RT_NULL)
-    	rt_thread_startup(init_thread);
-
-    return 0;
-}
-
-
-/*@}*/

bsp/stm32f0x/applications/startup.c

@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-31     Bernard      first implementation
- * 2013-11-15     bright       modify for stm32f0xx version and components initial
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-/**
- * @addtogroup STM32
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define STM32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define STM32_SRAM_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define STM32_SRAM_BEGIN    (&__bss_end)
-#endif
-
-/*******************************************************************************
-* Function Name  : assert_failed
-* Description    : Reports the name of the source file and the source line number
-*                  where the assert error has occurred.
-* Input          : - file: pointer to the source file name
-*                  - line: assert error line source number
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void assert_failed(uint8_t* file, uint32_t line)
-{
-	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
-	rt_kprintf("       file  %s\r\n", file);
-	rt_kprintf("       line  %d\r\n", line);
-
-	while (1) ;
-}
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* init board */
-	rt_hw_board_init();
-
-	/* show version */
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END);
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-	/* init application */
-	rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main(void)
-{
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
-
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
-
-	return 0;
-}
-
-/*@}*/

bsp/stm32f0x/drivers/SConscript

@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'drivers')
-src	= Glob('*.c')
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/stm32f0x/drivers/board.c

@@ -1,150 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2009-01-05     Bernard      first implementation
- * 2013-11-15     bright       add RCC initial and print RCC freq function
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#include "usart.h"
-
-/**
- * @addtogroup STM32
- */
-
-/*@{*/
-
-/*******************************************************************************
-* Function Name  : NVIC_Configuration
-* Description    : Configures Vector Table base location.
-* Input          : None
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void NVIC_Configuration(void)
-{
-//    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-/**
-* @brief  Inserts a delay time.
-* @param  nCount: specifies the delay time length.
-* @retval None
-*/
-static void Delay(__IO uint32_t nCount)
-{
-	/* Decrement nCount value */
-	while (nCount != 0)
-	{
-		nCount--;
-	}
-}
-
-/**
- * This RCC initial for system.
- * use HSI clock source and pll
- * HSI = 8; sysclk = 8/2 * 12 = 48MHZ
- * sysclk source is pllclk
- * AHB prescaler is 1, HCLK = SYSCKL = SystemCoreClock = 48MHZ
- */
-static void RCC_Configuration(void)
-{
-	RCC_DeInit();
-	/* setup HSI */
-	RCC_HSICmd(ENABLE);
-	/* Configure PLL source is HSI */
-	RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_12);
-	RCC_PLLCmd(ENABLE);
-	/* Configure SYSCLK source is PLL */
-	RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-	/* Conigure AHB prescaler value is 1 */
-	RCC_HCLKConfig(RCC_SYSCLK_Div1);
-	/* Delay for RCC setup */
-	Delay(0x3FFFF);
-	/* Update SystemCoreClock value from RCC configure */
-	SystemCoreClockUpdate();
-}
-
-#ifdef PRINT_RCC_FREQ_INFO
-/**
- * print RCC freq information
- *
- * for example:
- *
- * SYSCLK_Frequency is 48000000HZ
- * PCLK_Frequency is 48000000HZ
- * HCLK_Frequency is 48000000HZ
- * CECCLK_Frequency is 32786HZ
- * ADCCLK_Frequency is 14000000HZ
- * USART1CLK_Frequency is 48000000HZ
- * I2C1CLK_Frequency is 8000000HZ
- * SystemCoreClock is 48000000HZ
- *
- */
-void print_rcc_freq_info(void)
-{
-	RCC_ClocksTypeDef RCC_ClockFreq;
-
-	RCC_GetClocksFreq(&RCC_ClockFreq);
-
-	rt_kprintf("\nSYSCLK_Frequency is %dHZ", RCC_ClockFreq.SYSCLK_Frequency);
-	rt_kprintf("\nPCLK_Frequency is %dHZ", RCC_ClockFreq.PCLK_Frequency);
-	rt_kprintf("\nHCLK_Frequency is %dHZ", RCC_ClockFreq.HCLK_Frequency);
-
-	rt_kprintf("\nCECCLK_Frequency is %dHZ", RCC_ClockFreq.CECCLK_Frequency);
-	rt_kprintf("\nADCCLK_Frequency is %dHZ", RCC_ClockFreq.ADCCLK_Frequency);
-	rt_kprintf("\nUSART1CLK_Frequency is %dHZ", RCC_ClockFreq.USART1CLK_Frequency);
-	rt_kprintf("\nI2C1CLK_Frequency is %dHZ", RCC_ClockFreq.I2C1CLK_Frequency);
-	rt_kprintf("\nSystemCoreClock is %dHZ\n", SystemCoreClock);
-}
-#endif
-
-/**
- * This is the timer interrupt service routine.
- *
- */
-void SysTick_Handler(void)
-{
-	/* enter interrupt */
-	rt_interrupt_enter();
-
-	rt_tick_increase();
-
-	/* leave interrupt */
-	rt_interrupt_leave();
-}
-/**
- * This function will initial STM32 board.
- */
-void rt_hw_board_init()
-{
-	/* NVIC Configuration */
-	NVIC_Configuration();
-
-	/* Configure the SysTick */
-	RCC_Configuration();
-	SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
-
-	/* Initial usart deriver, and set console device */
-	rt_hw_usart_init();
-#ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-	/* Print RCC freq info */
-#ifdef PRINT_RCC_FREQ_INFO
-	print_rcc_freq_info();
-#endif
-	/* Call components board initial (use INIT_BOARD_EXPORT()) */
-#ifdef RT_USING_COMPONENTS_INIT
-    rt_components_board_init();
-#endif
-}
-
-/*@}*/

bsp/stm32f0x/drivers/board.h

@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2009-09-22     Bernard      add board.h to this bsp
- * 2013-11-15     bright       fix SRAM size for heap management
- */
-
-// <<< Use Configuration Wizard in Context Menu >>>
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-#include <stm32f0xx.h>
-
-/* board configuration */
-// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
-// 	<i>Default: 1
-#define STM32_USE_SDIO			0
-
-/* whether use board external SRAM memory */
-// <e>Use external SRAM memory on the board
-// 	<i>Enable External SRAM memory
-#define STM32_EXT_SRAM          0
-//	<o>Begin Address of External SRAM
-//		<i>Default: 0x68000000
-#define STM32_EXT_SRAM_BEGIN    0x68000000 /* the begining address of external SRAM */
-//	<o>End Address of External SRAM
-//		<i>Default: 0x68080000
-#define STM32_EXT_SRAM_END      0x68080000 /* the end address of external SRAM */
-// </e>
-
-// <o> Internal SRAM memory size[Kbytes] <8-64>
-//	<i>Default: 64
-#define STM32_SRAM_SIZE         8
-#define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
-
-void rt_hw_board_init(void);
-
-/* SD Card init function */
-void rt_hw_msd_init(void);
-
-#define PRINT_RCC_FREQ_INFO
-
-#endif
-
-// <<< Use Configuration Wizard in Context Menu >>>

bsp/stm32f0x/drivers/led.c

@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-15     bright       the first version
- */
-
-#include <rtthread.h>
-#include "led.h"
-
-/*
-LED_GREEN: PC8
-LED_RED  : PC9
-*/
-
-/* Initial led gpio pin  */
-int rt_hw_led_init(void)
-{
-    GPIO_InitTypeDef  GPIO_InitStructure;
-
-    /* Enable the GPIO_LED Clock */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
-
-    /* Configure the GPIO_LED pin */
-    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
-    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-    GPIO_Init(GPIOC, &GPIO_InitStructure);
-
-    return 0;
-}
-/* Initial components for device */
-INIT_DEVICE_EXPORT(rt_hw_led_init);

bsp/stm32f0x/drivers/led.h

@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-13-05     bright       the first version
- */
-
-#ifndef __LED_H__
-#define __LED_H__
-
-#include <rtthread.h>
-#include <stm32f0xx.h>
-
-#define rt_hw_led_on()   GPIO_SetBits(GPIOC, GPIO_Pin_9)
-#define rt_hw_led_off()  GPIO_ResetBits(GPIOC, GPIO_Pin_9)
-
-int rt_hw_led_init(void);
-
-#endif
-

bsp/stm32f0x/drivers/stm32f0xx_conf.h

@@ -1,81 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    ADC_DMA/stm32f0xx_conf.h 
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   Library configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CONF_H
-#define __STM32F0XX_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Comment the line below to disable peripheral header file inclusion */
-#include "stm32f0xx_adc.h"
-#include "stm32f0xx_cec.h"
-#include "stm32f0xx_crc.h"
-#include "stm32f0xx_comp.h"
-#include "stm32f0xx_dac.h"
-#include "stm32f0xx_dbgmcu.h"
-#include "stm32f0xx_dma.h"
-#include "stm32f0xx_exti.h"
-#include "stm32f0xx_flash.h"
-#include "stm32f0xx_gpio.h"
-#include "stm32f0xx_syscfg.h"
-#include "stm32f0xx_i2c.h"
-#include "stm32f0xx_iwdg.h"
-#include "stm32f0xx_pwr.h"
-#include "stm32f0xx_rcc.h"
-#include "stm32f0xx_rtc.h"
-#include "stm32f0xx_spi.h"
-#include "stm32f0xx_tim.h"
-#include "stm32f0xx_usart.h"
-#include "stm32f0xx_wwdg.h"
-#include "stm32f0xx_misc.h"  /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the 
-   Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT    1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function which reports 
-  *         the name of the source file and the source line number of the call 
-  *         that failed. If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F0XX_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/drivers/stm32f0xx_it.c

@@ -1,96 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f0xx_it.c 
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
-  * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
-  *          peripherals interrupt service routine.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include <stm32f0xx.h>
-
-/** @addtogroup STM32F0-Discovery_Demo
-  * @{
-  */
-
-/** @addtogroup STM32F0XX_IT
-  * @brief Interrupts driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/*            Cortex-M0 Processor Exceptions Handlers                         */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles NMI exception.
-  * @param  None
-  * @retval None
-  */
-void NMI_Handler(void)
-{
-}
-
-/**
-  * @brief  This function handles SVCall exception.
-  * @param  None
-  * @retval None
-  */
-void SVC_Handler(void)
-{
-}
-
-
-/******************************************************************************/
-/*                 STM32F0xx Peripherals Interrupt Handlers                   */
-/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
-/*  available peripheral interrupt handler's name please refer to the startup */
-/*  file (startup_stm32f0xx.s).                                               */
-/******************************************************************************/
-
-/**
-  * @brief  This function handles PPP interrupt request.
-  * @param  None
-  * @retval None
-  */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32f0x/drivers/usart.c

@@ -1,299 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-15     bright       the first version
- */
-
-#include <stm32f0xx.h>
-#include <rtdevice.h>
-#include "usart.h"
-
-/* USART1 */
-#define UART1_GPIO_TX			GPIO_Pin_9
-#define UART1_GPIO_TX_SOURCE	GPIO_PinSource9
-#define UART1_GPIO_RX			GPIO_Pin_10
-#define UART1_GPIO_RX_SOURCE	GPIO_PinSource10
-#define UART1_GPIO_AF			GPIO_AF_1
-#define UART1_GPIO				GPIOA
-
-/* USART2 */
-#define UART2_GPIO_TX			GPIO_Pin_2
-#define UART2_GPIO_TX_SOURCE	GPIO_PinSource2
-#define UART2_GPIO_RX			GPIO_Pin_3
-#define UART2_GPIO_RX_SOURCE	GPIO_PinSource3
-#define UART2_GPIO_AF			GPIO_AF_1
-#define UART2_GPIO				GPIOA
-
-/* STM32 uart driver */
-struct stm32_uart
-{
-    USART_TypeDef* uart_device;
-    IRQn_Type irq;
-};
-
-static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct stm32_uart* uart;
-    USART_InitTypeDef USART_InitStructure;
-
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(cfg != RT_NULL);
-
-    uart = (struct stm32_uart *)serial->parent.user_data;
-
-    USART_InitStructure.USART_BaudRate = cfg->baud_rate;
-
-    if (cfg->data_bits == DATA_BITS_8)
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-
-    if (cfg->stop_bits == STOP_BITS_1)
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-    else if (cfg->stop_bits == STOP_BITS_2)
-        USART_InitStructure.USART_StopBits = USART_StopBits_2;
-
-    USART_InitStructure.USART_Parity = USART_Parity_No;
-    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-    USART_Init(uart->uart_device, &USART_InitStructure);
-
-    /* Enable USART */
-    USART_Cmd(uart->uart_device, ENABLE);
-    /* enable interrupt */
-    USART_ITConfig(uart->uart_device, USART_IT_RXNE, ENABLE);
-
-    return RT_EOK;
-}
-
-static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct stm32_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct stm32_uart *)serial->parent.user_data;
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        UART_DISABLE_IRQ(uart->irq);
-        break;
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        UART_ENABLE_IRQ(uart->irq);
-        break;
-    }
-
-    return RT_EOK;
-}
-
-static int stm32_putc(struct rt_serial_device *serial, char c)
-{
-    struct stm32_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct stm32_uart *)serial->parent.user_data;
-
-    USART_ClearFlag(uart->uart_device,USART_FLAG_TC);
-    uart->uart_device->TDR = c;
-    while (!(uart->uart_device->ISR & USART_FLAG_TC));
-
-    return 1;
-}
-
-static int stm32_getc(struct rt_serial_device *serial)
-{
-    int ch;
-    struct stm32_uart* uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct stm32_uart *)serial->parent.user_data;
-
-    ch = -1;
-    if (uart->uart_device->ISR & USART_FLAG_RXNE)
-    {
-        ch = uart->uart_device->RDR & 0xff;
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops stm32_uart_ops =
-{
-    stm32_configure,
-    stm32_control,
-    stm32_putc,
-    stm32_getc,
-};
-
-#if defined(RT_USING_UART1)
-/* UART1 device driver structure */
-struct stm32_uart uart1 =
-{
-    USART1,
-    USART1_IRQn,
-};
-struct rt_serial_device serial1;
-
-void USART1_IRQHandler(void)
-{
-    struct stm32_uart* uart;
-
-    uart = &uart1;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-    if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
-    {
-        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
-    }
-    if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
-    {
-        /* clear interrupt */
-        USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* RT_USING_UART1 */
-
-#if defined(RT_USING_UART2)
-/* UART2 device driver structure */
-struct stm32_uart uart2 =
-{
-    USART2,
-    USART2_IRQn,
-};
-struct rt_serial_device serial2;
-
-void USART2_IRQHandler(void)
-{
-    struct stm32_uart* uart;
-
-    uart = &uart2;
-
-    /* enter interrupt */
-    rt_interrupt_enter();
-    if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
-    {
-        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
-    }
-    if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
-    {
-        /* clear interrupt */
-        USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
-    }
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-#endif /* RT_USING_UART2 */
-
-static void RCC_Configuration(void)
-{
-#ifdef RT_USING_UART1
-    /* Enable GPIO clock */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-    /* Enable USART clock */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
-#endif /* RT_USING_UART1 */
-
-#ifdef RT_USING_UART2
-    /* Enable GPIO clock */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-    /* Enable USART clock */
-    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
-#endif /* RT_USING_UART2 */
-
-}
-
-static void GPIO_Configuration(void)
-{
-    GPIO_InitTypeDef GPIO_InitStructure;
-
-#ifdef RT_USING_UART1
-	/* Connect PXx to USARTx_Tx */
-	GPIO_PinAFConfig(UART1_GPIO, UART1_GPIO_TX_SOURCE, UART1_GPIO_AF);
-
-	/* Connect PXx to USARTx_Rx */
-	GPIO_PinAFConfig(UART1_GPIO, UART1_GPIO_RX_SOURCE, UART1_GPIO_AF);
-
-	/* Configure USART Tx, Rx as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX | UART1_GPIO_RX;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
-	GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
-#endif /* RT_USING_UART1 */
-
-#ifdef RT_USING_UART2
-	/* Connect PXx to USARTx_Tx */
-	GPIO_PinAFConfig(UART2_GPIO, UART2_GPIO_TX_SOURCE, UART2_GPIO_AF);
-
-	/* Connect PXx to USARTx_Rx */
-	GPIO_PinAFConfig(UART2_GPIO, UART2_GPIO_RX_SOURCE, UART2_GPIO_AF);
-
-	/* Configure USART Tx, Rx as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX | UART2_GPIO_RX;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-	GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
-	GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
-#endif /* RT_USING_UART2 */
-}
-
-static void NVIC_Configuration(struct stm32_uart* uart)
-{
-    NVIC_InitTypeDef NVIC_InitStructure;
-
-    /* Enable the USART Interrupt */
-    NVIC_InitStructure.NVIC_IRQChannel = uart->irq;
-    NVIC_InitStructure.NVIC_IRQChannelPriority = 0;
-    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);
-}
-
-void rt_hw_usart_init(void)
-{
-    struct stm32_uart* uart;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-    RCC_Configuration();
-    GPIO_Configuration();
-
-#ifdef RT_USING_UART1
-    uart = &uart1;
-    config.baud_rate = BAUD_RATE_115200;
-
-    serial1.ops    = &stm32_uart_ops;
-    serial1.config = config;
-
-    NVIC_Configuration(&uart1);
-
-    /* register UART1 device */
-    rt_hw_serial_register(&serial1, "uart1",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-#endif /* RT_USING_UART1 */
-
-#ifdef RT_USING_UART2
-    uart = &uart2;
-
-    config.baud_rate = BAUD_RATE_115200;
-    serial2.ops    = &stm32_uart_ops;
-    serial2.config = config;
-
-    NVIC_Configuration(&uart2);
-
-    /* register UART1 device */
-    rt_hw_serial_register(&serial2, "uart2",
-                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
-                          uart);
-#endif /* RT_USING_UART2 */
-}

bsp/stm32f0x/drivers/usart.h

@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2013-11-15     bright       the first version
- */
-
-#ifndef __USART_H__
-#define __USART_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-#include "stm32f0xx.h"
-
-#define RT_USING_UART1
-#define RT_USING_UART2
-
-#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
-#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
-
-void rt_hw_usart_init(void);
-
-#endif

bsp/stm32f0x/project.uvproj

@@ -1,829 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-  <SchemaVersion>1.1</SchemaVersion>
-  <Header>### uVision Project, (C) Keil Software</Header>
-  <Targets>
-    <Target>
-      <TargetName>rt-thread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>STM32F051R8</Device>
-          <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x800FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0")</Cpu>
-          <FlashUtilSpec />
-          <StartupFile>"Startup\ST\STM32F0xx\startup_stm32f0xx.s" ("STM32F0xx Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F05x_64 -FS08000000 -FL010000)</FlashDriverDll>
-          <DeviceId>6188</DeviceId>
-          <RegisterFile>stm32f0xx.h</RegisterFile>
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
-          <SFDFile>SFD\ST\STM32F0xx\STM32F051xx.sfr</SFDFile>
-          <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath>ST\STM32F0xx\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F0xx\</DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>template</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>0</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments />
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments />
-          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>13</TargetSelection>
-          <SimDlls>
-            <CpuDll />
-            <CpuDllArguments />
-            <PeripheralDll />
-            <PeripheralDllArguments />
-            <InitializationFile />
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll />
-            <CpuDllArguments />
-            <PeripheralDll />
-            <PeripheralDllArguments />
-            <InitializationFile />
-            <Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4104</DriverSelection>
-          </Flash1>
-          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4 />
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName />
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>1</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector />
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
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-            <oTime>0</oTime>
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bsp/stm32f0x/project.uvprojx

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-              <FilePath>../../components/finsh/msh.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>msh_cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../components/finsh/msh_cmd.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>msh_file.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../../components/finsh/msh_file.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-</Project>

bsp/stm32f0x/readme.txt

@@ -1,3 +0,0 @@
-board info:
-stm32f0discovery
-http://www.st.com/stm32f0discovery

bsp/stm32f0x/rtconfig.h

@@ -1,116 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX	   8
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND	100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-#define RT_DEBUG_INIT 1
-#define RT_USING_OVERFLOW_CHECK
-
-/* Using Hook */
-/* #define RT_USING_HOOK */
-
-/* Using Software Timer */
-/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	10
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-/* #define RT_USING_EVENT */
-
-/* Using MailBox */
-/* #define RT_USING_MAILBOX */
-
-/* Using Message Queue */
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using Small MM */
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-#define RT_USING_COMPONENTS_INIT
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
-#define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
-
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
-#define RT_CONSOLE_DEVICE_NAME	    "uart1"
-
-
-
-/* SECTION: finsh, a C-Express shell */
-#define RT_USING_FINSH
-/* configure finsh parameters */
-#define FINSH_THREAD_PRIORITY 25
-#define FINSH_THREAD_STACK_SIZE	1024
-#define FINSH_HISTORY_LINES	1
-/* Using symbol table */
-//#define FINSH_USING_SYMTAB
-//#define FINSH_USING_DESCRIPTION
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_ONLY
-
-/* SECTION: libc management */
-// #define RT_USING_LIBC
-
-/* SECTION: device filesystem */
-/* #define RT_USING_DFS */
-//#define RT_USING_DFS_ELMFAT
-#define RT_DFS_ELM_WORD_ACCESS
-/* Reentrancy (thread safe) of the FatFs module.  */
-#define RT_DFS_ELM_REENTRANT
-/* Number of volumes (logical drives) to be used. */
-#define RT_DFS_ELM_DRIVES			2
-/* #define RT_DFS_ELM_USE_LFN			1 */
-#define RT_DFS_ELM_MAX_LFN			255
-/* Maximum sector size to be handled. */
-#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
-
-#define RT_USING_DFS_ROMFS
-
-/* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
-
-#endif

bsp/stm32f0x/rtconfig.py

@@ -1,127 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arm'
-CPU='cortex-m0'
-CROSS_TOOL='keil'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-# cross_tool provides the cross compiler
-# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
-if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
-elif CROSS_TOOL == 'keil':
-	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= 'C:/Keil'
-elif CROSS_TOOL == 'iar':
-    print('================ERROR============================')
-    print('Not support iar yet!')
-    print('=================================================')
-    exit(0)
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-#BUILD = 'debug'
-BUILD = 'release'
-STM32_TYPE = 'STM32F0XX'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC = PREFIX + 'gcc'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-
-    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE 
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
-
-    CPATH = ''
-    LPATH = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
-
-elif PLATFORM == 'iar':
-    # toolchains
-    CC = 'iccarm'
-    AS = 'iasmarm'
-    AR = 'iarchive'
-    LINK = 'ilinkarm'
-    TARGET_EXT = 'out'
-
-    DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D STM32F10X_HD'
-
-    CFLAGS = DEVICE
-    CFLAGS += ' --diag_suppress Pa050'
-    CFLAGS += ' --no_cse' 
-    CFLAGS += ' --no_unroll' 
-    CFLAGS += ' --no_inline' 
-    CFLAGS += ' --no_code_motion' 
-    CFLAGS += ' --no_tbaa' 
-    CFLAGS += ' --no_clustering' 
-    CFLAGS += ' --no_scheduling' 
-    CFLAGS += ' --debug' 
-    CFLAGS += ' --endian=little' 
-    CFLAGS += ' --cpu=Cortex-M0' 
-    CFLAGS += ' -e' 
-    CFLAGS += ' --fpu=None'
-    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
-    CFLAGS += ' -Ol'    
-    CFLAGS += ' --use_c++_inline'
-        
-    AFLAGS = ''
-    AFLAGS += ' -s+' 
-    AFLAGS += ' -w+' 
-    AFLAGS += ' -r' 
-    AFLAGS += ' --cpu Cortex-M0' 
-    AFLAGS += ' --fpu None' 
-
-    LFLAGS = ' --config stm32f0xx_flash.icf'
-    LFLAGS += ' --redirect _Printf=_PrintfTiny' 
-    LFLAGS += ' --redirect _Scanf=_ScanfSmall' 
-    LFLAGS += ' --entry __iar_program_start'    
-
-    EXEC_PATH = EXEC_PATH + '/arm/bin/'
-    POST_ACTION = ''

bsp/stm32f0x/stm32_rom.ld

@@ -1,141 +0,0 @@
-/*
- * linker script for STM32F0x with GNU ld
- * bernard.xiong 2009-10-14
- */
-
-/* Program Entry, set to mark it as "used" and avoid gc */
-MEMORY
-{
-    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 64k /* 64KB flash */
-    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  8k /* 8K sram */
-}
-ENTRY(Reset_Handler)
-_system_stack_size = 0x100;
-
-SECTIONS
-{
-    .text :
-    {
-        . = ALIGN(4);
-        KEEP(*(.isr_vector))            /* Startup code */
-        . = ALIGN(4);
-        *(.text)                        /* remaining code */
-        *(.text.*)                      /* remaining code */
-        *(.rodata)                      /* read-only data (constants) */
-        *(.rodata*)
-        *(.glue_7)
-        *(.glue_7t)
-        *(.gnu.linkonce.t*)
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        /* section information for initial. */
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-        . = ALIGN(4);
-
-        . = ALIGN(4);
-        _etext = .;
-    } > CODE = 0
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-
-        /* This is used by the startup in order to initialize the .data secion */
-        _sidata = .;
-    } > CODE
-    __exidx_end = .;
-
-    /* .data section which is used for initialized data */
-
-    .data : AT (_sidata)
-    {
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _sdata = . ;
-
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d*)
-
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .data secion */
-        _edata = . ;
-    } >DATA
-
-    .stack : 
-    {
-        . = . + _system_stack_size;
-        . = ALIGN(4);
-        _estack = .;
-    } >DATA
-
-    __bss_start = .;
-    .bss :
-    {
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _sbss = .;
-
-        *(.bss)
-        *(.bss.*)
-        *(COMMON)
-
-        . = ALIGN(4);
-        /* This is used by the startup in order to initialize the .bss secion */
-        _ebss = . ;
-        
-        *(.bss.init)
-    } > DATA
-    __bss_end = .;
-
-    _end = .;
-
-    /* Stabs debugging sections.  */
-    .stab          0 : { *(.stab) }
-    .stabstr       0 : { *(.stabstr) }
-    .stab.excl     0 : { *(.stab.excl) }
-    .stab.exclstr  0 : { *(.stab.exclstr) }
-    .stab.index    0 : { *(.stab.index) }
-    .stab.indexstr 0 : { *(.stab.indexstr) }
-    .comment       0 : { *(.comment) }
-    /* DWARF debug sections.
-     * Symbols in the DWARF debugging sections are relative to the beginning
-     * of the section so we begin them at 0.  */
-    /* DWARF 1 */
-    .debug          0 : { *(.debug) }
-    .line           0 : { *(.line) }
-    /* GNU DWARF 1 extensions */
-    .debug_srcinfo  0 : { *(.debug_srcinfo) }
-    .debug_sfnames  0 : { *(.debug_sfnames) }
-    /* DWARF 1.1 and DWARF 2 */
-    .debug_aranges  0 : { *(.debug_aranges) }
-    .debug_pubnames 0 : { *(.debug_pubnames) }
-    /* DWARF 2 */
-    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-    .debug_abbrev   0 : { *(.debug_abbrev) }
-    .debug_line     0 : { *(.debug_line) }
-    .debug_frame    0 : { *(.debug_frame) }
-    .debug_str      0 : { *(.debug_str) }
-    .debug_loc      0 : { *(.debug_loc) }
-    .debug_macinfo  0 : { *(.debug_macinfo) }
-    /* SGI/MIPS DWARF 2 extensions */
-    .debug_weaknames 0 : { *(.debug_weaknames) }
-    .debug_funcnames 0 : { *(.debug_funcnames) }
-    .debug_typenames 0 : { *(.debug_typenames) }
-    .debug_varnames  0 : { *(.debug_varnames) }
-}

bsp/stm32f0x/stm32_rom.sct

@@ -1,15 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00010000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00010000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  RW_IRAM1 0x20000000 0x00002000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-}
-

bsp/stm32f0x/template.uvproj

@@ -1,390 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
-
-  <SchemaVersion>1.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rt-thread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>STM32F051R8</Device>
-          <Vendor>STMicroelectronics</Vendor>
-          <Cpu>IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x800FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0")</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile>"Startup\ST\STM32F0xx\startup_stm32f0xx.s" ("STM32F0xx Startup Code")</StartupFile>
-          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F05x_64 -FS08000000 -FL010000)</FlashDriverDll>
-          <DeviceId>6188</DeviceId>
-          <RegisterFile>stm32f0xx.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>SFD\ST\STM32F0xx\STM32F051xx.sfr</SFDFile>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath>ST\STM32F0xx\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F0xx\</DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>template</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>0</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments></SimDllArguments>
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
-          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>13</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4104</DriverSelection>
-          </Flash1>
-          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>1</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>4</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-    </Target>
-  </Targets>
-
-</Project>

bsp/stm32f0x/template.uvprojx

@@ -1,393 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
-  <SchemaVersion>2.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rt-thread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>STM32F051R8</Device>
-          <Vendor>STMicroelectronics</Vendor>
-          <PackID>Keil.STM32F0xx_DFP.1.2.0</PackID>
-          <PackURL>http://www.keil.com/pack/</PackURL>
-          <Cpu>IROM(0x08000000,0x10000) IRAM(0x20000000,0x2000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_64 -FS08000000 -FL010000 -FP0($$Device:STM32F051R8$Flash\STM32F0xx_64.FLM))</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:STM32F051R8$Device\Include\stm32f0xx.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:STM32F051R8$SVD\STM32F0xx.svd</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath>ST\STM32F0xx\</RegisterFilePath>
-          <DBRegisterFilePath>ST\STM32F0xx\</DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>template</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>0</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments></SimDllArguments>
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments></TargetDllArguments>
-          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>13</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>STLink\ST-LINKIII-KEIL_SWO.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4104</DriverSelection>
-          </Flash1>
-          <Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>1</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>1</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x8000000</StartAddress>
-                <Size>0x10000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x2000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>4</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-    </Target>
-  </Targets>
-
-</Project>

bsp/stm32f107/.config

@@ -1,330 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# RT-Thread Configuration
-#
-
-#
-# RT-Thread Kernel
-#
-CONFIG_RT_NAME_MAX=8
-# CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
-# CONFIG_RT_THREAD_PRIORITY_8 is not set
-CONFIG_RT_THREAD_PRIORITY_32=y
-# CONFIG_RT_THREAD_PRIORITY_256 is not set
-CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=1000
-CONFIG_RT_USING_OVERFLOW_CHECK=y
-CONFIG_RT_USING_HOOK=y
-CONFIG_RT_USING_IDLE_HOOK=y
-CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
-CONFIG_RT_DEBUG=y
-CONFIG_RT_DEBUG_COLOR=y
-# CONFIG_RT_DEBUG_INIT_CONFIG is not set
-# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
-# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
-# CONFIG_RT_DEBUG_IPC_CONFIG is not set
-# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
-# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
-# CONFIG_RT_DEBUG_MEM_CONFIG is not set
-# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
-# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
-# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
-
-#
-# Inter-Thread communication
-#
-CONFIG_RT_USING_SEMAPHORE=y
-CONFIG_RT_USING_MUTEX=y
-CONFIG_RT_USING_EVENT=y
-CONFIG_RT_USING_MAILBOX=y
-CONFIG_RT_USING_MESSAGEQUEUE=y
-# CONFIG_RT_USING_SIGNALS is not set
-
-#
-# Memory Management
-#
-CONFIG_RT_USING_MEMPOOL=y
-CONFIG_RT_USING_MEMHEAP=y
-# CONFIG_RT_USING_NOHEAP is not set
-CONFIG_RT_USING_SMALL_MEM=y
-# CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
-# CONFIG_RT_USING_MEMTRACE is not set
-CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
-CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_INTERRUPT_INFO is not set
-CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
-CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
-CONFIG_RT_VER_NUM=0x40000
-CONFIG_ARCH_ARM=y
-CONFIG_ARCH_ARM_CORTEX_M=y
-CONFIG_ARCH_ARM_CORTEX_M3=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
-
-#
-# RT-Thread Components
-#
-CONFIG_RT_USING_COMPONENTS_INIT=y
-CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
-CONFIG_RT_MAIN_THREAD_PRIORITY=10
-
-#
-# C++ features
-#
-# CONFIG_RT_USING_CPLUSPLUS is not set
-
-#
-# Command shell
-#
-CONFIG_RT_USING_FINSH=y
-CONFIG_FINSH_THREAD_NAME="tshell"
-CONFIG_FINSH_USING_HISTORY=y
-CONFIG_FINSH_HISTORY_LINES=5
-CONFIG_FINSH_USING_SYMTAB=y
-CONFIG_FINSH_USING_DESCRIPTION=y
-# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
-CONFIG_FINSH_THREAD_PRIORITY=20
-CONFIG_FINSH_THREAD_STACK_SIZE=4096
-CONFIG_FINSH_CMD_SIZE=80
-# CONFIG_FINSH_USING_AUTH is not set
-CONFIG_FINSH_USING_MSH=y
-CONFIG_FINSH_USING_MSH_DEFAULT=y
-# CONFIG_FINSH_USING_MSH_ONLY is not set
-CONFIG_FINSH_ARG_MAX=10
-
-#
-# Device virtual file system
-#
-# CONFIG_RT_USING_DFS is not set
-
-#
-# Device Drivers
-#
-CONFIG_RT_USING_DEVICE_IPC=y
-CONFIG_RT_PIPE_BUFSZ=512
-CONFIG_RT_USING_SERIAL=y
-CONFIG_RT_SERIAL_USING_DMA=y
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
-# CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
-CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
-# CONFIG_RT_USING_MTD_NOR is not set
-# CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_MTD is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
-# CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
-# CONFIG_RT_USING_WDT is not set
-# CONFIG_RT_USING_AUDIO is not set
-
-#
-# Using WiFi
-#
-# CONFIG_RT_USING_WIFI is not set
-
-#
-# Using USB
-#
-# CONFIG_RT_USING_USB_HOST is not set
-# CONFIG_RT_USING_USB_DEVICE is not set
-
-#
-# POSIX layer and C standard library
-#
-CONFIG_RT_USING_LIBC=y
-# CONFIG_RT_USING_PTHREADS is not set
-
-#
-# Network
-#
-
-#
-# Socket abstraction layer
-#
-# CONFIG_RT_USING_SAL is not set
-
-#
-# light weight TCP/IP stack
-#
-# CONFIG_RT_USING_LWIP is not set
-
-#
-# Modbus master and slave stack
-#
-# CONFIG_RT_USING_MODBUS is not set
-
-#
-# AT commands
-#
-# CONFIG_RT_USING_AT is not set
-
-#
-# VBUS(Virtual Software BUS)
-#
-# CONFIG_RT_USING_VBUS is not set
-
-#
-# Utilities
-#
-# CONFIG_RT_USING_LOGTRACE is not set
-# CONFIG_RT_USING_RYM is not set
-# CONFIG_RT_USING_ULOG is not set
-# CONFIG_RT_USING_UTEST is not set
-
-#
-# ARM CMSIS
-#
-# CONFIG_RT_USING_CMSIS_OS is not set
-CONFIG_RT_USING_RTT_CMSIS=y
-# CONFIG_RT_USING_LWP is not set
-
-#
-# RT-Thread online packages
-#
-
-#
-# IoT - internet of things
-#
-# CONFIG_PKG_USING_PAHOMQTT is not set
-# CONFIG_PKG_USING_WEBCLIENT is not set
-# CONFIG_PKG_USING_WEBNET is not set
-# CONFIG_PKG_USING_MONGOOSE is not set
-# CONFIG_PKG_USING_WEBTERMINAL is not set
-# CONFIG_PKG_USING_CJSON is not set
-# CONFIG_PKG_USING_JSMN is not set
-# CONFIG_PKG_USING_LJSON is not set
-# CONFIG_PKG_USING_EZXML is not set
-# CONFIG_PKG_USING_NANOPB is not set
-
-#
-# Wi-Fi
-#
-
-#
-# Marvell WiFi
-#
-# CONFIG_PKG_USING_WLANMARVELL is not set
-
-#
-# Wiced WiFi
-#
-# CONFIG_PKG_USING_WLAN_WICED is not set
-# CONFIG_PKG_USING_COAP is not set
-# CONFIG_PKG_USING_NOPOLL is not set
-# CONFIG_PKG_USING_NETUTILS is not set
-# CONFIG_PKG_USING_AT_DEVICE is not set
-# CONFIG_PKG_USING_WIZNET is not set
-
-#
-# IoT Cloud
-#
-# CONFIG_PKG_USING_ONENET is not set
-# CONFIG_PKG_USING_GAGENT_CLOUD is not set
-# CONFIG_PKG_USING_ALI_IOTKIT is not set
-# CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
-
-#
-# security packages
-#
-# CONFIG_PKG_USING_MBEDTLS is not set
-# CONFIG_PKG_USING_libsodium is not set
-# CONFIG_PKG_USING_TINYCRYPT is not set
-
-#
-# language packages
-#
-# CONFIG_PKG_USING_LUA is not set
-# CONFIG_PKG_USING_JERRYSCRIPT is not set
-# CONFIG_PKG_USING_MICROPYTHON is not set
-
-#
-# multimedia packages
-#
-# CONFIG_PKG_USING_OPENMV is not set
-# CONFIG_PKG_USING_MUPDF is not set
-
-#
-# tools packages
-#
-# CONFIG_PKG_USING_CMBACKTRACE is not set
-# CONFIG_PKG_USING_EASYFLASH is not set
-# CONFIG_PKG_USING_EASYLOGGER is not set
-# CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_RDB is not set
-# CONFIG_PKG_USING_QRCODE is not set
-# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
-
-#
-# system packages
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_CAIRO is not set
-# CONFIG_PKG_USING_PIXMAN is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_FAL is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
-# CONFIG_PKG_USING_CMSIS is not set
-# CONFIG_PKG_USING_DFS_YAFFS is not set
-# CONFIG_PKG_USING_LITTLEFS is not set
-
-#
-# peripheral libraries and drivers
-#
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
-# CONFIG_PKG_USING_SHT2X is not set
-# CONFIG_PKG_USING_AHT10 is not set
-# CONFIG_PKG_USING_AP3216C is not set
-# CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_ICM20608 is not set
-# CONFIG_PKG_USING_U8G2 is not set
-# CONFIG_PKG_USING_BUTTON is not set
-# CONFIG_PKG_USING_MPU6XXX is not set
-# CONFIG_PKG_USING_PCF8574 is not set
-# CONFIG_PKG_USING_KENDRYTE_SDK is not set
-
-#
-# miscellaneous packages
-#
-# CONFIG_PKG_USING_LIBCSV is not set
-# CONFIG_PKG_USING_OPTPARSE is not set
-# CONFIG_PKG_USING_FASTLZ is not set
-# CONFIG_PKG_USING_MINILZO is not set
-# CONFIG_PKG_USING_QUICKLZ is not set
-# CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_CANFESTIVAL is not set
-# CONFIG_PKG_USING_ZLIB is not set
-# CONFIG_PKG_USING_DSTR is not set
-# CONFIG_PKG_USING_TINYFRAME is not set
-
-#
-# samples: kernel and components samples
-#
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
-# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
-# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
-# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-# CONFIG_PKG_USING_HELLO is not set
-CONFIG_SOC_STM32F1=y
-# CONFIG_RT_USING_UART1 is not set
-CONFIG_RT_USING_UART2=y
-# CONFIG_RT_USING_UART3 is not set
-# CONFIG_BSP_USING_RTC is not set
-CONFIG_BSP_USING_PIN=y

bsp/stm32f107/Kconfig

@@ -1,36 +0,0 @@
-mainmenu "RT-Thread Configuration"
-
-config BSP_DIR
-    string
-    option env="BSP_ROOT"
-    default "."
-
-config RTT_DIR
-    string
-    option env="RTT_ROOT"
-    default "../.."
-    
-# you can change the RTT_ROOT default "../.." to your rtthread_root,
-# example: default "F:/git_repositories/rt-thread"
-
-config PKGS_DIR
-    string
-    option env="PKGS_ROOT"
-    default "packages"
-    
-config ENV_DIR
-    string
-    option env="ENV_ROOT"
-    default "/"
-
-source "$RTT_DIR/Kconfig"
-source "$PKGS_DIR/Kconfig"
-
-
-config SOC_STM32F1
-    bool 
-    select ARCH_ARM_CORTEX_M3
-    default y
-
-source "$BSP_DIR/drivers/Kconfig"
-

bsp/stm32f107/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c

@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
-  clrex
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-  __ASM("bx lr"); 
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result=0;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-    uint8_t result=0;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-    uint16_t result=0;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-    uint32_t result=0;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif

bsp/stm32f107/Libraries/CMSIS/CM3/CoreSupport/core_cm3.h

@@ -1,1818 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- *   - Error 10: \n
- *     register uint32_t __regBasePri         __asm("basepri"); \n
- *     Error 10: Expecting ';'
- * .
- *   - Error 530: \n
- *     return(__regBasePri); \n
- *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * . 
- *   - Error 550: \n
- *     __regBasePri = (basePri & 0x1ff); \n
- *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- *   - Error 754: \n
- *     uint32_t RESERVED0[24]; \n
- *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
- * .
- *   - Error 750: \n
- *     #define __CM3_CORE_H__ \n
- *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- *   - Error 528: \n
- *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- *   - Error 751: \n
- *     } InterruptType_Type; \n
- *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note:  To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10  */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-    - CMSIS version number
-    - Cortex-M core registers and bitfields
-    - Cortex-M core peripheral base address
-  @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-  #define     __I     volatile                /*!< defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
-  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
-  @{
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
-  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
-  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
-  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
-  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
-  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
-  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
-  memory mapped structure for System Control Block (SCB)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
-  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
-  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
-  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
-  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
-  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
-  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
-} SCB_Type;                                                
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
-  memory mapped structure for Instrumentation Trace Macrocell (ITM)
-  @{
- */
-typedef struct
-{
-  __O  union  
-  {
-    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
-  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
-  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
-  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
-} ITM_Type;                                                
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
-  memory mapped structure for Interrupt Type
-  @{
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
-  memory mapped structure for Memory Protection Unit (MPU)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
-  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
-  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
-  memory mapped structure for Core Debug Register
-  @{
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
-
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-#define __RBIT                            __rbit
-#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
-#define __STREXB(value, ptr)              __strex(value, ptr)
-#define __STREXH(value, ptr)              __strex(value, ptr)
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param   priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX                           __clrex
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void)                                     */
-/* intrinsic void __DSB(void)                                     */
-/* intrinsic void __DMB(void)                                     */
-/* intrinsic void __set_PRIMASK();                                */
-/* intrinsic void __get_PRIMASK();                                */
-/* intrinsic void __set_FAULTMASK();                              */
-/* intrinsic void __get_FAULTMASK();                              */
-/* intrinsic uint32_t __REV(uint32_t value);                      */
-/* intrinsic uint32_t __REVSH(uint32_t value);                    */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *);              */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
-static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
-static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
-  Core  Function Interface containing:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Reset Functions
-*/
-/*@{*/
-
-/* ##########################   NVIC functions  #################################### */
-
-/**
- * @brief  Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param  PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field 
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-/**
- * @brief  Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field 
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn   The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn   The positive number of the external interrupt to disable
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn    The number of the device specifc interrupt
- * @return         1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending, 
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn    The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief  Read the active bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for read active bit
- * @return         1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active, 
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for set priority
- * @param  priority  The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for get priority
- * @return           The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/**
- * @brief  Encode the priority for an interrupt
- *
- * @param  PriorityGroup    The used priority group
- * @param  PreemptPriority  The preemptive priority value (starting from 0)
- * @param  SubPriority      The sub priority value (starting from 0)
- * @return                  The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/**
- * @brief  Decode the priority of an interrupt
- *
- * @param  Priority           The priority for the interrupt
- * @param  PriorityGroup      The used priority group
- * @param  pPreemptPriority   The preemptive priority value (starting from 0)
- * @param  pSubPriority       The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to 
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param   ticks   number of ticks between two interrupts
- * @return  1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
-  while(1);                                                    /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
-  Core Debug Interface containing:
-  - Core Debug Receive / Transmit Functions
-  - Core Debug Defines
-  - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief  Outputs a character via the ITM channel 0
- *
- * @param  ch   character to output
- * @return      character to output
- *
- * The function outputs a character via the ITM channel 0. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
-  return (ch);
-}
-
-
-/**
- * @brief  Inputs a character via variable ITM_RxBuffer
- *
- * @return      received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-
-
-/**
- * @brief  Check if a character via variable ITM_RxBuffer is available
- *
- * @return      1 = character available, 0 = no character available
- *
- * The function checks  variable ITM_RxBuffer whether a character is available or not. 
- * The function returns '1' if a character is available and '0' if no character is available. 
- */
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */

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-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p>&nbsp;</o:p></span></p>
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr>
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS
-update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;"></span>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS
-update History</span></h2>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
-            <ol>
-<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32F10x High-density Value line devices</b>.</span></li>
-            </ul>
-            <ol start="2">
-              <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>
-            </ol>
-
-
-            
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>
-                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>
-</ul>
-                <li class="MsoNormal" style="">
-
-                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">All
-STM32 devices definitions are commented by default. User has to select the
-appropriate device before starting else an error will be signaled on compile
-time.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
-                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li>
-</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
-to select if the user want to place the Vector Table in internal SRAM.
-An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
-                  </span></li>
-
-              </ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
-startup files for STM32 High-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>
-            </ul>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
-- 04/16/2010</span></h3>
-
-<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
-
-            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices&nbsp;(remove&nbsp;comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><br>
-                  </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
-startup files for STM32 XL-density&nbsp;devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ&nbsp;Handler (was missing in&nbsp;previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
-                </span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-</ul>
-<ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
-            <ul>
-              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
-            </ul>
-            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
-the stm32f10x.h file to support new Value line devices features: CEC
-peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
-HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
-HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
-purposes.<br>
-                  </span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
-                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
-                  </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
-                  </span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup files for STM32 Low-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
-files for STM32 Medium-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
-To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
-</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
-</span></li>
-              </ul>
-
-            </ul>
-
-<ul style="margin-top: 0in;" type="disc">
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F10x CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2011 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
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-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr>
-<td style="padding: 0cm;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
-<ol style="margin-top: 0cm;" start="1" type="1">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x CMSIS
-update History</a><o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
-</ol>
-<span style="font-family: &quot;Times New Roman&quot;;"></span>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x CMSIS
-update History</span></h2><br>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V3.5.0 / 11-March-2011<o:p></o:p></span></h3>
-            <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-            <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f10x.h
-</span>and <span style="font-style: italic;">startup_stm32f10x_hd_vl.s</span> files: remove the FSMC interrupt
-definition for STM32F10x High-density Value line devices.<br>
-</span></li>
-              <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">system_stm32f10x.c</span> file&nbsp;provided within the CMSIS folder. <br>
-</span></li>
-
-            </ul>
-
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0
-- 10/15/2010</span></h3>
-
-            <ol>
-<li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li>
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32F10x High-density Value line devices</b>.</span></li>
-            </ul>
-            <ol start="2">
-              <li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li>
-            </ol>
-
-
-            
-            <ul style="margin-top: 0in;" type="disc">
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support High-density Value line devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_HD_VL</span></span></li>
-                  <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, FSMC bits definition updated</span></li>
-</ul>
-                <li class="MsoNormal" style="">
-
-                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">All
-STM32 devices definitions are commented by default. User has to select the
-appropriate device before starting else an error will be signaled on compile
-time.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Add new IRQs definitons inside the IRQn_Type enumeration for STM23 High-density Value line devices.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">"<span style="font-weight: bold;">bool</span>" type removed.</span><br>
-                  <span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></li>
-</ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              <ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">"system_stm32f10x.c" </span><span style="font-weight: bold;"></span>moved to to "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Template</span>" directory. This file is also moved to each example directory under "<span style="font-weight: bold; font-style: italic;">STM32F10x_StdPeriph_Examples</span>".</span><br>
-<span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support High-density Value line devices.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add "<span style="font-style: italic;">VECT_TAB_SRAM</span>" inside "</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">system_stm32f10x.c</span></span><span style="font-size: 10pt; font-family: Verdana;">"
-to select if the user want to place the Vector Table in internal SRAM.
-An additional define is also to specify the Vector Table offset "<span style="font-style: italic;">VECT_TAB_OFFSET</span>".<br>
-                  </span></li>
-
-              </ul>
-<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add three
-startup files for STM32 High-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_hd_vl.s</span></span></li></ul>
-            </ul>
-            <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0
-- 04/16/2010</span></h3>
-
-<ol><li><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b></li></ol>
-<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32F10x XL-density devices</b>.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain<br></span></li></ul><ol start="2"><li><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b></li></ol>
-
-            <ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update to support XL-density devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">STM32F10X_XL</span></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IRQs for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update FLASH_TypeDef structure</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new IP instances TIM9..14</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC, AFIO, DBGMCU bits definition updated</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Correct IRQs definition for MD-, LD-, MD_VL- and LD_VL-density devices&nbsp;(remove&nbsp;comma "," at the end of enum list)<br></span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl() </span>function: update to support XL-density devices</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span> function: swap the order of SetSysClock() and SystemInit_ExtMemCtl() functions.&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><br>
-                  </span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS startup files:</span><span style="font-weight: bold; font-style: italic;"></span><span style="font-style: italic;"><span style="font-weight: bold;"></span></span></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">add three
-startup files for STM32 XL-density&nbsp;devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xl.s</span></span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">startup_stm32f10x_md_vl.s</span> for RIDE7: add USART3 IRQ&nbsp;Handler (was missing in&nbsp;previous version)</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add startup files for TrueSTUDIO toolchain</span></li></ul></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"></span></span>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0
-- 03/01/2010</span></h3>
-<ol style="margin-top: 0in;" start="1" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>
-</ol>
-<ul style="margin-top: 0in;" type="disc">
-
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS files updated to <span style="font-weight: bold;">CMSIS V1.30</span> release</span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Directory structure updated to be aligned with CMSIS V1.30<br>
-                </span></li>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support
-for&nbsp;<b>STM32 Low-density Value line (STM32F100x4/6) and
-Medium-density Value line (STM32F100x8/B) devices</b>.&nbsp;</span><span style="font-size: 10pt;"><o:p></o:p></span></li>
-
-</ul>
-<ol style="margin-top: 0in;" start="2" type="1">
-<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">CMSIS Core Peripheral Access Layer</span></i></b></li></ol>
-            <ul>
-              <li><b><i><span style="font-size: 10pt; font-family: Verdana;"></span></i></b><span style="font-size: 10pt; font-family: Verdana;"> Refer to <a href="../../../CMSIS_changes.htm" target="_blank">CMSIS changes</a></span></li>
-            </ul>
-            <ol style="margin-top: 0in; list-style-type: decimal;" start="3">
-              <li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x CMSIS Device Peripheral Access Layer </span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>
-
-            </ol>
-
-            <ul style="margin-top: 0in;" type="disc">
-
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer Header File:</span> <span style="font-weight: bold; font-style: italic;">stm32f10x.h</span></span><br>
-              </li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Update
-the stm32f10x.h file to support new Value line devices features: CEC
-peripheral, new General purpose timers TIM15, TIM16 and TIM17.</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Peripherals Bits definitions updated to be in line with Value line devices available features.<br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">HSE_Value,
-HSI_Value and HSEStartup_TimeOut changed to upper case: HSE_VALUE,
-HSI_VALUE and HSE_STARTUP_TIMEOUT. Old names are kept for legacy
-purposes.<br>
-                  </span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Cortex-M3 Device Peripheral Access Layer System Files:</span> <span style="font-weight: bold; font-style: italic;">system_stm32f10x.h and system_stm32f10x.c</span></span><br>
-                <span style="font-size: 10pt; font-family: Verdana;"></span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemFrequency variable name changed to SystemCoreClock</span><br>
-                  <span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"></span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Default
-                  </span></span><span style="font-size: 10pt; font-family: Verdana;">SystemCoreClock</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> is changed to 24MHz when Value line devices are selected and to 72MHz on other devices.</span></span><span style="font-size: 10pt;"><o:p></o:p></span><span style="font-size: 10pt; font-family: Verdana;"> <br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">All while(1) loop were removed from all clock setting functions. User has to handle the HSE startup failure.<br>
-                  </span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Additional function <span style="font-weight: bold; font-style: italic;">void SystemCoreClockUpdate (void)</span> is provided.<br>
-                  </span></li>
-              </ul>
-              <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;">STM32F10x CMSIS Startup files:</span> <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_xx.s</span></span></li>
-              <ul>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new
-startup files for STM32 Low-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_ld_vl.s</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new startup
-files for STM32 Medium-density Value line devices:
-                  <span style="font-weight: bold; font-style: italic;">startup_stm32f10x_md_vl.s</span></span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SystemInit() function is called from startup file (startup_stm32f10x_xx.s) before to branch to application main.<br>
-To reconfigure the default setting of SystemInit() function, refer to system_stm32f10x.c file <br>
-</span></li>
-                <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GNU startup file for Low density devices (startup_stm32f10x_ld.s) is updated to fix compilation errors.<br>
-</span></li>
-              </ul>
-
-            </ul>
-
-<ul style="margin-top: 0in;" type="disc">
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The
-enclosed firmware and all the related documentation are not covered by
-a License Agreement, if you need such License you can contact your
-local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE
-PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
-WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
-SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
-ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
-CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
-CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
-THEIR PRODUCTS. <o:p></o:p></span></b></p>
-<p class="MsoNormal"><span style="color: black;"><o:p>&nbsp;</o:p></span></p>
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
-complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers
-visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p>&nbsp;</o:p></p>
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