Merge pull request #5049 from StackRyan/mm32_dev

[bsp]add mindmotion MM32F103xx BSP.

bsp/mm32f103x/.config

@@ -0,0 +1,634 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_ASM_MEMCPY is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_PRINTF_LONGLONG is not set
+CONFIG_RT_VER_NUM=0x40004
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_RT_USING_MSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=1024
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+
+#
+# system packages
+#
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_WCWIDTH is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_ALI_LINKKIT is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+# CONFIG_PKG_USING_MCF is not set
+# CONFIG_PKG_USING_URPC is not set
+# CONFIG_PKG_USING_DCM is not set
+# CONFIG_PKG_USING_EMQ is not set
+# CONFIG_PKG_USING_CFGM is not set
+# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
+# CONFIG_PKG_USING_SMODULE is not set
+# CONFIG_PKG_USING_SNFD is not set
+# CONFIG_PKG_USING_UDBD is not set
+# CONFIG_PKG_USING_BENCHMARK is not set
+# CONFIG_PKG_USING_UBJSON is not set
+# CONFIG_PKG_USING_DATATYPE is not set
+# CONFIG_PKG_USING_FASTFS is not set
+# CONFIG_PKG_USING_RIL is not set
+# CONFIG_PKG_USING_WATCH_DCM_SVC is not set
+# CONFIG_PKG_USING_WATCH_APP_FWK is not set
+# CONFIG_PKG_USING_GUI_TEST is not set
+# CONFIG_PKG_USING_PMEM is not set
+# CONFIG_PKG_USING_LWRDP is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+
+#
+# GPIO Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+CONFIG_SOC_MM32L373=y

bsp/mm32f103x/.ignore_format.yml

@@ -0,0 +1,4 @@
+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- Libraries

bsp/mm32f103x/Kconfig

@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "drivers/Kconfig"
+
+config SOC_MM32L373
+    bool 
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision:    V1.4.4
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision:    V1.4.4
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/arm_math.h

@@ -0,0 +1,7435 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        12. March 2014
+* $Revision:    V1.4.4
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   * ------------
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * Using the Library
+   * ------------
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * Examples
+   * --------
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Toolchain Support
+   * ------------
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Building the Library
+   * ------------
+   *
+   * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM_math.uvproj
+   *
+   *
+   * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+   *
+   * Pre-processor Macros
+   * ------------
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <hr>
+   * CMSIS-DSP in ARM::CMSIS Pack
+   * -----------------------------
+   *
+   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
+   * |File/Folder                   |Content                                                                 |
+   * |------------------------------|------------------------------------------------------------------------|
+   * |\b CMSIS\\Documentation\\DSP  | This documentation                                                     |
+   * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
+   * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
+   * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
+   *
+   * <hr>
+   * Revision History of CMSIS-DSP
+   * ------------
+   * Please refer to \ref ChangeLog_pg.
+   *
+   * Copyright Notice
+   * ------------
+   *
+   * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31           (0x100)
+#define DELTA_Q15           0x5
+#define INDEX_MASK          0x0000003F
+#ifndef PI
+#define PI                  3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE  512
+#define FAST_MATH_Q31_SHIFT   (32 - 10)
+#define FAST_MATH_Q15_SHIFT   (16 - 10)
+#define CONTROLLER_Q31_SHIFT  (32 - 9)
+#define TABLE_SIZE  256
+#define TABLE_SPACING_Q31      0x400000
+#define TABLE_SPACING_Q15      0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING           0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined  (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE   */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__          /* Cosmic */
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+        (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+        (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+static __INLINE q31_t clip_q63_to_q31(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+static __INLINE q15_t clip_q63_to_q15(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+static __INLINE q7_t clip_q31_to_q7(
+    q31_t x)
+{
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+static __INLINE q15_t clip_q31_to_q15(
+    q31_t x)
+{
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+static __INLINE q63_t mult32x64(
+    q63_t x,
+    q31_t y)
+{
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+}
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+static __INLINE uint32_t __CLZ(
+    q31_t data);
+
+
+static __INLINE uint32_t __CLZ(
+    q31_t data)
+{
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0) {
+        count += 1u;
+        mask = mask >> 1u;
+    }
+
+    return (count);
+
+}
+
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+static __INLINE uint32_t arm_recip_q31(
+    q31_t in,
+    q31_t* dst,
+    q31_t* pRecipTable)
+{
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0) {
+        signBits = __CLZ(in) - 1;
+    }
+    else {
+        signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+        tempVal = 0x7FFFFFFF - tempVal;
+        /*      1.31 with exp 1 */
+        //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+        out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+}
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+static __INLINE uint32_t arm_recip_q15(
+    q15_t in,
+    q15_t* dst,
+    q15_t* pRecipTable)
+{
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0) {
+        signBits = __CLZ(in) - 17;
+    }
+    else {
+        signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++) {
+        tempVal = (q15_t) (((q31_t) in * out) >> 15);
+        tempVal = 0x7FFF - tempVal;
+        /*      1.15 with exp 1 */
+        out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+static __INLINE q31_t __SSAT(
+    q31_t x,
+    uint32_t y)
+{
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++) {
+        posMax = posMax * 2;
+    }
+
+    if(x > 0) {
+        posMax = (posMax - 1);
+
+        if(x > posMax) {
+            x = posMax;
+        }
+    }
+    else {
+        negMin = -posMax;
+
+        if(x < negMin) {
+            x = negMin;
+        }
+    }
+    return (x);
+
+
+}
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD8(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+        (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+        (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB8(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+        (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                0x000000FF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SHADD16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SHSUB16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+}
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+static __INLINE q31_t __QASX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum = 0;
+
+    sum =
+        ((sum +
+          clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+        clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+static __INLINE q31_t __SHASX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+static __INLINE q31_t __QSAX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum = 0;
+
+    sum =
+        ((sum +
+          clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+        clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+static __INLINE q31_t __SHSAX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (q15_t) x;
+    s = (q15_t) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUSDX(
+    q31_t x,
+    q31_t y)
+{
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUADX(
+    q31_t x,
+    q31_t y)
+{
+
+    return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+                     ((q15_t) (x >> 16) * (q15_t) y)));
+}
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD(
+    q31_t x,
+    q31_t y)
+{
+    return clip_q63_to_q31((q63_t) x + y);
+}
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB(
+    q31_t x,
+    q31_t y)
+{
+    return clip_q63_to_q31((q63_t) x - y);
+}
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLAD(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+}
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLADX(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+}
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLSDX(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+            ((q15_t) x * (q15_t) (y >> 16)));
+}
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+static __INLINE q63_t __SMLALD(
+    q31_t x,
+    q31_t y,
+    q63_t sum)
+{
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+            ((q15_t) x * (q15_t) y));
+}
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+static __INLINE q63_t __SMLALDX(
+    q31_t x,
+    q31_t y,
+    q63_t sum)
+{
+
+    return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+           ((q15_t) x * (q15_t) (y >> 16));
+}
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUAD(
+    q31_t x,
+    q31_t y)
+{
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUSD(
+    q31_t x,
+    q31_t y)
+{
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SXTB16(
+    q31_t x)
+{
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+}
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q7(
+    const arm_fir_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps  Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+void arm_fir_init_q7(
+    arm_fir_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_fast_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+arm_status arm_fir_init_q15(
+    arm_fir_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_fast_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in]   numTaps  Number of filter coefficients in the filter.
+ * @param[in]   *pCoeffs points to the filter coefficients.
+ * @param[in]   *pState points to the state buffer.
+ * @param[in]   blockSize number of samples that are processed at a time.
+ * @return      none.
+ */
+void arm_fir_init_q31(
+    arm_fir_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_f32(
+    const arm_fir_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in]   numTaps  Number of filter coefficients in the filter.
+ * @param[in]   *pCoeffs points to the filter coefficients.
+ * @param[in]   *pState points to the state buffer.
+ * @param[in]   blockSize number of samples that are processed at a time.
+ * @return      none.
+ */
+void arm_fir_init_f32(
+    arm_fir_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t* pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t* pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_casd_df1_inst_q15;
+
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+} arm_biquad_casd_df1_inst_f32;
+
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+    arm_biquad_casd_df1_inst_q15* S,
+    uint8_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]     numStages      number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+    arm_biquad_casd_df1_inst_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int8_t postShift);
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_f32(
+    const arm_biquad_casd_df1_inst_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+    arm_biquad_casd_df1_inst_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float64_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t* pData;         /**< points to the data of the matrix. */
+
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t* pData;         /**< points to the data of the matrix. */
+
+} arm_matrix_instance_q31;
+
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_cmplx_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15, complex,  matrix multiplication.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_cmplx_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pScratch);
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_cmplx_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_f32(
+    const arm_matrix_instance_f32* pSrc,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+    const arm_matrix_instance_q15* pSrc,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+    const arm_matrix_instance_q31* pSrc,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @param[in]        *pState points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA  points to the first input matrix structure
+ * @param[in]       *pSrcB  points to the second input matrix structure
+ * @param[out]      *pDst   points to output matrix structure
+ * @param[in]         *pState points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[in]  scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_f32(
+    const arm_matrix_instance_f32* pSrc,
+    float32_t scale,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_q15(
+    const arm_matrix_instance_q15* pSrc,
+    q15_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_q31(
+    const arm_matrix_instance_q31* pSrc,
+    q31_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief  Q31 matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_q31(
+    arm_matrix_instance_q31* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q31_t* pData);
+
+/**
+ * @brief  Q15 matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_q15(
+    arm_matrix_instance_q15* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q15_t* pData);
+
+/**
+ * @brief  Floating-point matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_f32(
+    arm_matrix_instance_f32* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief  Initialization function for the floating-point PID Control.
+ * @param[in,out] *S      points to an instance of the PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_f32(
+    arm_pid_instance_f32* S,
+    int32_t resetStateFlag);
+
+/**
+ * @brief  Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+void arm_pid_reset_f32(
+    arm_pid_instance_f32* S);
+
+
+/**
+ * @brief  Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_q31(
+    arm_pid_instance_q31* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+void arm_pid_reset_q31(
+    arm_pid_instance_q31* S);
+
+/**
+ * @brief  Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_q15(
+    arm_pid_instance_q15* S,
+    int32_t resetStateFlag);
+
+/**
+ * @brief  Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+void arm_pid_reset_q15(
+    arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t* pYData;          /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t* pData;   /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t* pData;                /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst  points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst  points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+
+
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+    arm_cfft_radix2_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+    const arm_cfft_radix2_instance_q15* S,
+    q15_t* pSrc);
+
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+    arm_cfft_radix4_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+    const arm_cfft_radix4_instance_q15* S,
+    q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+    arm_cfft_radix2_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+    const arm_cfft_radix2_instance_q31* S,
+    q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+    const arm_cfft_radix4_instance_q31* S,
+    q31_t* pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+    arm_cfft_radix4_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+    arm_cfft_radix2_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+    const arm_cfft_radix2_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+    arm_cfft_radix4_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+    const arm_cfft_radix4_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q15_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+    const arm_cfft_instance_q15* S,
+    q15_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const q31_t* pTwiddle;             /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+    const arm_cfft_instance_q31* S,
+    q31_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+    const arm_cfft_instance_f32* S,
+    float32_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q15* pCfft;       /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    const arm_cfft_instance_q31* pCfft;         /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31* S,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+    const arm_rfft_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+    arm_rfft_instance_f32* S,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+    const arm_rfft_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+    float32_t* pTwiddleRFFT;                    /**< Twiddle factors real stage  */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+    arm_rfft_fast_instance_f32* S,
+    uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+    arm_rfft_fast_instance_f32* S,
+    float32_t* p, float32_t* pOut,
+    uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t* pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t* pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+/**
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_f32(
+    arm_dct4_instance_f32* S,
+    arm_rfft_instance_f32* S_RFFT,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    float32_t normalize);
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+    const arm_dct4_instance_f32* S,
+    float32_t* pState,
+    float32_t* pInlineBuffer);
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t* pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t* pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+/**
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_q31(
+    arm_dct4_instance_q31* S,
+    arm_rfft_instance_q31* S_RFFT,
+    arm_cfft_radix4_instance_q31* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q31_t normalize);
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_q31(
+    const arm_dct4_instance_q31* S,
+    q31_t* pState,
+    q31_t* pInlineBuffer);
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t* pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t* pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+/**
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_q15(
+    arm_dct4_instance_q15* S,
+    arm_rfft_instance_q15* S_RFFT,
+    arm_cfft_radix4_instance_q15* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q15_t normalize);
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_q15(
+    const arm_dct4_instance_q15* S,
+    q15_t* pState,
+    q15_t* pInlineBuffer);
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scale scale factor to be applied
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_f32(
+    float32_t* pSrc,
+    float32_t scale,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q7(
+    q7_t* pSrc,
+    q7_t scaleFract,
+    int8_t shift,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q15(
+    q15_t* pSrc,
+    q15_t scaleFract,
+    int8_t shift,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q31(
+    q31_t* pSrc,
+    q31_t scaleFract,
+    int8_t shift,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t blockSize,
+    float32_t* result);
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    uint32_t blockSize,
+    q31_t* result);
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+/**
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q7(
+    q7_t* pSrc,
+    int8_t shiftBits,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q15(
+    q15_t* pSrc,
+    int8_t shiftBits,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q31(
+    q31_t* pSrc,
+    int8_t shiftBits,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a floating-point vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_f32(
+    float32_t* pSrc,
+    float32_t offset,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q7 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q7(
+    q7_t* pSrc,
+    q7_t offset,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q15 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q15(
+    q15_t* pSrc,
+    q15_t offset,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q31 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q31(
+    q31_t* pSrc,
+    q31_t offset,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a floating-point vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q7 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q15 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q31 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+/**
+ * @brief  Copies the elements of a floating-point vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q7 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q15 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q31 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+/**
+ * @brief  Fills a constant value into a floating-point vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_f32(
+    float32_t value,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q7 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q7(
+    q7_t value,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q15 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q15(
+    q15_t value,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q31 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q31(
+    q31_t value,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+void arm_conv_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+void arm_conv_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] *pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] *pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+* @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+* @return none.
+*/
+
+void arm_conv_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+/**
+* @brief Partial convolution of Q15 sequences.
+* @param[in]       *pSrcA points to the first input sequence.
+* @param[in]       srcALen length of the first input sequence.
+* @param[in]       *pSrcB points to the second input sequence.
+* @param[in]       srcBLen length of the second input sequence.
+* @param[out]      *pDst points to the block of output data
+* @param[in]       firstIndex is the first output sample to start with.
+* @param[in]       numPoints is the number of output points to be computed.
+* @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+* @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+*/
+
+arm_status arm_conv_partial_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+arm_status arm_conv_partial_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+arm_status arm_conv_partial_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t* pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t* pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t* pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+} arm_fir_decimate_instance_f32;
+
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_f32(
+    const arm_fir_decimate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+    arm_fir_decimate_instance_f32* S,
+    uint16_t numTaps,
+    uint8_t M,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_fast_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+    arm_fir_decimate_instance_q15* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_q31(
+    const arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_fast_q31(
+    arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+    arm_fir_decimate_instance_q31* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t* pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t* pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t* pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t* pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_q15(
+    const arm_fir_interpolate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+    arm_fir_interpolate_instance_q15* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_q31(
+    const arm_fir_interpolate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+    arm_fir_interpolate_instance_q31* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_f32(
+    const arm_fir_interpolate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+    arm_fir_interpolate_instance_f32* S,
+    uint8_t L,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+    const arm_biquad_cas_df1_32x64_ins_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+    arm_biquad_cas_df1_32x64_ins_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q63_t* pState,
+    uint8_t postShift);
+
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float64_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float64_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  *S        points to an instance of the filter data structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cascade_df2T_f32(
+    const arm_biquad_cascade_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in]  *S        points to an instance of the filter data structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cascade_stereo_df2T_f32(
+    const arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  *S        points to an instance of the filter data structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cascade_df2T_f64(
+    const arm_biquad_cascade_df2T_instance_f64* S,
+    float64_t* pSrc,
+    float64_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+    arm_biquad_cascade_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+    arm_biquad_cascade_stereo_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+    arm_biquad_cascade_df2T_instance_f64* S,
+    uint8_t numStages,
+    float64_t* pCoeffs,
+    float64_t* pState);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t* pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t* pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t* pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t* pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q15(
+    arm_fir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_lattice_q15(
+    const arm_fir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.   The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q31(
+    arm_fir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q31(
+    const arm_fir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+    arm_fir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_f32(
+    const arm_fir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t* pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t* pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t* pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t* pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t* pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t* pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t* pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t* pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t* pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_f32(
+    const arm_iir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+    arm_iir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pkCoeffs,
+    float32_t* pvCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_q31(
+    const arm_iir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q31(
+    arm_iir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pkCoeffs,
+    q31_t* pvCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_q15(
+    const arm_iir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q15(
+    arm_iir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pkCoeffs,
+    q15_t* pvCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_lms_f32(
+    const arm_lms_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_init_f32(
+    arm_lms_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return    none.
+ */
+
+void arm_lms_init_q15(
+    arm_lms_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_q15(
+    const arm_lms_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+} arm_lms_instance_q31;
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_lms_q31(
+    const arm_lms_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_init_q31(
+    arm_lms_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_f32(
+    arm_lms_norm_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_init_f32(
+    arm_lms_norm_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_q31(
+    arm_lms_norm_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_norm_init_q31(
+    arm_lms_norm_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t* recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_q15(
+    arm_lms_norm_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_norm_init_q15(
+    arm_lms_norm_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in] *pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] *pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @return none.
+*/
+void arm_correlate_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+void arm_correlate_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+
+/**
+  * @brief Correlation of Q7 sequences.
+  * @param[in] *pSrcA points to the first input sequence.
+  * @param[in] srcALen length of the first input sequence.
+  * @param[in] *pSrcB points to the second input sequence.
+  * @param[in] srcBLen length of the second input sequence.
+  * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+  * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+  * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+  * @return none.
+  */
+
+void arm_correlate_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+    arm_fir_sparse_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    float32_t* pScratchIn,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_f32(
+    arm_fir_sparse_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q31(
+    arm_fir_sparse_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    q31_t* pScratchIn,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q31(
+    arm_fir_sparse_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q15(
+    arm_fir_sparse_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    q15_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q15(
+    arm_fir_sparse_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q7(
+    arm_fir_sparse_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    q7_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q7(
+    arm_fir_sparse_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/*
+ * @brief  Floating-point sin_cos function.
+ * @param[in]  theta    input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+void arm_sin_cos_f32(
+    float32_t theta,
+    float32_t* pSinVal,
+    float32_t* pCcosVal);
+
+/*
+ * @brief  Q31 sin_cos function.
+ * @param[in]  theta    scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+void arm_sin_cos_q31(
+    q31_t theta,
+    q31_t* pSinVal,
+    q31_t* pCosVal);
+
+
+/**
+ * @brief  Floating-point complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+
+/**
+ * @brief  Floating-point complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+  * @ingroup groupController
+  */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd  </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+static __INLINE float32_t arm_pid_f32(
+    arm_pid_instance_f32* S,
+    float32_t in)
+{
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+static __INLINE q31_t arm_pid_q31(
+    arm_pid_instance_q31* S,
+    q31_t in)
+{
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+static __INLINE q15_t arm_pid_q15(
+    arm_pid_instance_q15* S,
+    q15_t in)
+{
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE* vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) * vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+arm_status arm_mat_inverse_f32(
+    const arm_matrix_instance_f32* src,
+    arm_matrix_instance_f32* dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+arm_status arm_mat_inverse_f64(
+    const arm_matrix_instance_f64* src,
+    arm_matrix_instance_f64* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief  Floating-point Clarke transform
+ * @param[in]       Ia       input three-phase coordinate <code>a</code>
+ * @param[in]       Ib       input three-phase coordinate <code>b</code>
+ * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+static __INLINE void arm_clarke_f32(
+    float32_t Ia,
+    float32_t Ib,
+    float32_t* pIalpha,
+    float32_t* pIbeta)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+        ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+}
+
+/**
+ * @brief  Clarke transform for Q31 version
+ * @param[in]       Ia       input three-phase coordinate <code>a</code>
+ * @param[in]       Ib       input three-phase coordinate <code>b</code>
+ * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+static __INLINE void arm_clarke_q31(
+    q31_t Ia,
+    q31_t Ib,
+    q31_t* pIalpha,
+    q31_t* pIbeta)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in]  *pSrc     input pointer
+ * @param[out]  *pDst    output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_q7_to_q31(
+    q7_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Clarke transform
+* @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+* @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+* @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+* @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+* @return none.
+*/
+
+
+static __INLINE void arm_inv_clarke_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pIa,
+    float32_t* pIb)
+{
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 * Ibeta;
+
+}
+
+/**
+ * @brief  Inverse Clarke transform for Q31 version
+ * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+ * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+ * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+ * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+static __INLINE void arm_inv_clarke_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pIa,
+    q31_t* pIb)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in]  *pSrc     input pointer
+ * @param[out] *pDst     output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_q7_to_q15(
+    q7_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in]       Ialpha input two-phase vector coordinate alpha
+ * @param[in]       Ibeta  input two-phase vector coordinate beta
+ * @param[out]      *pId   points to output rotor reference frame d
+ * @param[out]      *pIq   points to output rotor reference frame q
+ * @param[in]       sinVal sine value of rotation angle theta
+ * @param[in]       cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+static __INLINE void arm_park_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pId,
+    float32_t* pIq,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+}
+
+/**
+ * @brief  Park transform for Q31 version
+ * @param[in]       Ialpha input two-phase vector coordinate alpha
+ * @param[in]       Ibeta  input two-phase vector coordinate beta
+ * @param[out]      *pId   points to output rotor reference frame d
+ * @param[out]      *pIq   points to output rotor reference frame q
+ * @param[in]       sinVal sine value of rotation angle theta
+ * @param[in]       cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+static __INLINE void arm_park_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pId,
+    q31_t* pIq,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q7_to_float(
+    q7_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Park transform
+* @param[in]       Id        input coordinate of rotor reference frame d
+* @param[in]       Iq        input coordinate of rotor reference frame q
+* @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+* @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+* @param[in]       sinVal    sine value of rotation angle theta
+* @param[in]       cosVal    cosine value of rotation angle theta
+* @return none.
+*/
+
+static __INLINE void arm_inv_park_f32(
+    float32_t Id,
+    float32_t Iq,
+    float32_t* pIalpha,
+    float32_t* pIbeta,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+}
+
+
+/**
+ * @brief  Inverse Park transform for   Q31 version
+ * @param[in]       Id        input coordinate of rotor reference frame d
+ * @param[in]       Iq        input coordinate of rotor reference frame q
+ * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+ * @param[in]       sinVal    sine value of rotation angle theta
+ * @param[in]       cosVal    cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+static __INLINE void arm_inv_park_q31(
+    q31_t Id,
+    q31_t Iq,
+    q31_t* pIalpha,
+    q31_t* pIbeta,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_float(
+    q31_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A  Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+static __INLINE float32_t arm_linear_interp_f32(
+    arm_linear_interp_instance_f32* S,
+    float32_t x)
+{
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t* pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0) {
+        /* Iniatilize output for below specified range as least output value of table */
+        y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues) {
+        /* Iniatilize output for above specified range as last output value of table */
+        y = pYData[S->nValues - 1];
+    }
+    else {
+        /* Calculation of nearest input values */
+        x0 = S->x1 + i * xSpacing;
+        x1 = S->x1 + (i + 1) * xSpacing;
+
+        /* Read of nearest output values */
+        y0 = pYData[i];
+        y1 = pYData[i + 1];
+
+        /* Calculation of output */
+        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+}
+
+/**
+*
+* @brief  Process function for the Q31 Linear Interpolation Function.
+* @param[in] *pYData  pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+
+
+static __INLINE q31_t arm_linear_interp_q31(
+    q31_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if(index < 0) {
+        return (pYData[0]);
+    }
+    else {
+
+        /* 20 bits for the fractional part */
+        /* shift left by 11 to keep fract in 1.31 format */
+        fract = (x & 0x000FFFFF) << 11;
+
+        /* Read two nearest output values from the index in 1.31(q31) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+        /* Convert y to 1.31 format */
+        return (y << 1u);
+
+    }
+
+}
+
+/**
+ *
+ * @brief  Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+static __INLINE q15_t arm_linear_interp_q15(
+    q15_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if(index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+        y = ((q63_t) y0 * (0xFFFFF - fract));
+
+        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+        y += ((q63_t) y1 * (fract));
+
+        /* convert y to 1.15 format */
+        return (y >> 20);
+    }
+
+
+}
+
+/**
+ *
+ * @brief  Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+static __INLINE q7_t arm_linear_interp_q7(
+    q7_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0) {
+        return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else {
+
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index and are in 1.7(q7) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+        y = ((y0 * (0xFFFFF - fract)));
+
+        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+        y += (y1 * fract);
+
+        /* convert y to 1.7(q7) format */
+        return (y >> 20u);
+
+    }
+
+}
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return  sin(x).
+ */
+
+float32_t arm_sin_f32(
+    float32_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ */
+
+q31_t arm_sin_q31(
+    q31_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ */
+
+q15_t arm_sin_q15(
+    q15_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return  cos(x).
+ */
+
+float32_t arm_cos_f32(
+    float32_t x);
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ */
+
+q31_t arm_cos_q31(
+    q31_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ */
+
+q15_t arm_cos_q15(
+    q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ *      x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ * </pre>
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief  Floating-point square root function.
+ * @param[in]  in     input value.
+ * @param[out] *pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+static __INLINE arm_status arm_sqrt_f32(
+    float32_t in,
+    float32_t* pOut)
+{
+    if(in > 0) {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+#else
+        *pOut = sqrtf(in);
+#endif
+
+        return (ARM_MATH_SUCCESS);
+    }
+    else {
+        *pOut = 0.0f;
+        return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out]  *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+    q31_t in,
+    q31_t* pOut);
+
+/**
+ * @brief  Q15 square root function.
+ * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out]  *pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+    q15_t in,
+    q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const int32_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+static __INLINE void arm_circularRead_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    int32_t* dst,
+    int32_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (int32_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value  */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+/**
+ * @brief Q15 Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q15_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q15_t* dst,
+    q15_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (q15_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q7_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q7_t* dst,
+    q7_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (q7_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Mean value of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_mean_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult);
+
+/**
+ * @brief  Mean value of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Mean value of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Mean value of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Floating-point complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t numSamples,
+    q31_t* realResult,
+    q31_t* imagResult);
+
+/**
+ * @brief  Q31 complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t numSamples,
+    q63_t* realResult,
+    q63_t* imagResult);
+
+/**
+ * @brief  Floating-point complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t numSamples,
+    float32_t* realResult,
+    float32_t* imagResult);
+
+/**
+ * @brief  Q15 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_q15(
+    q15_t* pSrcCmplx,
+    q15_t* pSrcReal,
+    q15_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_q31(
+    q31_t* pSrcCmplx,
+    q31_t* pSrcReal,
+    q31_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Floating-point complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+    float32_t* pSrcCmplx,
+    float32_t* pSrcReal,
+    float32_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Minimum value of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *result is output pointer
+ * @param[in]  index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* result,
+    uint32_t* index);
+
+/**
+ * @brief  Minimum value of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Minimum value of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+void arm_min_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Minimum value of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Q15 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Floating-point complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q31 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ */
+void arm_float_to_q31(
+    float32_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q15 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return          none
+ */
+void arm_float_to_q15(
+    float32_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q7 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return          none
+ */
+void arm_float_to_q7(
+    float32_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_q15(
+    q31_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_q7(
+    q31_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_float(
+    q15_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_q31(
+    q15_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_q7(
+    q15_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+ * <pre>
+ *     XF = floor(x)
+ *     YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+/**
+*
+* @brief  Floating-point bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+
+
+static __INLINE float32_t arm_bilinear_interp_f32(
+    const arm_bilinear_interp_instance_f32* S,
+    float32_t X,
+    float32_t Y)
+{
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t* pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+            || yIndex > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+*
+* @brief  Q31 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q31_t arm_bilinear_interp_q31(
+    arm_bilinear_interp_instance_q31* S,
+    q31_t X,
+    q31_t Y)
+{
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+}
+
+/**
+* @brief  Q15 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q15_t arm_bilinear_interp_q15(
+    arm_bilinear_interp_instance_q15* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+}
+
+/**
+* @brief  Q7 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q7_t arm_bilinear_interp_q7(
+    arm_bilinear_interp_instance_q7* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t* pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
+
+//Enter low optimization region - place directly above function definition
+#ifdef ARM_MATH_CM4
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("push")         \
+    _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+//Exit low optimization region - place directly after end of function definition
+#ifdef ARM_MATH_CM4
+#define LOW_OPTIMIZATION_EXIT \
+    _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+//Enter low optimization region - place directly above function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+
+//Enter low optimization region - place directly above function definition
+#ifdef ARM_MATH_CM4
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+//Exit low optimization region - place directly after end of function definition
+#define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+#ifdef ARM_MATH_CM4
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+//Exit low optimization region - place directly after end of function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+
+#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+#define LOW_OPTIMIZATION_EXIT
+
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)     // Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0.h

@@ -0,0 +1,704 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV               0x0000
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    uint32_t RESERVED0;
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED1;
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm0plus.h

@@ -0,0 +1,814 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV             0x0000
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED1;
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm3.h

@@ -0,0 +1,1638 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV               0x0200
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+    uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm4.h

@@ -0,0 +1,1789 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI_VFP_SUPPORT__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV               0x0000
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+    __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+    __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+    __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+    __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+#define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+#define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+    NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cm7.h

@@ -0,0 +1,2208 @@
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     01. September 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+  @{
+ */
+
+/*  CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM7_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM7_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x07)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI_VFP_SUPPORT__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cmSimd.h>                 /* Compiler specific SIMD Intrinsics               */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM7_REV
+#define __CM7_REV               0x0000
+#warning "__CM7_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __ICACHE_PRESENT
+#define __ICACHE_PRESENT          0
+#warning "__ICACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DCACHE_PRESENT
+#define __DCACHE_PRESENT          0
+#warning "__DCACHE_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __DTCM_PRESENT
+#define __DTCM_PRESENT            0
+#warning "__DTCM_PRESENT        not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          3
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x07)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x07)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHPR[12];                /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t ID_PFR[2];               /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t ID_DFR;                  /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ID_AFR;                  /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t ID_MFR[4];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ID_ISAR[5];              /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[1];
+    __I  uint32_t CLIDR;                   /*!< Offset: 0x078 (R/ )  Cache Level ID register                               */
+    __I  uint32_t CTR;                     /*!< Offset: 0x07C (R/ )  Cache Type register                                   */
+    __I  uint32_t CCSIDR;                  /*!< Offset: 0x080 (R/ )  Cache Size ID Register                                */
+    __IO uint32_t CSSELR;                  /*!< Offset: 0x084 (R/W)  Cache Size Selection Register                         */
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+    uint32_t RESERVED3[93];
+    __O  uint32_t STIR;                    /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register                 */
+    uint32_t RESERVED4[15];
+    __I  uint32_t MVFR0;                   /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0                      */
+    __I  uint32_t MVFR1;                   /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1                      */
+    __I  uint32_t MVFR2;                   /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 1                      */
+    uint32_t RESERVED5[1];
+    __O  uint32_t ICIALLU;                 /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU                         */
+    uint32_t RESERVED6[1];
+    __O  uint32_t ICIMVAU;                 /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU                      */
+    __O  uint32_t DCIMVAU;                 /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC                      */
+    __O  uint32_t DCISW;                   /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way                         */
+    __O  uint32_t DCCMVAU;                 /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU                           */
+    __O  uint32_t DCCMVAC;                 /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC                           */
+    __O  uint32_t DCCSW;                   /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way                              */
+    __O  uint32_t DCCIMVAC;                /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC            */
+    __O  uint32_t DCCISW;                  /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way               */
+    uint32_t RESERVED7[6];
+    __IO uint32_t ITCMCR;                  /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register   */
+    __IO uint32_t DTCMCR;                  /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers         */
+    __IO uint32_t AHBPCR;                  /*!< Offset: 0x298 (R/W)  AHBP Control Register                                 */
+    __IO uint32_t CACR;                    /*!< Offset: 0x29C (R/W)  L1 Cache Control Register                             */
+    __IO uint32_t AHBSCR;                  /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register                            */
+    uint32_t RESERVED8[1];
+    __IO uint32_t ABFSR;                   /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18                                            /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17                                            /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16                                            /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos                 27                                             /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24                                             /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_FORMAT_Pos)                  /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos                 29                                             /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24                                             /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20                                             /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16                                             /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0                                             /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL << SCB_CTR_IMINLINE_Pos)                /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos                  31                                             /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (7UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30                                             /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (7UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29                                             /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (7UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28                                             /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (7UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13                                             /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3                                             /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0                                             /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL << SCB_CCSIDR_LINESIZE_Pos)               /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos                0                                             /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (1UL << SCB_CSSELR_LEVEL_Pos)                    /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0                                             /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL << SCB_CSSELR_IND_Pos)                    /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos                  0                                             /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL << SCB_STIR_INTID_Pos)                /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos                   3                                             /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2                                             /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1FFUL << SCB_ITCMCR_RETEN_Pos)                /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1                                             /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1FFUL << SCB_ITCMCR_RMW_Pos)                  /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0                                             /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1FFUL << SCB_ITCMCR_EN_Pos)                   /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos                   3                                             /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2                                             /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1                                             /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0                                             /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL << SCB_DTCMCR_EN_Pos)                     /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos                   1                                             /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0                                             /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL << SCB_AHBPCR_EN_Pos)                     /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos                2                                             /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1                                             /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0                                             /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL << SCB_CACR_SIWT_Pos)                     /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos           11                                             /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2                                             /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0                                             /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL << SCB_AHBPCR_CTL_Pos)                    /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos              8                                             /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4                                             /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3                                             /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2                                             /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1                                             /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0                                             /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL << SCB_ABFSR_ITCM_Pos)                    /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12                                          /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11                                          /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10                                          /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+    uint32_t RESERVED3[981];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 (  W)  Lock Access Register                      */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R  )  Lock Status Register                      */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+    __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+    __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+    __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+    __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+    __I  uint32_t MVFR2;                   /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+#define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+#define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+    NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHPR[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  Cache functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_CacheFunctions Cache Functions
+    \brief      Functions that configure Instruction and Data cache.
+    @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+#define CCSIDR_LSSHIFT(x)      (((x) & SCB_CCSIDR_LINESIZE_Msk     ) >> SCB_CCSIDR_LINESIZE_Pos     )
+
+
+/** \brief Enable I-Cache
+
+    The function turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache(void)
+{
+#if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Disable I-Cache
+
+    The function turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache(void)
+{
+#if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
+    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+    The function invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache(void)
+{
+#if (__ICACHE_PRESENT == 1)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0;
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Enable D-Cache
+
+    The function turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache(void)
+{
+#if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+        int32_t tmpways = ways;
+        do {
+            sw = ((tmpways << wshift) | (sets << sshift));
+            SCB->DCISW = sw;
+        } while(tmpways--);
+    } while(sets--);
+    __DSB();
+
+    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Disable D-Cache
+
+    The function turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache(void)
+{
+#if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+
+    do {                                    // clean & invalidate D-Cache
+        int32_t tmpways = ways;
+        do {
+            sw = ((tmpways << wshift) | (sets << sshift));
+            SCB->DCCISW = sw;
+        } while(tmpways--);
+    } while(sets--);
+
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+    The function invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache(void)
+{
+#if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // invalidate D-Cache
+        int32_t tmpways = ways;
+        do {
+            sw = ((tmpways << wshift) | (sets << sshift));
+            SCB->DCISW = sw;
+        } while(tmpways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Clean D-Cache
+
+    The function cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache(void)
+{
+#if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean D-Cache
+        int32_t tmpways = ways;
+        do {
+            sw = ((tmpways << wshift) | (sets << sshift));
+            SCB->DCCSW = sw;
+        } while(tmpways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+    The function cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
+{
+#if (__DCACHE_PRESENT == 1)
+    uint32_t ccsidr, sshift, wshift, sw;
+    uint32_t sets, ways;
+
+    ccsidr  = SCB->CCSIDR;
+    sets    = CCSIDR_SETS(ccsidr);
+    sshift  = CCSIDR_LSSHIFT(ccsidr) + 4;
+    ways    = CCSIDR_WAYS(ccsidr);
+    wshift  = __CLZ(ways) & 0x1f;
+
+    __DSB();
+
+    do {                                    // clean & invalidate D-Cache
+        int32_t tmpways = ways;
+        do {
+            sw = ((tmpways << wshift) | (sets << sshift));
+            SCB->DCCISW = sw;
+        } while(tmpways--);
+    } while(sets--);
+
+    __DSB();
+    __ISB();
+#endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmFunc.h

@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    register uint32_t __regControl         __ASM("control");
+    return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+    register uint32_t __regAPSR          __ASM("apsr");
+    return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return(__regfpscr);
+#else
+    return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+    __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+    __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    uint32_t result;
+
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile ("");
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    __ASM volatile ("");
+    return(result);
+#else
+    return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile ("");
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+    __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmInstr.h

@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+    rev16 r0, r0
+    bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+    revsh r0, r0
+    bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+    rrx r0, r0
+    bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+    __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+    __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+    __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+    __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+    __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+    __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+    __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+    return __builtin_bswap32(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    return (short)__builtin_bswap16(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+    return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+    return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+    __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* addr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* addr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* addr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_cmSimd.h

@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+        ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+        ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+        ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+    __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+    __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+    __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+    union llreg_u {
+        uint32_t w32[2];
+        uint64_t w64;
+    } llr;
+    llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+    __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+    return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc000.h

@@ -0,0 +1,833 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                     __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV             0x0000
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED0[1];
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    uint32_t RESERVED1[154];
+    __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/core_sc300.h

@@ -0,0 +1,1618 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V4.00
+ * @date     22. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                     __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                 (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+#define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )      /* Cosmic */
+#if ( __CSMC__ & 0x400)     // FPU present for parser
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV               0x0000
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+    uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_common_tables.h

@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_const_structs.h

@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+    16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+    32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+    64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+    128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+    256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+    512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+    1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+    2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+};
+
+const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+    4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+};
+
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/arm_math.h

@@ -0,0 +1,7207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef  __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31           (0x100)
+#define DELTA_Q15           0x5
+#define INDEX_MASK          0x0000003F
+#ifndef PI
+#define PI                  3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE          256
+#define TABLE_SPACING_Q31   0x800000
+#define TABLE_SPACING_Q15   0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING           0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined  (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE   */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+        (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+        (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+static __INLINE q31_t clip_q63_to_q31(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+static __INLINE q15_t clip_q63_to_q15(
+    q63_t x)
+{
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+static __INLINE q7_t clip_q31_to_q7(
+    q31_t x)
+{
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+           ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+static __INLINE q15_t clip_q31_to_q15(
+    q31_t x)
+{
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+           ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+static __INLINE q63_t mult32x64(
+    q63_t x,
+    q31_t y)
+{
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+}
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+static __INLINE uint32_t __CLZ(
+    q31_t data);
+
+
+static __INLINE uint32_t __CLZ(
+    q31_t data)
+{
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0) {
+        count += 1u;
+        mask = mask >> 1u;
+    }
+
+    return (count);
+
+}
+
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+static __INLINE uint32_t arm_recip_q31(
+    q31_t in,
+    q31_t* dst,
+    q31_t* pRecipTable)
+{
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0) {
+        signBits = __CLZ(in) - 1;
+    }
+    else {
+        signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++) {
+        tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+        tempVal = 0x7FFFFFFF - tempVal;
+        /*      1.31 with exp 1 */
+        //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+        out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+}
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+static __INLINE uint32_t arm_recip_q15(
+    q15_t in,
+    q15_t* dst,
+    q15_t* pRecipTable)
+{
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0) {
+        signBits = __CLZ(in) - 17;
+    }
+    else {
+        signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++) {
+        tempVal = (q15_t) (((q31_t) in * out) >> 15);
+        tempVal = 0x7FFF - tempVal;
+        /*      1.15 with exp 1 */
+        out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+static __INLINE q31_t __SSAT(
+    q31_t x,
+    uint32_t y)
+{
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++) {
+        posMax = posMax * 2;
+    }
+
+    if(x > 0) {
+        posMax = (posMax - 1);
+
+        if(x > posMax) {
+            x = posMax;
+        }
+    }
+    else {
+        negMin = -posMax;
+
+        if(x < negMin) {
+            x = negMin;
+        }
+    }
+    return (x);
+
+
+}
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD8(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+        (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+        (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB8(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+        (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                0x000000FF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SHADD16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+}
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SHSUB16(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+}
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+static __INLINE q31_t __QASX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum = 0;
+
+    sum =
+        ((sum +
+          clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+        clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+static __INLINE q31_t __SHASX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+static __INLINE q31_t __QSAX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum = 0;
+
+    sum =
+        ((sum +
+          clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+        clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+static __INLINE q31_t __SHSAX(
+    q31_t x,
+    q31_t y)
+{
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+}
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUSDX(
+    q31_t x,
+    q31_t y)
+{
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUADX(
+    q31_t x,
+    q31_t y)
+{
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+}
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+static __INLINE q31_t __QADD(
+    q31_t x,
+    q31_t y)
+{
+    return clip_q63_to_q31((q63_t) x + y);
+}
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+static __INLINE q31_t __QSUB(
+    q31_t x,
+    q31_t y)
+{
+    return clip_q63_to_q31((q63_t) x - y);
+}
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLAD(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+}
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLADX(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+}
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+static __INLINE q31_t __SMLSDX(
+    q31_t x,
+    q31_t y,
+    q31_t sum)
+{
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+}
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+static __INLINE q63_t __SMLALD(
+    q31_t x,
+    q31_t y,
+    q63_t sum)
+{
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+}
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+static __INLINE q63_t __SMLALDX(
+    q31_t x,
+    q31_t y,
+    q63_t sum)
+{
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+           ((short) x * (short) (y >> 16));
+}
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUAD(
+    q31_t x,
+    q31_t y)
+{
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+static __INLINE q31_t __SMUSD(
+    q31_t x,
+    q31_t y)
+{
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+static __INLINE q31_t __SXTB16(
+    q31_t x)
+{
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+}
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t* pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q7(
+    const arm_fir_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps  Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+void arm_fir_init_q7(
+    arm_fir_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_fast_q15(
+    const arm_fir_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+arm_status arm_fir_init_q15(
+    arm_fir_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_fast_q31(
+    const arm_fir_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in]   numTaps  Number of filter coefficients in the filter.
+ * @param[in]   *pCoeffs points to the filter coefficients.
+ * @param[in]   *pState points to the state buffer.
+ * @param[in]   blockSize number of samples that are processed at a time.
+ * @return      none.
+ */
+void arm_fir_init_q31(
+    arm_fir_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_f32(
+    const arm_fir_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in]   numTaps  Number of filter coefficients in the filter.
+ * @param[in]   *pCoeffs points to the filter coefficients.
+ * @param[in]   *pState points to the state buffer.
+ * @param[in]   blockSize number of samples that are processed at a time.
+ * @return      none.
+ */
+void arm_fir_init_f32(
+    arm_fir_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t* pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t* pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_casd_df1_inst_q15;
+
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t* pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t* pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+} arm_biquad_casd_df1_inst_f32;
+
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+    arm_biquad_casd_df1_inst_q15* S,
+    uint8_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+    const arm_biquad_casd_df1_inst_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+    const arm_biquad_casd_df1_inst_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+ * @param[in]     numStages      number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+    arm_biquad_casd_df1_inst_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int8_t postShift);
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]  *pSrc      points to the block of input data.
+ * @param[out] *pDst      points to the block of output data.
+ * @param[in]  blockSize  number of samples to process.
+ * @return     none.
+ */
+
+void arm_biquad_cascade_df1_f32(
+    const arm_biquad_casd_df1_inst_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+    arm_biquad_casd_df1_inst_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t* pData;     /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t* pData;         /**< points to the data of the matrix. */
+
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+typedef struct {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t* pData;         /**< points to the data of the matrix. */
+
+} arm_matrix_instance_q31;
+
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_f32(
+    const arm_matrix_instance_f32* pSrc,
+    arm_matrix_instance_f32* pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+    const arm_matrix_instance_q15* pSrc,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return  The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+    const arm_matrix_instance_q31* pSrc,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @param[in]         *pState points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA  points to the first input matrix structure
+ * @param[in]       *pSrcB  points to the second input matrix structure
+ * @param[out]      *pDst   points to output matrix structure
+ * @param[in]         *pState points to the array for storing intermediate results
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst,
+    q15_t* pState);
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+    const arm_matrix_instance_f32* pSrcA,
+    const arm_matrix_instance_f32* pSrcB,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_q15(
+    const arm_matrix_instance_q15* pSrcA,
+    const arm_matrix_instance_q15* pSrcB,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in]       *pSrcA points to the first input matrix structure
+ * @param[in]       *pSrcB points to the second input matrix structure
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_q31(
+    const arm_matrix_instance_q31* pSrcA,
+    const arm_matrix_instance_q31* pSrcB,
+    arm_matrix_instance_q31* pDst);
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in]  *pSrc points to the input matrix
+ * @param[in]  scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_f32(
+    const arm_matrix_instance_f32* pSrc,
+    float32_t scale,
+    arm_matrix_instance_f32* pDst);
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_q15(
+    const arm_matrix_instance_q15* pSrc,
+    q15_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q15* pDst);
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in]       *pSrc points to input matrix
+ * @param[in]       scaleFract fractional portion of the scale factor
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to output matrix structure
+ * @return     The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_scale_q31(
+    const arm_matrix_instance_q31* pSrc,
+    q31_t scaleFract,
+    int32_t shift,
+    arm_matrix_instance_q31* pDst);
+
+
+/**
+ * @brief  Q31 matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_q31(
+    arm_matrix_instance_q31* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q31_t* pData);
+
+/**
+ * @brief  Q15 matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_q15(
+    arm_matrix_instance_q15* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    q15_t* pData);
+
+/**
+ * @brief  Floating-point matrix initialization.
+ * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+ * @param[in]     nRows          number of rows in the matrix.
+ * @param[in]     nColumns       number of columns in the matrix.
+ * @param[in]     *pData           points to the matrix data array.
+ * @return        none
+ */
+
+void arm_mat_init_f32(
+    arm_matrix_instance_f32* S,
+    uint16_t nRows,
+    uint16_t nColumns,
+    float32_t* pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief  Initialization function for the floating-point PID Control.
+ * @param[in,out] *S      points to an instance of the PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_f32(
+    arm_pid_instance_f32* S,
+    int32_t resetStateFlag);
+
+/**
+ * @brief  Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+void arm_pid_reset_f32(
+    arm_pid_instance_f32* S);
+
+
+/**
+ * @brief  Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_q31(
+    arm_pid_instance_q31* S,
+    int32_t resetStateFlag);
+
+
+/**
+ * @brief  Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+void arm_pid_reset_q31(
+    arm_pid_instance_q31* S);
+
+/**
+ * @brief  Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+void arm_pid_init_q15(
+    arm_pid_instance_q15* S,
+    int32_t resetStateFlag);
+
+/**
+ * @brief  Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+void arm_pid_reset_q15(
+    arm_pid_instance_q15* S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t* pYData;          /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t* pData;   /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t* pData;       /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+
+typedef struct {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t* pData;                /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst  points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst  points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+
+
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+arm_status arm_cfft_radix2_init_q15(
+    arm_cfft_radix2_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+void arm_cfft_radix2_q15(
+    const arm_cfft_radix2_instance_q15* S,
+    q15_t* pSrc);
+
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+arm_status arm_cfft_radix4_init_q15(
+    arm_cfft_radix4_instance_q15* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+void arm_cfft_radix4_q15(
+    const arm_cfft_radix4_instance_q15* S,
+    q15_t* pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+arm_status arm_cfft_radix2_init_q31(
+    arm_cfft_radix2_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+void arm_cfft_radix2_q31(
+    const arm_cfft_radix2_instance_q31* S,
+    q31_t* pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t* pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t* pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+
+void arm_cfft_radix4_q31(
+    const arm_cfft_radix4_instance_q31* S,
+    q31_t* pSrc);
+
+arm_status arm_cfft_radix4_init_q31(
+    arm_cfft_radix4_instance_q31* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+    arm_cfft_radix2_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+    const arm_cfft_radix2_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t* pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t* pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+    arm_cfft_radix4_instance_f32* S,
+    uint16_t fftLen,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+    const arm_cfft_radix4_instance_f32* S,
+    float32_t* pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+typedef struct {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t* pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t* pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+    const arm_cfft_instance_f32* S,
+    float32_t* p1,
+    uint8_t ifftFlag,
+    uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t* pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t* pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15* pCfft;          /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+    arm_rfft_instance_q15* S,
+    arm_cfft_radix4_instance_q15* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+    const arm_rfft_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t* pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t* pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31* pCfft;        /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+    arm_rfft_instance_q31* S,
+    arm_cfft_radix4_instance_q31* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+    const arm_rfft_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t* pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t* pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32* pCfft;        /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+    arm_rfft_instance_f32* S,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint32_t fftLenReal,
+    uint32_t ifftFlagR,
+    uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+    const arm_rfft_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+    float32_t* pTwiddleRFFT;                    /**< Twiddle factors real stage  */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+    arm_rfft_fast_instance_f32* S,
+    uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+    arm_rfft_fast_instance_f32* S,
+    float32_t* p, float32_t* pOut,
+    uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t* pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t* pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+/**
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_f32(
+    arm_dct4_instance_f32* S,
+    arm_rfft_instance_f32* S_RFFT,
+    arm_cfft_radix4_instance_f32* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    float32_t normalize);
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+    const arm_dct4_instance_f32* S,
+    float32_t* pState,
+    float32_t* pInlineBuffer);
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t* pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t* pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+/**
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_q31(
+    arm_dct4_instance_q31* S,
+    arm_rfft_instance_q31* S_RFFT,
+    arm_cfft_radix4_instance_q31* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q31_t normalize);
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_q31(
+    const arm_dct4_instance_q31* S,
+    q31_t* pState,
+    q31_t* pInlineBuffer);
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+typedef struct {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t* pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t* pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15* pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+/**
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in]     N          length of the DCT4.
+ * @param[in]     Nby2       half of the length of the DCT4.
+ * @param[in]     normalize  normalizing factor.
+ * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+arm_status arm_dct4_init_q15(
+    arm_dct4_instance_q15* S,
+    arm_rfft_instance_q15* S_RFFT,
+    arm_cfft_radix4_instance_q15* S_CFFT,
+    uint16_t N,
+    uint16_t Nby2,
+    q15_t normalize);
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+ * @param[in]       *pState        points to state buffer.
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_q15(
+    const arm_dct4_instance_q15* S,
+    q15_t* pState,
+    q15_t* pInlineBuffer);
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scale scale factor to be applied
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_f32(
+    float32_t* pSrc,
+    float32_t scale,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q7(
+    q7_t* pSrc,
+    q7_t scaleFract,
+    int8_t shift,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q15(
+    q15_t* pSrc,
+    q15_t scaleFract,
+    int8_t shift,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in]       *pSrc points to the input vector
+ * @param[in]       scaleFract fractional portion of the scale value
+ * @param[in]       shift number of bits to shift the result by
+ * @param[out]      *pDst points to the output vector
+ * @param[in]       blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_scale_q31(
+    q31_t* pSrc,
+    q31_t scaleFract,
+    int8_t shift,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[out]      *pDst points to the output buffer
+ * @param[in]       blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t blockSize,
+    float32_t* result);
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q7(
+    q7_t* pSrcA,
+    q7_t* pSrcB,
+    uint32_t blockSize,
+    q31_t* result);
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in]       *pSrcA points to the first input vector
+ * @param[in]       *pSrcB points to the second input vector
+ * @param[in]       blockSize number of samples in each vector
+ * @param[out]      *result output result returned here
+ * @return none.
+ */
+
+void arm_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t blockSize,
+    q63_t* result);
+
+/**
+ * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q7(
+    q7_t* pSrc,
+    int8_t shiftBits,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q15(
+    q15_t* pSrc,
+    int8_t shiftBits,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_shift_q31(
+    q31_t* pSrc,
+    int8_t shiftBits,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a floating-point vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_f32(
+    float32_t* pSrc,
+    float32_t offset,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q7 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q7(
+    q7_t* pSrc,
+    q7_t offset,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q15 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q15(
+    q15_t* pSrc,
+    q15_t offset,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Adds a constant offset to a Q31 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[in]  offset is the offset to be added
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_offset_q31(
+    q31_t* pSrc,
+    q31_t offset,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a floating-point vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q7 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q15 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Negates the elements of a Q31 vector.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+/**
+ * @brief  Copies the elements of a floating-point vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q7 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q7(
+    q7_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q15 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Copies the elements of a Q31 vector.
+ * @param[in]  *pSrc input pointer
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_copy_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+/**
+ * @brief  Fills a constant value into a floating-point vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_f32(
+    float32_t value,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q7 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q7(
+    q7_t value,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q15 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q15(
+    q15_t value,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Fills a constant value into a Q31 vector.
+ * @param[in]  value input value to be filled
+ * @param[out]  *pDst output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_fill_q31(
+    q31_t value,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+void arm_conv_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+void arm_conv_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] *pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] *pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+* @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+* @return none.
+*/
+
+void arm_conv_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+/**
+* @brief Partial convolution of Q15 sequences.
+* @param[in]       *pSrcA points to the first input sequence.
+* @param[in]       srcALen length of the first input sequence.
+* @param[in]       *pSrcB points to the second input sequence.
+* @param[in]       srcBLen length of the second input sequence.
+* @param[out]      *pDst points to the block of output data
+* @param[in]       firstIndex is the first output sample to start with.
+* @param[in]       numPoints is the number of output points to be computed.
+* @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+* @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+*/
+
+arm_status arm_conv_partial_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+arm_status arm_conv_partial_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in]       *pSrcA points to the first input sequence.
+ * @param[in]       srcALen length of the first input sequence.
+ * @param[in]       *pSrcB points to the second input sequence.
+ * @param[in]       srcBLen length of the second input sequence.
+ * @param[out]      *pDst points to the block of output data
+ * @param[in]       firstIndex is the first output sample to start with.
+ * @param[in]       numPoints is the number of output points to be computed.
+ * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+arm_status arm_conv_partial_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    uint32_t firstIndex,
+    uint32_t numPoints);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t* pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t* pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t* pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+typedef struct {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+} arm_fir_decimate_instance_f32;
+
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_f32(
+    const arm_fir_decimate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+    arm_fir_decimate_instance_f32* S,
+    uint16_t numTaps,
+    uint8_t M,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_fast_q15(
+    const arm_fir_decimate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+    arm_fir_decimate_instance_q15* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_q31(
+    const arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+void arm_fir_decimate_fast_q31(
+    arm_fir_decimate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps  number of coefficients in the filter.
+ * @param[in] M  decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+    arm_fir_decimate_instance_q31* S,
+    uint16_t numTaps,
+    uint8_t M,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t* pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t* pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t* pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t* pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+typedef struct {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t* pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t* pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_q15(
+    const arm_fir_interpolate_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+    arm_fir_interpolate_instance_q15* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_q31(
+    const arm_fir_interpolate_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+    arm_fir_interpolate_instance_q31* S,
+    uint8_t L,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc     points to the block of input data.
+ * @param[out] *pDst    points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_interpolate_f32(
+    const arm_fir_interpolate_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+ * @param[in]     L         upsample factor.
+ * @param[in]     numTaps   number of filter coefficients in the filter.
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+ * @param[in]     *pState   points to the state buffer.
+ * @param[in]     blockSize number of input samples to process per call.
+ * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+    arm_fir_interpolate_instance_f32* S,
+    uint8_t L,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t* pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t* pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+    const arm_biquad_cas_df1_32x64_ins_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+ * @return        none
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+    arm_biquad_cas_df1_32x64_ins_q31* S,
+    uint8_t numStages,
+    q31_t* pCoeffs,
+    q63_t* pState,
+    uint8_t postShift);
+
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+typedef struct {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t* pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t* pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in]  *S        points to an instance of the filter data structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_biquad_cascade_df2T_f32(
+    const arm_biquad_cascade_df2T_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S           points to an instance of the filter data structure.
+ * @param[in]     numStages    number of 2nd order stages in the filter.
+ * @param[in]     *pCoeffs     points to the filter coefficients.
+ * @param[in]     *pState      points to the state buffer.
+ * @return        none
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+    arm_biquad_cascade_df2T_instance_f32* S,
+    uint8_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t* pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t* pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t* pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t* pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+typedef struct {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t* pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t* pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q15(
+    arm_fir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pCoeffs,
+    q15_t* pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+void arm_fir_lattice_q15(
+    const arm_fir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.   The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q31(
+    arm_fir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pCoeffs,
+    q31_t* pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q31(
+    const arm_fir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+    arm_fir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pCoeffs,
+    float32_t* pState);
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+ * @param[in]  *pSrc     points to the block of input data.
+ * @param[out] *pDst     points to the block of output data
+ * @param[in]  blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_f32(
+    const arm_fir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t* pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t* pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t* pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t* pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t* pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t* pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t* pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t* pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t* pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_f32(
+    const arm_iir_lattice_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+    arm_iir_lattice_instance_f32* S,
+    uint16_t numStages,
+    float32_t* pkCoeffs,
+    float32_t* pvCoeffs,
+    float32_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_q31(
+    const arm_iir_lattice_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q31(
+    arm_iir_lattice_instance_q31* S,
+    uint16_t numStages,
+    q31_t* pkCoeffs,
+    q31_t* pvCoeffs,
+    q31_t* pState,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_q15(
+    const arm_iir_lattice_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q15(
+    arm_iir_lattice_instance_q15* S,
+    uint16_t numStages,
+    q15_t* pkCoeffs,
+    q15_t* pvCoeffs,
+    q15_t* pState,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t* pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_lms_f32(
+    const arm_lms_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_init_f32(
+    arm_lms_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return    none.
+ */
+
+void arm_lms_init_q15(
+    arm_lms_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_q15(
+    const arm_lms_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t* pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+} arm_lms_instance_q31;
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+ * @param[in]  *pSrc points to the block of input data.
+ * @param[in]  *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in]  blockSize number of samples to process.
+ * @return     none.
+ */
+
+void arm_lms_q31(
+    const arm_lms_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_init_q31(
+    arm_lms_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint32_t postShift);
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t* pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t* pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_f32(
+    arm_lms_norm_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pRef,
+    float32_t* pOut,
+    float32_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_init_f32(
+    arm_lms_norm_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    float32_t mu,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t* recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_q31(
+    arm_lms_norm_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pRef,
+    q31_t* pOut,
+    q31_t* pErr,
+    uint32_t blockSize);
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_norm_init_q31(
+    arm_lms_norm_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    q31_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t* pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t* pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t* recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_q15(
+    arm_lms_norm_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pRef,
+    q15_t* pOut,
+    q15_t* pErr,
+    uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps  number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+void arm_lms_norm_init_q15(
+    arm_lms_norm_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    q15_t mu,
+    uint32_t blockSize,
+    uint8_t postShift);
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+    float32_t* pSrcA,
+    uint32_t srcALen,
+    float32_t* pSrcB,
+    uint32_t srcBLen,
+    float32_t* pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in] *pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] *pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @return none.
+*/
+void arm_correlate_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_fast_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst);
+
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+void arm_correlate_fast_opt_q15(
+    q15_t* pSrcA,
+    uint32_t srcALen,
+    q15_t* pSrcB,
+    uint32_t srcBLen,
+    q15_t* pDst,
+    q15_t* pScratch);
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_fast_q31(
+    q31_t* pSrcA,
+    uint32_t srcALen,
+    q31_t* pSrcB,
+    uint32_t srcBLen,
+    q31_t* pDst);
+
+
+
+/**
+  * @brief Correlation of Q7 sequences.
+  * @param[in] *pSrcA points to the first input sequence.
+  * @param[in] srcALen length of the first input sequence.
+  * @param[in] *pSrcB points to the second input sequence.
+  * @param[in] srcBLen length of the second input sequence.
+  * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+  * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+  * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+  * @return none.
+  */
+
+void arm_correlate_opt_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst,
+    q15_t* pScratch1,
+    q15_t* pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_q7(
+    q7_t* pSrcA,
+    uint32_t srcALen,
+    q7_t* pSrcB,
+    uint32_t srcBLen,
+    q7_t* pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t* pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t* pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t* pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t* pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+typedef struct {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t* pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t* pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t* pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+    arm_fir_sparse_instance_f32* S,
+    float32_t* pSrc,
+    float32_t* pDst,
+    float32_t* pScratchIn,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_f32(
+    arm_fir_sparse_instance_f32* S,
+    uint16_t numTaps,
+    float32_t* pCoeffs,
+    float32_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+ * @param[in]  *pSrc       points to the block of input data.
+ * @param[out] *pDst       points to the block of output data
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize   number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q31(
+    arm_fir_sparse_instance_q31* S,
+    q31_t* pSrc,
+    q31_t* pDst,
+    q31_t* pScratchIn,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q31(
+    arm_fir_sparse_instance_q31* S,
+    uint16_t numTaps,
+    q31_t* pCoeffs,
+    q31_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q15(
+    arm_fir_sparse_instance_q15* S,
+    q15_t* pSrc,
+    q15_t* pDst,
+    q15_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q15(
+    arm_fir_sparse_instance_q15* S,
+    uint16_t numTaps,
+    q15_t* pCoeffs,
+    q15_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+ * @param[in]  *pSrc        points to the block of input data.
+ * @param[out] *pDst        points to the block of output data
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in]  blockSize    number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_q7(
+    arm_fir_sparse_instance_q7* S,
+    q7_t* pSrc,
+    q7_t* pDst,
+    q7_t* pScratchIn,
+    q31_t* pScratchOut,
+    uint32_t blockSize);
+
+/**
+ * @brief  Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.
+ * @param[in]     *pState    points to the state buffer.
+ * @param[in]     *pTapDelay points to the array of offset times.
+ * @param[in]     maxDelay   maximum offset time supported.
+ * @param[in]     blockSize  number of samples that will be processed per block.
+ * @return none
+ */
+
+void arm_fir_sparse_init_q7(
+    arm_fir_sparse_instance_q7* S,
+    uint16_t numTaps,
+    q7_t* pCoeffs,
+    q7_t* pState,
+    int32_t* pTapDelay,
+    uint16_t maxDelay,
+    uint32_t blockSize);
+
+
+/*
+ * @brief  Floating-point sin_cos function.
+ * @param[in]  theta    input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+void arm_sin_cos_f32(
+    float32_t theta,
+    float32_t* pSinVal,
+    float32_t* pCcosVal);
+
+/*
+ * @brief  Q31 sin_cos function.
+ * @param[in]  theta    scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+void arm_sin_cos_q31(
+    q31_t theta,
+    q31_t* pSinVal,
+    q31_t* pCosVal);
+
+
+/**
+ * @brief  Floating-point complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex conjugate.
+ * @param[in]  *pSrc points to the input vector
+ * @param[out]  *pDst points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+
+/**
+ * @brief  Floating-point complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex magnitude squared
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+
+/**
+  * @ingroup groupController
+  */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ *    A0 = Kp + Ki + Kd
+ *    A1 = (-Kp ) - (2 * Kd )
+ *    A2 = Kd  </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+static __INLINE float32_t arm_pid_f32(
+    arm_pid_instance_f32* S,
+    float32_t in)
+{
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+          (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+static __INLINE q31_t arm_pid_q31(
+    arm_pid_instance_q31* S,
+    q31_t in)
+{
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @brief  Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+static __INLINE q15_t arm_pid_q15(
+    arm_pid_instance_q15* S,
+    q15_t in)
+{
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE* vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) * vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in]  *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+arm_status arm_mat_inverse_f32(
+    const arm_matrix_instance_f32* src,
+    arm_matrix_instance_f32* dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief  Floating-point Clarke transform
+ * @param[in]       Ia       input three-phase coordinate <code>a</code>
+ * @param[in]       Ib       input three-phase coordinate <code>b</code>
+ * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+static __INLINE void arm_clarke_f32(
+    float32_t Ia,
+    float32_t Ib,
+    float32_t* pIalpha,
+    float32_t* pIbeta)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+        ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+}
+
+/**
+ * @brief  Clarke transform for Q31 version
+ * @param[in]       Ia       input three-phase coordinate <code>a</code>
+ * @param[in]       Ib       input three-phase coordinate <code>b</code>
+ * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+static __INLINE void arm_clarke_q31(
+    q31_t Ia,
+    q31_t Ib,
+    q31_t* pIalpha,
+    q31_t* pIbeta)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in]  *pSrc     input pointer
+ * @param[out]  *pDst    output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_q7_to_q31(
+    q7_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Clarke transform
+* @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+* @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+* @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+* @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+* @return none.
+*/
+
+
+static __INLINE void arm_inv_clarke_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pIa,
+    float32_t* pIb)
+{
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 * Ibeta;
+
+}
+
+/**
+ * @brief  Inverse Clarke transform for Q31 version
+ * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+ * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+ * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+ * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+static __INLINE void arm_inv_clarke_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pIa,
+    q31_t* pIb)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in]  *pSrc     input pointer
+ * @param[out] *pDst     output pointer
+ * @param[in]  blockSize number of samples to process
+ * @return none.
+ */
+void arm_q7_to_q15(
+    q7_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in]       Ialpha input two-phase vector coordinate alpha
+ * @param[in]       Ibeta  input two-phase vector coordinate beta
+ * @param[out]      *pId   points to output rotor reference frame d
+ * @param[out]      *pIq   points to output rotor reference frame q
+ * @param[in]       sinVal sine value of rotation angle theta
+ * @param[in]       cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+static __INLINE void arm_park_f32(
+    float32_t Ialpha,
+    float32_t Ibeta,
+    float32_t* pId,
+    float32_t* pIq,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+}
+
+/**
+ * @brief  Park transform for Q31 version
+ * @param[in]       Ialpha input two-phase vector coordinate alpha
+ * @param[in]       Ibeta  input two-phase vector coordinate beta
+ * @param[out]      *pId   points to output rotor reference frame d
+ * @param[out]      *pIq   points to output rotor reference frame q
+ * @param[in]       sinVal sine value of rotation angle theta
+ * @param[in]       cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+static __INLINE void arm_park_q31(
+    q31_t Ialpha,
+    q31_t Ibeta,
+    q31_t* pId,
+    q31_t* pIq,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief  Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q7_to_float(
+    q7_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief  Floating-point Inverse Park transform
+* @param[in]       Id        input coordinate of rotor reference frame d
+* @param[in]       Iq        input coordinate of rotor reference frame q
+* @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+* @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+* @param[in]       sinVal    sine value of rotation angle theta
+* @param[in]       cosVal    cosine value of rotation angle theta
+* @return none.
+*/
+
+static __INLINE void arm_inv_park_f32(
+    float32_t Id,
+    float32_t Iq,
+    float32_t* pIalpha,
+    float32_t* pIbeta,
+    float32_t sinVal,
+    float32_t cosVal)
+{
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+}
+
+
+/**
+ * @brief  Inverse Park transform for   Q31 version
+ * @param[in]       Id        input coordinate of rotor reference frame d
+ * @param[in]       Iq        input coordinate of rotor reference frame q
+ * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+ * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+ * @param[in]       sinVal    sine value of rotation angle theta
+ * @param[in]       cosVal    cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+static __INLINE void arm_inv_park_q31(
+    q31_t Id,
+    q31_t Iq,
+    q31_t* pIalpha,
+    q31_t* pIbeta,
+    q31_t sinVal,
+    q31_t cosVal)
+{
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_float(
+    q31_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A  Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ *       where x0, x1 are nearest values of input x
+ *             y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief  Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+static __INLINE float32_t arm_linear_interp_f32(
+    arm_linear_interp_instance_f32* S,
+    float32_t x)
+{
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t* pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0) {
+        /* Iniatilize output for below specified range as least output value of table */
+        y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues) {
+        /* Iniatilize output for above specified range as last output value of table */
+        y = pYData[S->nValues - 1];
+    }
+    else {
+        /* Calculation of nearest input values */
+        x0 = S->x1 + i * xSpacing;
+        x1 = S->x1 + (i + 1) * xSpacing;
+
+        /* Read of nearest output values */
+        y0 = pYData[i];
+        y1 = pYData[i + 1];
+
+        /* Calculation of output */
+        y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+}
+
+/**
+*
+* @brief  Process function for the Q31 Linear Interpolation Function.
+* @param[in] *pYData  pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+
+
+static __INLINE q31_t arm_linear_interp_q31(
+    q31_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if(index < 0) {
+        return (pYData[0]);
+    }
+    else {
+
+        /* 20 bits for the fractional part */
+        /* shift left by 11 to keep fract in 1.31 format */
+        fract = (x & 0x000FFFFF) << 11;
+
+        /* Read two nearest output values from the index in 1.31(q31) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+        y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+        /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+        y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+        /* Convert y to 1.31 format */
+        return (y << 1u);
+
+    }
+
+}
+
+/**
+ *
+ * @brief  Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+static __INLINE q15_t arm_linear_interp_q15(
+    q15_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else if(index < 0) {
+        return (pYData[0]);
+    }
+    else {
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+        y = ((q63_t) y0 * (0xFFFFF - fract));
+
+        /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+        y += ((q63_t) y1 * (fract));
+
+        /* convert y to 1.15 format */
+        return (y >> 20);
+    }
+
+
+}
+
+/**
+ *
+ * @brief  Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+static __INLINE q7_t arm_linear_interp_q7(
+    q7_t* pYData,
+    q31_t x,
+    uint32_t nValues)
+{
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0) {
+        return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1)) {
+        return (pYData[nValues - 1]);
+    }
+    else {
+
+        /* 20 bits for the fractional part */
+        /* fract is in 12.20 format */
+        fract = (x & 0x000FFFFF);
+
+        /* Read two nearest output values from the index and are in 1.7(q7) format */
+        y0 = pYData[index];
+        y1 = pYData[index + 1u];
+
+        /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+        y = ((y0 * (0xFFFFF - fract)));
+
+        /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+        y += (y1 * fract);
+
+        /* convert y to 1.7(q7) format */
+        return (y >> 20u);
+
+    }
+
+}
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return  sin(x).
+ */
+
+float32_t arm_sin_f32(
+    float32_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ */
+
+q31_t arm_sin_q31(
+    q31_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  sin(x).
+ */
+
+q15_t arm_sin_q15(
+    q15_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return  cos(x).
+ */
+
+float32_t arm_cos_f32(
+    float32_t x);
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ */
+
+q31_t arm_cos_q31(
+    q31_t x);
+
+/**
+ * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return  cos(x).
+ */
+
+q15_t arm_cos_q15(
+    q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ *      x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ *     x0 = in/2                         [initial guess]
+ *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+ * </pre>
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief  Floating-point square root function.
+ * @param[in]  in     input value.
+ * @param[out] *pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+static __INLINE arm_status arm_sqrt_f32(
+    float32_t in,
+    float32_t* pOut)
+{
+    if(in > 0) {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+        *pOut = __sqrtf(in);
+#else
+        *pOut = sqrtf(in);
+#endif
+
+        return (ARM_MATH_SUCCESS);
+    }
+    else {
+        *pOut = 0.0f;
+        return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out]  *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+    q31_t in,
+    q31_t* pOut);
+
+/**
+ * @brief  Q15 square root function.
+ * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out]  *pOut  square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+    q15_t in,
+    q15_t* pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const int32_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+static __INLINE void arm_circularRead_f32(
+    int32_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    int32_t* dst,
+    int32_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (int32_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value  */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+/**
+ * @brief Q15 Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q15_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q15(
+    q15_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q15_t* dst,
+    q15_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (q15_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+
+static __INLINE void arm_circularWrite_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    uint16_t* writeOffset,
+    int32_t bufferInc,
+    const q7_t* src,
+    int32_t srcInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the input sample to the circular buffer */
+        circBuffer[wOffset] = *src;
+
+        /* Update the input pointer */
+        src += srcInc;
+
+        /* Circularly update wOffset.  Watch out for positive and negative value */
+        wOffset += bufferInc;
+        if(wOffset >= L)
+            wOffset -= L;
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+}
+
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q7(
+    q7_t* circBuffer,
+    int32_t L,
+    int32_t* readOffset,
+    int32_t bufferInc,
+    q7_t* dst,
+    q7_t* dst_base,
+    int32_t dst_length,
+    int32_t dstInc,
+    uint32_t blockSize)
+{
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u) {
+        /* copy the sample from the circular buffer to the destination buffer */
+        *dst = circBuffer[rOffset];
+
+        /* Update the input pointer */
+        dst += dstInc;
+
+        if(dst == (q7_t*) dst_end) {
+            dst = dst_base;
+        }
+
+        /* Circularly update rOffset.  Watch out for positive and negative value */
+        rOffset += bufferInc;
+
+        if(rOffset >= L) {
+            rOffset -= L;
+        }
+
+        /* Decrement the loop counter */
+        i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+}
+
+
+/**
+ * @brief  Sum of the squares of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+/**
+ * @brief  Sum of the squares of the elements of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_power_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Mean value of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_mean_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult);
+
+/**
+ * @brief  Mean value of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Mean value of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Mean value of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+void arm_mean_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q63_t* pResult);
+
+/**
+ * @brief  Variance of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_var_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Root Mean Square of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_rms_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult);
+
+/**
+ * @brief  Standard deviation of the elements of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output value.
+ * @return none.
+ */
+
+void arm_std_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult);
+
+/**
+ * @brief  Floating-point complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_f32(
+    float32_t* pSrc,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_q31(
+    q31_t* pSrc,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex magnitude
+ * @param[in]  *pSrc points to the complex input vector
+ * @param[out]  *pDst points to the real output vector
+ * @param[in]  numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_q15(
+    q15_t* pSrc,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q15 complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    uint32_t numSamples,
+    q31_t* realResult,
+    q31_t* imagResult);
+
+/**
+ * @brief  Q31 complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    uint32_t numSamples,
+    q63_t* realResult,
+    q63_t* imagResult);
+
+/**
+ * @brief  Floating-point complex dot product
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @param[out]  *realResult real part of the result returned here
+ * @param[out]  *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    uint32_t numSamples,
+    float32_t* realResult,
+    float32_t* imagResult);
+
+/**
+ * @brief  Q15 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_q15(
+    q15_t* pSrcCmplx,
+    q15_t* pSrcReal,
+    q15_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_q31(
+    q31_t* pSrcCmplx,
+    q31_t* pSrcReal,
+    q31_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Floating-point complex-by-real multiplication
+ * @param[in]  *pSrcCmplx points to the complex input vector
+ * @param[in]  *pSrcReal points to the real input vector
+ * @param[out]  *pCmplxDst points to the complex output vector
+ * @param[in]  numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+    float32_t* pSrcCmplx,
+    float32_t* pSrcReal,
+    float32_t* pCmplxDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Minimum value of a Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *result is output pointer
+ * @param[in]  index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* result,
+    uint32_t* index);
+
+/**
+ * @brief  Minimum value of a Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Minimum value of a Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+void arm_min_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Minimum value of a floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @param[out]  *pResult is output pointer
+ * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+void arm_min_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+    q7_t* pSrc,
+    uint32_t blockSize,
+    q7_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+    q15_t* pSrc,
+    uint32_t blockSize,
+    q15_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+    q31_t* pSrc,
+    uint32_t blockSize,
+    q31_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+    float32_t* pSrc,
+    uint32_t blockSize,
+    float32_t* pResult,
+    uint32_t* pIndex);
+
+/**
+ * @brief  Q15 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+    q15_t* pSrcA,
+    q15_t* pSrcB,
+    q15_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Q31 complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+    q31_t* pSrcA,
+    q31_t* pSrcB,
+    q31_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief  Floating-point complex-by-complex multiplication
+ * @param[in]  *pSrcA points to the first input vector
+ * @param[in]  *pSrcB points to the second input vector
+ * @param[out]  *pDst  points to the output vector
+ * @param[in]  numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+    float32_t* pSrcA,
+    float32_t* pSrcB,
+    float32_t* pDst,
+    uint32_t numSamples);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q31 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return none.
+ */
+void arm_float_to_q31(
+    float32_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q15 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return          none
+ */
+void arm_float_to_q15(
+    float32_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in]       *pSrc points to the floating-point input vector
+ * @param[out]      *pDst points to the Q7 output vector
+ * @param[in]       blockSize length of the input vector
+ * @return          none
+ */
+void arm_float_to_q7(
+    float32_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_q15(
+    q31_t* pSrc,
+    q15_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q31_to_q7(
+    q31_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+/**
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_float(
+    q15_t* pSrc,
+    float32_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_q31(
+    q15_t* pSrc,
+    q31_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @brief  Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in]  *pSrc is input pointer
+ * @param[out]  *pDst is output pointer
+ * @param[in]  blockSize is the number of samples to process
+ * @return none.
+ */
+void arm_q15_to_q7(
+    q15_t* pSrc,
+    q7_t* pDst,
+    uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ *   typedef struct
+ *   {
+ *     uint16_t numRows;
+ *     uint16_t numCols;
+ *     float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+ * <pre>
+ *     XF = floor(x)
+ *     YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+/**
+*
+* @brief  Floating-point bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+
+
+static __INLINE float32_t arm_bilinear_interp_f32(
+    const arm_bilinear_interp_instance_f32* S,
+    float32_t X,
+    float32_t Y)
+{
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t* pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+            || yIndex > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+}
+
+/**
+*
+* @brief  Q31 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q31_t arm_bilinear_interp_q31(
+    arm_bilinear_interp_instance_q31* S,
+    q31_t X,
+    q31_t Y)
+{
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+}
+
+/**
+* @brief  Q15 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q15_t arm_bilinear_interp_q15(
+    arm_bilinear_interp_instance_q15* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t* pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+}
+
+/**
+* @brief  Q7 bilinear interpolation.
+* @param[in,out] *S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+
+static __INLINE q7_t arm_bilinear_interp_q7(
+    arm_bilinear_interp_instance_q7* S,
+    q31_t X,
+    q31_t Y)
+{
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t* pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+        return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+#define multSub_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("push")         \
+    _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+#define LOW_OPTIMIZATION_EXIT \
+    _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+//SMMLA
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32_R(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+#define LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+#define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+    _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+//SMMLA
+#define multAcc_32x32_keep32_R(a, x, y) \
+    a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32_R(a, x, y) \
+    a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32_R(a, x, y) \
+    a = (q31_t) (((q63_t) x * y ) >> 32)
+
+#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+#define LOW_OPTIMIZATION_EXIT
+
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0.h

@@ -0,0 +1,660 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.02
+ * @date     16. July 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+#define __NVIC_PRIO_BITS          2
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x01)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0_REV
+#define __CM0_REV               0x0000
+#warning "__CM0_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    uint32_t RESERVED0;
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED1;
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm0plus.h

@@ -0,0 +1,785 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                      __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM0PLUS_REV
+#define __CM0PLUS_REV             0x0000
+#warning "__CM0PLUS_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __VTOR_PRESENT
+#define __VTOR_PRESENT            0
+#warning "__VTOR_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+    uint32_t RESERVED0;
+#endif
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED1;
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm3.h

@@ -0,0 +1,1615 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI__VFP_SUPPORT____
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV               0x0200
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+    uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4.h

@@ -0,0 +1,1759 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                   __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI_VFP_SUPPORT__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#if (__FPU_PRESENT == 1)
+#define __FPU_USED       1
+#else
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#define __FPU_USED       0
+#endif
+#else
+#define __FPU_USED         0
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM4_REV
+#define __CM4_REV               0x0000
+#warning "__CM4_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __FPU_PRESENT
+#define __FPU_PRESENT             0
+#warning "__FPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+    __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+    __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+    __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+    __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+#define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+#define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+    NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cm4_simd.h

@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+        ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+        ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+        ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+#define __USAT16(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+    ({ \
+        uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+        __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+        (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+    })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+    ({ \
+        uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+        __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+        (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+    uint32_t result;
+
+    __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+    ({ \
+        uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+        __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+        (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+    })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+    ({ \
+        uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+        __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+        (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+    uint32_t result;
+
+    __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+    return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+        if (ARG3 == 0) \
+            __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+        else \
+            __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+        __RES; \
+    })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+    int32_t result;
+
+    __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+    return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmFunc.h

@@ -0,0 +1,637 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2016
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2016 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    register uint32_t __regControl         __ASM("control");
+    return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+    register uint32_t __regAPSR          __ASM("apsr");
+    return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return(__regfpscr);
+#else
+    return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, control" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, primask" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+    __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+    __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+    __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+    return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    uint32_t result;
+
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile ("");
+    __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+    __ASM volatile ("");
+    return(result);
+#else
+    return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    /* Empty asm statement works as a scheduling barrier */
+    __ASM volatile ("");
+    __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+    __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_cmInstr.h

@@ -0,0 +1,880 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.00
+ * @date     28. August 2016
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2016 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+    rev16 r0, r0
+    bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+    revsh r0, r0
+    bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+    rrx r0, r0
+    bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+    __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+    __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+    __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+    __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+    __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+    __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+    __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+    return __builtin_bswap32(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    return (short)__builtin_bswap16(value);
+#else
+    uint32_t result;
+
+    __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+    return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+    return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+    return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+    return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+    __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+    ({                          \
+        uint32_t __RES, __ARG1 = (ARG1); \
+        __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+        __RES; \
+    })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+    uint32_t result;
+
+    __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+    return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t* addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+    __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+    __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+    return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t* addr)
+{
+    uint32_t result;
+
+    __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+    return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t* addr)
+{
+    __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t* addr)
+{
+    __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t* addr)
+{
+    __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc000.h

@@ -0,0 +1,804 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                     __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC000_REV
+#define __SC000_REV             0x0000
+#warning "__SC000_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          2
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[31];
+    __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+    uint32_t RSERVED1[31];
+    __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+    uint32_t RESERVED2[31];
+    __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+    uint32_t RESERVED3[31];
+    uint32_t RESERVED4[64];
+    __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    uint32_t RESERVED0[1];
+    __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    uint32_t RESERVED1[154];
+    __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                   (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+    else {
+        NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+                                  (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
+    }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M0 system interrupts */
+    else {
+        return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   SCB_AIRCR_SYSRESETREQ_Msk);
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/core_sc300.h

@@ -0,0 +1,1586 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                     __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+#define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+#define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+#define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+#define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+#define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+#define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+#define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+#define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+#define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __SC300_REV
+#define __SC300_REV               0x0000
+#warning "__SC300_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT             0
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS          4
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig    0
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+#define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+    struct {
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 27;             /*!< bit:  0..26  Reserved                           */
+#else
+        uint32_t _reserved0: 16;             /*!< bit:  0..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 7;              /*!< bit: 20..26  Reserved                           */
+#endif
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+        uint32_t _reserved0: 23;             /*!< bit:  9..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+    struct {
+        uint32_t ISR: 9;                     /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+        uint32_t _reserved0: 15;             /*!< bit:  9..23  Reserved                           */
+#else
+        uint32_t _reserved0: 7;              /*!< bit:  9..15  Reserved                           */
+        uint32_t GE: 4;                      /*!< bit: 16..19  Greater than or Equal flags        */
+        uint32_t _reserved1: 4;              /*!< bit: 20..23  Reserved                           */
+#endif
+        uint32_t T: 1;                       /*!< bit:     24  Thumb bit        (read 0)          */
+        uint32_t IT: 2;                      /*!< bit: 25..26  saved IT state   (read 0)          */
+        uint32_t Q: 1;                       /*!< bit:     27  Saturation condition flag          */
+        uint32_t V: 1;                       /*!< bit:     28  Overflow condition code flag       */
+        uint32_t C: 1;                       /*!< bit:     29  Carry condition code flag          */
+        uint32_t Z: 1;                       /*!< bit:     30  Zero condition code flag           */
+        uint32_t N: 1;                       /*!< bit:     31  Negative condition code flag       */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+    struct {
+        uint32_t nPRIV: 1;                   /*!< bit:      0  Execution privilege in Thread mode */
+        uint32_t SPSEL: 1;                   /*!< bit:      1  Stack to be used                   */
+        uint32_t FPCA: 1;                    /*!< bit:      2  FP extension active flag           */
+        uint32_t _reserved0: 29;             /*!< bit:  3..31  Reserved                           */
+    } b;                                   /*!< Structure used for bit  access                  */
+    uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+    __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+    uint32_t RESERVED0[24];
+    __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+    uint32_t RSERVED1[24];
+    __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+    uint32_t RESERVED2[24];
+    __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+    uint32_t RESERVED3[24];
+    __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+    uint32_t RESERVED4[56];
+    __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+    uint32_t RESERVED5[644];
+    __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+    __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+    __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+    __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+    __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+    __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+    __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+    __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+    __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+    __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+    __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+    __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+    __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+    __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+    __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+    __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+    __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+    __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+    __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+    __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+    uint32_t RESERVED0[5];
+    __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+    uint32_t RESERVED0[1];
+    __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+    uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+    __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+    __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+    __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+    __O  union {
+        __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+        __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+        __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+    }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+    uint32_t RESERVED0[864];
+    __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+    uint32_t RESERVED1[15];
+    __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+    uint32_t RESERVED2[15];
+    __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+    uint32_t RESERVED3[29];
+    __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+    __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+    __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+    uint32_t RESERVED4[43];
+    __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+    __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+    uint32_t RESERVED5[6];
+    __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+    __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+    __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+    __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+    __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+    __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+    __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+    __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+    __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+    __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+    __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+    __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+    __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+    __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+    __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+    __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+    __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+    __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+    __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+    __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+    __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+    __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+    __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+    uint32_t RESERVED0[1];
+    __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+    __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+    __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+    uint32_t RESERVED1[1];
+    __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+    __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+    __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+    uint32_t RESERVED2[1];
+    __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+    __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+    __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+    __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+    __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+    uint32_t RESERVED0[2];
+    __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+    uint32_t RESERVED1[55];
+    __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+    uint32_t RESERVED2[131];
+    __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+    __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+    __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+    uint32_t RESERVED3[759];
+    __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+    __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+    __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+    uint32_t RESERVED4[1];
+    __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+    __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+    __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+    uint32_t RESERVED5[39];
+    __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+    __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+    uint32_t RESERVED7[8];
+    __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+    __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+    __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+    __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+    __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+    __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+    __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+    __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+    __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+    __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+    __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+    __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+    __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+    __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+    __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+    __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+#define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+#define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+    uint32_t reg_value;
+    uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+    reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+    reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+    reg_value  =  (reg_value                                 |
+                   ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                   (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+    SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+    return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+    return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+    return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    if(IRQn < 0) {
+        SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    } /* set Priority for Cortex-M  System Interrupts */
+    else {
+        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
+    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+    if(IRQn < 0) {
+        return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF) - 4] >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for Cortex-M  system interrupts */
+    else {
+        return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));
+    } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    return (
+               ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+               ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+           );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+    uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+    uint32_t PreemptPriorityBits;
+    uint32_t SubPriorityBits;
+
+    PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+    SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+    *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+    *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+    __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+    SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                   (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                   SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+    __DSB();                                                     /* Ensure completion of memory access */
+    while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+    if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+    SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+    NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
+    SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+    SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                     SysTick_CTRL_TICKINT_Msk   |
+                     SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+    return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+    if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+            (ITM->TER & (1UL << 0)        )                    ) {   /* ITM Port #0 enabled */
+        while (ITM->PORT[0].u32 == 0);
+        ITM->PORT[0].u8 = (uint8_t) ch;
+    }
+    return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+    int32_t ch = -1;                           /* no character available */
+
+    if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+        ch = ITM_RxBuffer;
+        ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+    }
+
+    return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+    if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+        return (0);                                 /* no character available */
+    }
+    else {
+        return (1);                                 /*    character available */
+    }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_adc.h

@@ -0,0 +1,412 @@
+/**
+******************************************************************************
+* @file    HAL_adc.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the ADC firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_ADC_H
+#define __HAL_ADC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup ADC
+* @{
+*/
+
+/** @defgroup ADC_Exported_Types
+* @{
+*/
+
+/**
+* @brief  ADC Init structure definition
+*/
+
+/*
+typedef struct
+{
+uint32_t ADC_Mode;
+FunctionalState ADC_ScanConvMode;
+FunctionalState ADC_ContinuousConvMode;
+uint32_t ADC_ExternalTrigConv;
+uint32_t ADC_DataAlign;
+uint8_t ADC_NbrOfChannel;
+}ADC_InitTypeDef;
+*/
+typedef struct
+{
+    uint32_t ADC_Resolution;
+    uint32_t ADC_PRESCARE;
+    uint32_t ADC_Mode;
+    FunctionalState ADC_ContinuousConvMode;
+    uint32_t ADC_ExternalTrigConv;
+    uint32_t ADC_DataAlign;
+} ADC_InitTypeDef;
+/**
+* @}
+*/
+
+/** @defgroup ADC_Exported_Constants
+* @{
+*/
+
+#define IS_ADC_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == ADC2_BASE))
+
+#define IS_ADC_DMA_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == ADC2_BASE))
+
+/** @defgroup ADC_Resolution
+* @{
+*/
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_11b                         ((uint32_t)0x00000080)
+#define ADC_Resolution_10b                         ((uint32_t)0x00000100)
+#define ADC_Resolution_9b                          ((uint32_t)0x00000180)
+#define ADC_Resolution_8b                          ((uint32_t)0x00000200)
+/**
+* @brief  for ADC1, ADC2
+*/
+
+#define ADC_PCLK2_PRESCARE_2                       ((uint32_t)0x00000000)
+#define ADC_PCLK2_PRESCARE_4                       ((uint32_t)0x00000010)
+#define ADC_PCLK2_PRESCARE_6                       ((uint32_t)0x00000020)
+#define ADC_PCLK2_PRESCARE_8                       ((uint32_t)0x00000030)
+#define ADC_PCLK2_PRESCARE_10                      ((uint32_t)0x00000040)
+#define ADC_PCLK2_PRESCARE_12                      ((uint32_t)0x00000050)
+#define ADC_PCLK2_PRESCARE_14                      ((uint32_t)0x00000060)
+#define ADC_PCLK2_PRESCARE_16                      ((uint32_t)0x00000070)
+
+
+/** @defgroup ADC_dual_mode
+* @{
+*/
+
+#define ADC_Mode_Single                   	((uint32_t)0x00000000)
+#define ADC_Mode_Single_Period              ((uint32_t)0x00000200)
+#define ADC_Mode_Continuous_Scan            ((uint32_t)0x00000400)
+
+
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Single) || \
+                           ((MODE) == ADC_Mode_Single_Period) || \
+                           ((MODE) == ADC_Mode_Continuous_Scan))
+/**
+* @}
+*/
+
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
+* @{
+*/
+
+/**
+* @brief  for ADC1
+*/
+
+#define ADC_ExternalTrigConv_T1_CC1         	((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2   			  ((uint32_t)0x00000010)
+#define ADC_ExternalTrigConv_T1_CC3     		  ((uint32_t)0x00000020)
+#define ADC_ExternalTrigConv_T2_CC2  			  ((uint32_t)0x00000030)
+#define ADC_ExternalTrigConv_T3_TRGO      		((uint32_t)0x00000040)
+#define ADC_ExternalTrigConv_T4_CC4      		((uint32_t)0x00000050)
+#define ADC_ExternalTrigConv_T3_CC1      		((uint32_t)0x00000060)
+#define ADC_ExternalTrigConv_EXTI_11     	  ((uint32_t)0x00000070)
+
+/**
+* @brief  for ADC2
+*/
+
+#define ADC_ExternalTrigConv_T1_TRGO          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC4           ((uint32_t)0x00000010)
+#define ADC_ExternalTrigConv_T2_TRGO          ((uint32_t)0x00000020)
+#define ADC_ExternalTrigConv_T2_CC1           ((uint32_t)0x00000030)
+#define ADC_ExternalTrigConv_T3_CC4           ((uint32_t)0x00000040)
+#define ADC_ExternalTrigConv_T4_TRGO          ((uint32_t)0x00000050)
+#define ADC_ExternalTrigConv_T3_CC1           ((uint32_t)0x00000060)
+#define ADC_ExternalTrigConv_EXTI_15          ((uint32_t)0x00000070)
+
+
+
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_EXTI_11) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_EXTI_15))
+/**
+* @}
+*/
+
+/** @defgroup ADC_data_align
+* @{
+*/
+
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+* @}
+*/
+
+/** @defgroup ADC_channels
+* @{
+*/
+
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_All															((uint8_t)0x0f)
+
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_All))
+/**
+* @}
+*/
+
+#define  ADC_SMPR_SMP                      ((uint32_t)0x00000007)        /*!< SMP[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR_SMP_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR_SMP_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR_SMP_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+/** @defgroup ADC_sampling_times
+* @{
+*/
+
+#define ADC_SampleTime_1_5Cycles                     ((uint32_t)0x00000000)
+#define ADC_SampleTime_7_5Cycles                     ((uint32_t)0x00000001)
+#define ADC_SampleTime_13_5Cycles                    ((uint32_t)0x00000002)
+#define ADC_SampleTime_28_5Cycles                    ((uint32_t)0x00000003)
+#define ADC_SampleTime_41_5Cycles                    ((uint32_t)0x00000004)
+#define ADC_SampleTime_55_5Cycles                    ((uint32_t)0x00000005)
+#define ADC_SampleTime_71_5Cycles                    ((uint32_t)0x00000006)
+#define ADC_SampleTime_239_5Cycles                   ((uint32_t)0x00000007)
+
+/** @defgroup ADC_injected_channel_selection
+* @{
+*/
+
+#define ADC_InjectedChannel_0                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_1                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x20)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x24)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x28)
+#define ADC_InjectedChannel_5                       ((uint8_t)0x2C)
+#define ADC_InjectedChannel_6                       ((uint8_t)0x30)
+#define ADC_InjectedChannel_7                       ((uint8_t)0x34)
+#define ADC_InjectedChannel_8                       ((uint8_t)0x38)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+        ((CHANNEL) == ADC_InjectedChannel_2) || \
+        ((CHANNEL) == ADC_InjectedChannel_3) || \
+        ((CHANNEL) == ADC_InjectedChannel_4) || \
+        ((CHANNEL) == ADC_InjectedChannel_5) || \
+        ((CHANNEL) == ADC_InjectedChannel_6) || \
+        ((CHANNEL) == ADC_InjectedChannel_7) || \
+        ((CHANNEL) == ADC_InjectedChannel_8))
+/**
+* @}
+*/
+
+/** @defgroup ADC_analog_watchdog_selection
+* @{
+*/
+
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00000002)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+        ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+* @}
+*/
+
+/** @defgroup ADC_interrupts_definition
+* @{
+*/
+
+#define ADC_IT_EOC                                 ((uint16_t)0x0001)
+#define ADC_IT_AWD                                 ((uint16_t)0x0002)
+
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xFFFC) == 0x00) && ((IT) != 0x00))
+
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD))
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_flags_definition
+* @{
+*/
+
+#define ADC_FLAG_AWD                               ((uint8_t)0x02)
+#define ADC_FLAG_EOC                               ((uint8_t)0x01)
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC))
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_thresholds
+* @{
+*/
+
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_injected_offset
+* @{
+*/
+
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_injected_length
+* @{
+*/
+
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_injected_rank
+* @{
+*/
+
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+
+/**
+* @}
+*/
+
+
+/** @defgroup ADC_regular_length
+* @{
+*/
+
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+* @}
+*/
+
+/** @defgroup ADC_regular_rank
+* @{
+*/
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_regular_discontinuous_mode_number
+* @{
+*/
+
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Exported_Functions
+* @{
+*/
+
+void ADC_DeInit(ADC_TypeDef* ADCx);
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#endif /*__HAL_ADC_H */
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_bkp.h

@@ -0,0 +1,186 @@
+/**
+******************************************************************************
+* @file    HAL_bkp.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the BKP firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_BKP_H
+#define __HAL_BKP_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup BKP
+* @{
+*/
+
+/** @defgroup BKP_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Exported_Constants
+* @{
+*/
+
+/** @defgroup Tamper_Pin_active_level
+* @{
+*/
+
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \
+                                        ((LEVEL) == BKP_TamperPinLevel_Low))
+/**
+* @}
+*/
+
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin
+* @{
+*/
+
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \
+        ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \
+        ((SOURCE) == BKP_RTCOutputSource_Alarm) || \
+        ((SOURCE) == BKP_RTCOutputSource_Second))
+/**
+* @}
+*/
+
+/** @defgroup Data_Backup_Register
+* @{
+*/
+
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1)  || ((DR) == BKP_DR2)  || ((DR) == BKP_DR3)  || \
+                       ((DR) == BKP_DR4)  || ((DR) == BKP_DR5)  || ((DR) == BKP_DR6)  || \
+                       ((DR) == BKP_DR7)  || ((DR) == BKP_DR8)  || ((DR) == BKP_DR9)  || \
+                       ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \
+                       ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \
+                       ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \
+                       ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \
+                       ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \
+                       ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \
+                       ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \
+                       ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \
+                       ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \
+                       ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \
+                       ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))
+
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Exported_Functions
+* @{
+*/
+
+void BKP_DeInit(void);
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void BKP_TamperPinCmd(FunctionalState NewState);
+void BKP_ITConfig(FunctionalState NewState);
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void BKP_ClearFlag(void);
+ITStatus BKP_GetITStatus(void);
+void BKP_ClearITPendingBit(void);
+
+#endif /* __HAL_BKP_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_can.h

@@ -0,0 +1,392 @@
+/**
+******************************************************************************
+* @file    HAL_can.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the BKP firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_CAN_H
+#define __HAL_CAN_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+
+/** @defgroup CAN_sleep_constants
+* @{
+*/
+
+#define CANINITFAILED              ((uint8_t)0x00) /* CAN initialization failed */
+#define CANINITOK                  ((uint8_t)0x01) /* CAN initialization ok */
+
+/**
+* @}
+*/
+
+
+
+/** @defgroup CAN_sleep_constants
+* @{
+*/
+
+#define CANSLEEPFAILED              ((uint8_t)0x00) /* CAN did not enter the sleep mode */
+#define CANSLEEPOK                  ((uint8_t)0x01) /* CAN entered the sleep mode */
+
+/**
+* @}
+*/
+
+
+/** @defgroup CAN_wake_up_constants
+* @{
+*/
+
+#define CANWAKEUPFAILED             ((uint8_t)0x00) /* CAN did not leave the sleep mode */
+#define CANWAKEUPOK                 ((uint8_t)0x01) /* CAN leaved the sleep mode */
+
+/**
+* @}
+*/
+
+/**
+* @brief  parasmeter of CAN Mode
+*/
+#define CAN_BASICMode ((uint32_t)0x0)
+#define CAN_PELIMode  ((uint32_t)0x80)
+#define CAN_WorkMode		((uint32_t)0x80)
+#define CAN_ResetMode 		((uint32_t)0x1)
+#define CAN_ListenOnlyMode	((uint32_t)0x2)
+#define CAN_SeftTestMode	((uint32_t)0x4)
+#define CAN_FilterMode_Singal	((uint32_t)0x8)
+#define CAN_FilterMode_Double	((uint32_t)0xf7)
+#define CAN_SleepMode		((uint32_t)0x10)
+
+/**
+* @}
+*/
+
+/**
+* @brief  parasmeter of BASIC CAN interrupt
+*/
+#define CAN_IT_RIE	((uint32_t)0x2)
+#define CAN_IT_TIE	((uint32_t)0x4)
+#define CAN_IT_EIE	((uint32_t)0x8)
+#define CAN_IT_OIE	((uint32_t)0x10)
+
+/**
+* @}
+*/
+
+/**
+* @brief  parasmeter of PELI CAN interrupt
+*/
+#define CAN_IT_RI	((uint32_t)0x1)
+#define CAN_IT_TI	((uint32_t)0x2)
+#define CAN_IT_EI	((uint32_t)0x4)
+#define CAN_IT_DOI	((uint32_t)0x8)
+#define CAN_IT_WUI	((uint32_t)0x10)
+#define CAN_IT_EPI	((uint32_t)0x20)
+#define CAN_IT_ALI	((uint32_t)0x40)
+#define CAN_IT_BEI	((uint32_t)0x80)
+#define CAN_IT_ALL	((uint32_t)0xff)
+
+/**
+* @}
+*/
+
+/**
+* @brief  parasmeter of CAN Status
+*/
+#define CAN_STATUS_RBS	((uint32_t)0x1)
+#define CAN_STATUS_DOS	((uint32_t)0x2)
+#define CAN_STATUS_TBS	((uint32_t)0x4)
+#define CAN_STATUS_TCS	((uint32_t)0x8)
+#define CAN_STATUS_RS	((uint32_t)0x10)
+#define CAN_STATUS_TS	((uint32_t)0x20)
+#define CAN_STATUS_ES	((uint32_t)0x40)
+#define CAN_STATUS_BS	((uint32_t)0x80)
+
+/**
+* @}
+*/
+
+/**
+* @brief  parasmeter of CAN Command register
+*/
+#define CAN_TR	0x1
+#define CAN_AT	0x2
+#define CAN_RRB	0x4
+#define CAN_CDO	0x8
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Basic init structure definition
+*/
+typedef struct
+{
+    uint8_t SJW;
+    uint8_t BRP;
+    FlagStatus SAM;
+    uint8_t TESG2;
+    uint8_t TESG1;
+    FunctionalState GTS;
+    uint8_t CDCLK;
+    uint8_t CLOSE_OPEN_CLK;
+    uint8_t RXINTEN;
+    uint8_t CBP;
+} CAN_Basic_InitTypeDef;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Peli init structure definition
+*/
+typedef struct
+{
+    uint8_t SJW;
+    uint8_t BRP;
+    FlagStatus SAM;
+    uint8_t TESG2;
+    uint8_t TESG1;
+    FunctionalState LOM;
+    FunctionalState STM;
+    FunctionalState SM;
+    FunctionalState SRR;
+    uint32_t EWLR;
+} CAN_Peli_InitTypeDef;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Basic filter init structure definition
+*/
+typedef struct
+{
+    uint8_t CAN_FilterId;         /*!< Specifies the filter identification number .
+  This parameter can be a value between 0x00 and 0xFF */
+
+    uint8_t CAN_FilterMaskId;     /*!< Specifies the filter mask number or identification number,
+  This parameter can be a value between 0x00 and 0xFF */
+} CAN_Basic_FilterInitTypeDef;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Peli filter init structure definition
+*/
+typedef struct
+{
+    uint8_t AFM;
+    uint8_t CAN_FilterId0;         /*!< Specifies the filter identification number
+  This parameter can be a value between 0x00 and 0xFF */
+    uint8_t CAN_FilterId1;
+    uint8_t CAN_FilterId2;
+    uint8_t CAN_FilterId3;
+
+    uint8_t CAN_FilterMaskId0;     /*!< Specifies the filter mask number or identification number,
+  This parameter can be a value between 0x00 and 0xFF */
+    uint8_t CAN_FilterMaskId1;
+    uint8_t CAN_FilterMaskId2;
+    uint8_t CAN_FilterMaskId3;
+} CAN_Peli_FilterInitTypeDef;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Peli transmit frame definition
+*/
+typedef enum {DataFrame = 0, RemoteFrame = !DataFrame} TransFrame;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Basic Tx message structure definition
+*/
+typedef struct
+{
+    uint8_t IDH;  /*!< Specifies the standard high identifier.
+  This parameter can be a value between 0 to 0xFF. */
+    uint8_t IDL;  /*!< Specifies the standard low identifier.
+  This parameter can be a value between 0 to 0x7. */
+    uint8_t RTR;     /*!< Specifies the type of frame for the message that will
+  be transmitted. This parameter can be @TransFrame */
+
+    uint8_t DLC;     /*!< Specifies the length of the frame that will be
+  transmitted. This parameter can be a value between
+  0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+  to 0xFF. */
+} CanBasicTxMsg;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Basic Rx message structure definition
+*/
+typedef struct
+{
+    uint16_t ID;  /*!< Specifies the standard identifier.
+  This parameter can be a value between 0 to 0x7FF. */
+    uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+  This parameter can be a value of
+  @ref TransFrame */
+
+    uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+  This parameter can be a value between 0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+  0xFF. */
+
+} CanBasicRxMsg;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN_Peli_Tx message structure definition
+*/
+typedef struct
+{
+    uint8_t IDLL;  /*!< Specifies the extended identifier.
+  This parameter can be a value between 0 to 0xFF. */
+    uint8_t IDLH;
+    uint8_t IDHL;
+    uint8_t IDHH;
+    uint8_t FF;     /*!< Specifies the type of identifier for the message that
+  will be transmitted. This parameter can be a value
+  of @ref CAN_identifier_type */
+
+    uint8_t RTR;     /*!< Specifies the type of frame for the message that will
+  be transmitted. This parameter can be a value of
+  @ref TransFrame */
+
+    uint8_t DLC;     /*!< Specifies the length of the frame that will be
+  transmitted. This parameter can be a value between
+  0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
+  to 0xFF. */
+} CanPeliTxMsg;
+
+/**
+* @}
+*/
+
+/**
+* @brief  CAN Rx message structure definition
+*/
+typedef struct
+{
+    uint32_t ID;  /*!< Specifies the extended identifier.
+  This parameter can be a value between 0 to 0x1FFFFFFF. */
+    uint8_t FF;     /*!< Specifies the type of identifier for the message that
+  will be received. This parameter can be a value of
+  @ref CAN_identifier_type */
+
+    uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+  This parameter can be a value of
+  @ref TransFrame */
+
+    uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+  This parameter can be a value between 0 to 8 */
+
+    uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
+  0xFF. */
+
+} CanPeliRxMsg;
+
+
+
+
+#define CANTXFAILED                 ((uint8_t)0x00) /* CAN transmission failed */
+#define CANTXOK                     ((uint8_t)0x01) /* CAN transmission succeeded */
+#define CANTXPENDING                ((uint8_t)0x02) /* CAN transmission pending */
+#define CAN_NO_MB                   ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
+
+
+/************************ Basic and Peli Work all need function ********************/
+
+void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE);
+void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_ClearDataOverflow(CAN_TypeDef* CANx);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx);
+
+
+/************************ Basic Work function ********************/
+void CAN_DeInit(CAN_TypeDef* CANx);
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct);
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct);
+void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct);
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate);
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage);
+void CAN_CancelTransmit(CAN_TypeDef* CANx);
+void CAN_FIFORelease(CAN_TypeDef* CANx);
+void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+
+/************************ Peli Work function *********************/
+void CAN_Peli_SleepMode_Cmd(FunctionalState NewState);
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* CAN_InitStruct);
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct);
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct);
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct);
+void CAN_Peli_Transmit(CanPeliTxMsg* PeliTxMessage);
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* PeliTxMessage);
+void CAN_Peli_Receive(CanPeliRxMsg* PeliRxMessage);
+uint32_t CAN_Peli_GetRxFIFOInfo(void);
+uint8_t CAN_Peli_GetLastErrorCode(void);
+uint8_t CAN_Peli_GetReceiveErrorCounter(void);
+uint8_t CAN_Peli_GetLSBTransmitErrorCounter(void);
+void CAN_Peli_ITConfig(uint32_t CAN_IT, FunctionalState NewState);
+ITStatus CAN_Peli_GetITStatus(uint32_t CAN_IT);
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef  *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud );
+#endif /* __HAL_CAN_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/
+

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_conf.h

@@ -0,0 +1,48 @@
+/**
+******************************************************************************
+* @file    HAL_conf.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains Header file for generic microcontroller.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+#ifndef __HAL_CONF_H__
+#define __HAL_CONF_H__
+
+/*´Ë´¦¿ÉÌí¼Ó»òɾ³ýÍâÉè*/
+#include "HAL_device.h"
+
+
+#include "HAL_adc.h"
+#include "HAL_bkp.h"
+#include "HAL_can.h"
+#include "HAL_crc.h"
+#include "HAL_dma.h"
+#include "HAL_exti.h"
+#include "HAL_flash.h"
+#include "HAL_gpio.h"
+#include "HAL_i2c.h"
+#include "HAL_iwdg.h"
+#include "HAL_pwr.h"
+#include "HAL_rcc.h"
+#include "HAL_rtc.h"
+#include "HAL_spi.h"
+#include "HAL_tim.h"
+#include "HAL_uart.h"
+#include "HAL_wwdg.h"
+#include "HAL_misc.h"
+
+#endif  /* __HAL_CONF_H__ */
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_crc.h

@@ -0,0 +1,85 @@
+/**
+******************************************************************************
+* @file    HAL_crc.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the CRC firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_CRC_H
+#define __HAL_CRC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup CRC
+* @{
+*/
+
+/** @defgroup CRC_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Exported_Constants
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Exported_Functions
+* @{
+*/
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#endif /* __HAL_CRC_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_dma.h

@@ -0,0 +1,354 @@
+/**
+******************************************************************************
+* @file    HAL_dma.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the DMA firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_DMA_H
+#define __HAL_DMA_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup DMA
+* @{
+*/
+
+/** @defgroup DMA_Exported_Types
+* @{
+*/
+
+/**
+* @brief  DMA Init structure definition
+*/
+
+typedef struct
+{
+    uint32_t DMA_PeripheralBaseAddr;
+    uint32_t DMA_MemoryBaseAddr;
+    uint32_t DMA_DIR;
+    uint32_t DMA_BufferSize;
+    uint32_t DMA_PeripheralInc;
+    uint32_t DMA_MemoryInc;
+    uint32_t DMA_PeripheralDataSize;
+    uint32_t DMA_MemoryDataSize;
+    uint32_t DMA_Mode;
+    uint32_t DMA_Priority;
+    uint32_t DMA_M2M;
+} DMA_InitTypeDef;
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Exported_Constants
+* @{
+*/
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel2_BASE)  || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel3_BASE)  || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel4_BASE)  || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel5_BASE)  || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel6_BASE)  || \
+                                   ((*(uint32_t*)&(PERIPH)) == DMA1_Channel7_BASE))
+
+
+/** @defgroup DMA_data_transfer_direction
+* @{
+*/
+
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010) //mtop
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000) //ptom
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
+                         ((DIR) == DMA_DIR_PeripheralSRC))
+/**
+* @}
+*/
+
+/** @defgroup DMA_peripheral_incremented_mode
+* @{
+*/
+
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+        ((STATE) == DMA_PeripheralInc_Disable))
+/**
+* @}
+*/
+
+/** @defgroup DMA_memory_incremented_mode
+* @{
+*/
+
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+* @}
+*/
+
+/** @defgroup DMA_peripheral_data_size
+* @{
+*/
+
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+        ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+        ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+* @}
+*/
+
+/** @defgroup DMA_memory_data_size
+* @{
+*/
+
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+* @}
+*/
+
+/** @defgroup DMA_circular_normal_mode
+* @{
+*/
+
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
+/**
+* @}
+*/
+
+/** @defgroup DMA_priority_level
+* @{
+*/
+
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+                                   ((PRIORITY) == DMA_Priority_High) || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_Low))
+/**
+* @}
+*/
+
+/** @defgroup DMA_memory_to_memory
+* @{
+*/
+
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_interrupts_definition
+* @{
+*/
+
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+/**
+* @brief  For DMA1
+*/
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_flags_definition
+* @{
+*/
+
+/**
+* @brief  For DMA1
+*/
+
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Buffer_Size
+* @{
+*/
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Exported_Functions
+* @{
+*/
+
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+void DMA_ClearFlag(uint32_t DMA_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+#endif /*__HAL_DMA_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*------------------ (C) COPYRIGHT 2019 MindMotion ------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_exti.h

@@ -0,0 +1,170 @@
+/**
+******************************************************************************
+* @file    HAL_exti.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the EXTI
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_EXTI_H
+#define __HAL_EXTI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup EXTI
+* @{
+*/
+
+/** @defgroup EXTI_Exported_Types
+* @{
+*/
+
+/**
+* @brief  EXTI mode enumeration
+*/
+
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event = 0x04
+} EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+* @brief  EXTI Trigger enumeration
+*/
+
+typedef enum
+{
+    EXTI_Trigger_Rising = 0x08,
+    EXTI_Trigger_Falling = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+* @brief  EXTI Init Structure definition
+*/
+
+typedef struct
+{
+    uint32_t EXTI_Line;
+    EXTIMode_TypeDef EXTI_Mode;
+    EXTITrigger_TypeDef EXTI_Trigger;
+    FunctionalState EXTI_LineCmd;
+} EXTI_InitTypeDef;
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Exported_Constants
+* @{
+*/
+
+/** @defgroup EXTI_Lines
+* @{
+*/
+
+#define EXTI_Line0       ((uint32_t)0x00001)  /* External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)  /* External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)  /* External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)  /* External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)  /* External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)  /* External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)  /* External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)  /* External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)  /* External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)  /* External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)  /* External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)  /* External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)  /* External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)  /* External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)  /* External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)  /* External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)  /* External interrupt line 16
+Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)  /* External interrupt line 17 
+Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)  /* External interrupt line 18 
+Connected to the USB Wakeup from 
+suspend event */
+
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF80000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Exported_Functions
+* @{
+*/
+
+void EXTI_DeInit(void);
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#endif /* __HAL_EXTI_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_flash.h

@@ -0,0 +1,307 @@
+/**
+******************************************************************************
+* @file    HAL_flash.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the FLASH
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_FLASH_H
+#define __HAL_FLASH_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup FLASH
+* @{
+*/
+
+/** @defgroup FLASH_Exported_Types
+* @{
+*/
+
+/**
+* @brief  FLASH Status
+*/
+
+typedef enum
+{
+    FLASH_BUSY = 1,
+    FLASH_ERROR_PG,
+    FLASH_ERROR_WRP,
+    FLASH_COMPLETE,
+    FLASH_TIMEOUT
+} FLASH_Status;
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Exported_Constants
+* @{
+*/
+
+/** @defgroup Flash_Latency
+* @{
+*/
+
+#define FLASH_Latency_0                ((uint32_t)0x00000000)  /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint32_t)0x00000001)  /* FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint32_t)0x00000002)  /* FLASH Two Latency cycles */
+#define FLASH_Latency_3                ((uint32_t)0x00000003)  /* FLASH Three Latency cycles */
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2) || \
+                                   ((LATENCY) == FLASH_Latency_3))
+/**
+* @}
+*/
+
+/** @defgroup Half_Cycle_Enable_Disable
+* @{
+*/
+
+#define FLASH_HalfCycleAccess_Enable   ((uint32_t)0x00000008)  /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable  ((uint32_t)0x00000000)  /* FLASH Half Cycle Disable */
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \
+        ((STATE) == FLASH_HalfCycleAccess_Disable))
+/**
+* @}
+*/
+
+/** @defgroup Prefetch_Buffer_Enable_Disable
+* @{
+*/
+
+#define FLASH_PrefetchBuffer_Enable    ((uint32_t)0x00000010)  /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable   ((uint32_t)0x00000000)  /* FLASH Prefetch Buffer Disable */
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \
+        ((STATE) == FLASH_PrefetchBuffer_Disable))
+/**
+* @}
+*/
+
+/** @defgroup Option_Bytes_Write_Protection
+* @{
+*/
+
+/* Values to be used with microcontroller Medium-density devices: FLASH memory density
+ranges between 32 and 128 Kbytes with page size equal to 1 Kbytes */
+#define FLASH_WRProt_Pages0to3         ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7         ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11        ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15       ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19       ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23       ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27       ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31       ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
+#define FLASH_WRProt_Pages32to35       ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39       ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43       ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47       ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51       ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55       ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59       ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63       ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67       ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71       ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75       ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79       ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83       ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87       ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91       ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95       ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99       ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103     ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107     ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111     ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115     ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119     ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123     ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127     ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */
+
+/* Values to be used with microcontroller High-density devices: FLASH memory density
+ranges between 256 and 512 Kbytes with page size equal to 2 Kbytes */
+#define FLASH_WRProt_Pages0to1         ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define FLASH_WRProt_Pages2to3         ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define FLASH_WRProt_Pages4to5         ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define FLASH_WRProt_Pages6to7         ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define FLASH_WRProt_Pages8to9         ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define FLASH_WRProt_Pages10to11       ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define FLASH_WRProt_Pages12to13       ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define FLASH_WRProt_Pages14to15       ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define FLASH_WRProt_Pages16to17       ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define FLASH_WRProt_Pages18to19       ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define FLASH_WRProt_Pages20to21       ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define FLASH_WRProt_Pages22to23       ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define FLASH_WRProt_Pages24to25       ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define FLASH_WRProt_Pages26to27       ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define FLASH_WRProt_Pages28to29       ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define FLASH_WRProt_Pages30to31       ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define FLASH_WRProt_Pages32to33       ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define FLASH_WRProt_Pages34to35       ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define FLASH_WRProt_Pages36to37       ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define FLASH_WRProt_Pages38to39       ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define FLASH_WRProt_Pages40to41       ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define FLASH_WRProt_Pages42to43       ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define FLASH_WRProt_Pages44to45       ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define FLASH_WRProt_Pages46to47       ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define FLASH_WRProt_Pages48to49       ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define FLASH_WRProt_Pages50to51       ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define FLASH_WRProt_Pages52to53       ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define FLASH_WRProt_Pages54to55       ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define FLASH_WRProt_Pages56to57       ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define FLASH_WRProt_Pages58to59       ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define FLASH_WRProt_Pages60to61       ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define FLASH_WRProt_Pages62to255      ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
+#define FLASH_WRProt_AllPages          ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
+
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))
+
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0807FFFF))
+
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+* @}
+*/
+
+/** @defgroup Option_Bytes_IWatchdog
+* @{
+*/
+
+#define OB_IWDG_SW                     ((uint16_t)0x0001)  /* Software IWDG selected */
+#define OB_IWDG_HW                     ((uint16_t)0x0000)  /* Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+* @}
+*/
+
+/** @defgroup Option_Bytes_nRST_STOP
+* @{
+*/
+
+#define OB_STOP_NoRST                  ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+* @}
+*/
+
+/** @defgroup Option_Bytes_nRST_STDBY
+* @{
+*/
+
+#define OB_STDBY_NoRST                 ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Interrupts
+* @{
+*/
+
+#define FLASH_IT_ERROR                 ((uint32_t)0x00000400)  /* FPEC error interrupt source */
+#define FLASH_IT_EOP                   ((uint32_t)0x00001000)  /* End of FLASH Operation Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Flags
+* @{
+*/
+
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00000001)  /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000020)  /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR               ((uint32_t)0x00000004)  /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR            ((uint32_t)0x00000010)  /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR              ((uint32_t)0x00000001)  /* FLASH Option Byte error flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
+                                  ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \
+                                  ((FLAG) == FLASH_FLAG_OPTERR))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Exported_Functions
+* @{
+*/
+
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t FLASH_GetUserOptionByte(void);
+uint32_t FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus FLASH_GetReadOutProtectionStatus(void);
+FlagStatus FLASH_GetPrefetchBufferStatus(void);
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG);
+void FLASH_ClearFlag(uint16_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#endif /* __HAL_FLASH_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_gpio.h

@@ -0,0 +1,325 @@
+/**
+******************************************************************************
+* @file    HAL_gpio.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the GPIO
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_GPIO_H
+#define __HAL_GPIO_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup GPIO
+* @{
+*/
+
+/** @defgroup GPIO_Exported_Types
+* @{
+*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == GPIOA_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOB_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOC_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOD_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOE_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOF_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == GPIOG_BASE))
+
+/**
+* @brief  Output Maximum frequency selection
+*/
+
+typedef enum
+{
+    GPIO_Speed_10MHz = 1,
+    GPIO_Speed_2MHz,
+    GPIO_Speed_50MHz
+} GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \
+                              ((SPEED) == GPIO_Speed_50MHz))
+
+/**
+* @brief  Configuration Mode enumeration
+*/
+
+typedef enum
+{
+    GPIO_Mode_AIN = 0x0,  //模拟输入
+    GPIO_Mode_IN_FLOATING = 0x04, //浮空输入
+    GPIO_Mode_IPD = 0x28,  //下拉输入
+    GPIO_Mode_IPU = 0x48,  //上拉输入
+    GPIO_Mode_Out_OD = 0x14,//通用开漏输出
+    GPIO_Mode_Out_PP = 0x10,//通用推免输出
+    GPIO_Mode_AF_OD = 0x1C, // 复用开漏输出
+    GPIO_Mode_AF_PP = 0x18  //复用推免输出
+} GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \
+                            ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \
+                            ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \
+                            ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
+
+/**
+* @brief  GPIO Init structure definition
+*/
+
+typedef struct
+{
+    uint16_t GPIO_Pin;
+    GPIOSpeed_TypeDef GPIO_Speed;
+    GPIOMode_TypeDef GPIO_Mode;
+} GPIO_InitTypeDef;
+
+/**
+* @brief  Bit_SET and Bit_RESET enumeration
+*/
+
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Exported_Constants
+* @{
+*/
+
+/** @defgroup GPIO_pins_define
+* @{
+*/
+
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Remap_define
+* @{
+*/
+
+#define GPIO_Remap_SPI1            ((uint32_t)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1            ((uint32_t)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_UART1          ((uint32_t)0x00000004)  /* UART1 Alternate Function mapping */
+#define GPIO_Remap_UART2          ((uint32_t)0x00000008)  /* UART2 Alternate Function mapping */
+#define GPIO_PartialRemap_UART3   ((uint32_t)0x00140010)  /* UART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_UART3      ((uint32_t)0x00140030)  /* UART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1     ((uint32_t)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1        ((uint32_t)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2    ((uint32_t)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2    ((uint32_t)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2        ((uint32_t)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3     ((uint32_t)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3        ((uint32_t)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4            ((uint32_t)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1           ((uint32_t)0x001D4000)  /* CAN Alternate Function mapping */
+#define GPIO_Remap2_CAN1           ((uint32_t)0x001D0000)  /* CAN Alternate Function mapping */
+#define GPIO_Remap_PD01            ((uint32_t)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI     ((uint32_t)0x00200001)  /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ    ((uint32_t)0x00200002)  /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG    ((uint32_t)0x00200004)  /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ    ((uint32_t)0x00200008)  /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG    ((uint32_t)0x00200010)  /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJTRST     ((uint32_t)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable     ((uint32_t)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \
+                              ((REMAP) == GPIO_Remap_UART1) || ((REMAP) == GPIO_Remap_UART2) || \
+                              ((REMAP) == GPIO_PartialRemap_UART3) || ((REMAP) == GPIO_FullRemap_UART3) || \
+                              ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \
+                              ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \
+                              ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \
+                              ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \
+                              ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \
+                              ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \
+                              ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \
+                              ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \
+                              ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable)|| \
+                              ((REMAP) == GPIO_Remap_SWJ_Disable))
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Port_Sources
+* @{
+*/
+
+#define GPIO_PortSourceGPIOA       ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB       ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC       ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD       ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE       ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF       ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG       ((uint8_t)0x06)
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOE))
+
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \
+        ((PORTSOURCE) == GPIO_PortSourceGPIOG))
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Pin_sources
+* @{
+*/
+
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Exported_Functions
+* @{
+*/
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+
+#endif /* __HAL_GPIO_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_i2c.h

@@ -0,0 +1,333 @@
+/**
+******************************************************************************
+* @file    HAL_i2c.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the I2C firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_I2C_H
+#define __HAL_I2C_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup I2C
+* @{
+*/
+
+/** @defgroup I2C_Exported_Types
+* @{
+*/
+
+/**
+* @brief  I2C Init structure definition
+*/
+/*
+typedef struct
+{
+uint16_t I2C_Mode;
+uint16_t I2C_DutyCycle;
+uint16_t I2C_OwnAddress1;
+uint16_t I2C_Ack;
+uint16_t I2C_AcknowledgedAddress;
+uint32_t I2C_ClockSpeed;
+}I2C_InitTypeDef;
+*/
+typedef struct
+{
+    uint16_t I2C_Mode;
+    uint16_t I2C_Speed;
+    uint16_t I2C_OwnAddress;
+    uint32_t I2C_ClockSpeed;
+} I2C_InitTypeDef;
+
+/**
+* @}
+*/
+
+
+/** @defgroup I2C_Exported_Constants
+* @{
+*/
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == I2C1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == I2C2_BASE))
+/** @defgroup I2C_modes
+* @{
+*/
+
+#define   TX_EMPTY_CTRL						(0x0001<<8)
+#define		IC_SLAVE_DISABLE				(0x0001<<6)
+#define		IC_SLAVE_ENABLE					(0x0000<<6)
+#define		IC_RESTART_EN						(0x0001<<5)
+#define		IC_7BITADDR_MASTER			(0x0000<<4)
+#define		IC_7BITADDR_SLAVE				(0x0000<<3)
+
+#define 	I2C_Speed_STANDARD      ((uint16_t)0x0002)
+#define 	I2C_Speed_FAST         	((uint16_t)0x0004)
+#define 	I2C_Mode_MASTER					((uint16_t)0x0001)
+#define 	I2C_Mode_SLAVE					((uint16_t)0x0000)
+
+#define 	TDMAE_SET								((uint16_t)0x0002)
+#define 	RDMAE_SET								((uint16_t)0x0001)
+
+#define 	CMD_READ								((uint16_t)0x0100)
+#define 	CMD_WRITE								((uint16_t)0x0000)
+
+
+
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C))
+
+/**
+* @}
+*/
+
+
+/** @defgroup I2C_transfer_direction
+* @{
+*/
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+* @}
+*/
+
+/** @defgroup I2C_acknowledged_address_defines
+* @{
+*/
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+        ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_interrupts_definition
+* @{
+*/
+
+
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+* @}
+*/
+
+/** @defgroup I2C_interrupts_definition
+* @{
+*/
+
+#define I2C_IT_RX_UNDER					((uint16_t)0x0001)
+#define I2C_IT_RX_OVER					((uint16_t)0x0002)
+#define I2C_IT_RX_FULL  				((uint16_t)0x0004)
+#define I2C_IT_TX_OVER					((uint16_t)0x0008)
+#define I2C_IT_TX_EMPTY					((uint16_t)0x0010)
+#define I2C_IT_RD_REQ						((uint16_t)0x0020)
+#define I2C_IT_TX_ABRT					((uint16_t)0x0040)
+#define I2C_IT_RX_DONE					((uint16_t)0x0080)
+#define I2C_IT_ACTIVITY					((uint16_t)0x0100)
+#define I2C_IT_STOP_DET					((uint16_t)0x0200)
+#define I2C_IT_START_DET				((uint16_t)0x0400)
+#define I2C_IT_GEN_CALL				((uint16_t)0x0800)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0xF000) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RX_UNDER) || ((IT) == I2C_IT_RX_OVER) || \
+                           ((IT) == I2C_IT_RX_FULL) || ((IT) == I2C_IT_TX_OVER) || \
+                           ((IT) == I2C_IT_TX_EMPTY) || ((IT) == I2C_IT_RD_REQ) || \
+                           ((IT) == I2C_IT_TX_ABRT) || ((IT) == I2C_IT_RX_DONE) || \
+                           ((IT) == I2C_IT_ACTIVITY) || ((IT) == I2C_IT_STOP_DET) || \
+                           ((IT) == I2C_IT_START_DET) || ((IT) == I2C_IT_GEN_CALL))
+/**
+* @}
+*/
+
+/** @defgroup I2C_flags_definition
+* @{
+*/
+
+
+
+#define I2C_FLAG_RX_UNDER					((uint16_t)0x0001)
+#define I2C_FLAG_RX_OVER					((uint16_t)0x0002)
+#define I2C_FLAG_RX_FULL  				((uint16_t)0x0004)
+#define I2C_FLAG_TX_OVER					((uint16_t)0x0008)
+#define I2C_FLAG_TX_EMPTY					((uint16_t)0x0010)
+#define I2C_FLAG_RD_REQ						((uint16_t)0x0020)
+#define I2C_FLAG_TX_ABRT					((uint16_t)0x0040)
+#define I2C_FLAG_RX_DONE					((uint16_t)0x0080)
+#define I2C_FLAG_ACTIVITY					((uint16_t)0x0100)
+#define I2C_FLAG_STOP_DET					((uint16_t)0x0200)
+#define I2C_FLAG_START_DET				((uint16_t)0x0400)
+#define I2C_FLAG_GEN_CALL					((uint16_t)0x0800)
+
+
+
+
+
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xF000) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_RX_UNDER) || ((FLAG) == I2C_FLAG_RX_OVER) || \
+                               ((FLAG) == I2C_FLAG_RX_FULL) || ((FLAG) == I2C_FLAG_TX_OVER) || \
+                               ((FLAG) == I2C_FLAG_TX_EMPTY) || ((FLAG) == I2C_FLAG_RD_REQ) || \
+                               ((FLAG) == I2C_FLAG_TX_ABRT) || ((FLAG) == I2C_FLAG_RX_DONE) || \
+                               ((FLAG) == I2C_FLAG_ACTIVITY) || ((FLAG) == I2C_FLAG_STOP_DET) || \
+                               ((FLAG) == I2C_FLAG_START_DET) || ((FLAG) == I2C_FLAG_GEN_CALL))
+
+
+/** @defgroup I2C_Statusflags_definition
+* @{
+*/
+
+#define I2C_STATUS_FLAG_ACTIVITY				((uint16_t)0x8001)
+#define I2C_STATUS_FLAG_TFNF					((uint16_t)0x8002)
+#define I2C_STATUS_FLAG_TFE						((uint16_t)0x8004)
+#define I2C_STATUS_FLAG_RFNE					((uint16_t)0x8008)
+#define I2C_STATUS_FLAG_RFF						((uint16_t)0x8010)
+#define I2C_STATUS_FLAG_M_ACTIVITY				((uint16_t)0x8020)
+#define I2C_STATUS_FLAG_S_ACTIVITY				((uint16_t)0x8040)
+
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Events
+* @{
+*/
+
+
+#define I2C_EVENT_RX_UNDER				((uint32_t)0x0001)
+#define I2C_EVENT_RX_OVER				((uint32_t)0x0002)
+#define I2C_EVENT_RX_FULL  				((uint32_t)0x0004)
+#define I2C_EVENT_TX_OVER				((uint32_t)0x0008)
+#define I2C_EVENT_TX_EMPTY				((uint32_t)0x0010)
+#define I2C_EVENT_RD_REQ				((uint32_t)0x0020)
+#define I2C_EVENT_TX_ABRT				((uint32_t)0x0040)
+#define I2C_EVENT_RX_DONE				((uint32_t)0x0080)
+#define I2C_EVENT_ACTIVITY				((uint32_t)0x0100)
+#define I2C_EVENT_STOP_DET				((uint32_t)0x0200)
+#define I2C_EVENT_START_DET				((uint32_t)0x0400)
+#define I2C_EVENT_GEN_CALL				((uint32_t)0x0800)
+
+
+#define IS_I2C_EVENT(EVENT)  (((EVENT) == I2C_EVENT_RX_UNDER) || \
+                              ((EVENT) == I2C_EVENT_RX_OVER) || \
+                              ((EVENT) == I2C_EVENT_RX_FULL) || \
+                              ((EVENT) == I2C_EVENT_TX_OVER) || \
+                              ((EVENT) == I2C_EVENT_RD_REQ) || \
+                              ((EVENT) == I2C_EVENT_TX_ABRT) || \
+                              ((EVENT) == I2C_EVENT_RX_DONE) || \
+                              ((EVENT) == (I2C_EVENT_ACTIVITY | I2C_EVENT_STOP_DET)) || \
+                              ((EVENT) == (I2C_EVENT_START_DET | I2C_EVENT_GEN_CALL)))
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_own_address1
+* @{
+*/
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+* @}
+*/
+
+/** @defgroup I2C_clock_speed
+* @{
+*/
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Exported_Functions
+* @{
+*/
+
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+void I2C_SendLastDataOrStop(I2C_TypeDef* I2Cx, uint8_t Data);
+void I2C_ReadCmd(I2C_TypeDef* I2Cx);
+uint8_t I2C_ReadLastDataOrStop(I2C_TypeDef* I2Cx);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+
+#endif /*__HAL_I2C_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_iwdg.h

@@ -0,0 +1,131 @@
+/**
+******************************************************************************
+* @file    HAL_iwdg.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the IWDG
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_IWDG_H
+#define __HAL_IWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup IWDG
+* @{
+*/
+
+/** @defgroup IWDG_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Exported_Constants
+* @{
+*/
+
+/** @defgroup Write_access_to_IWDG_PR_and_IWDG_RLR_registers
+* @{
+*/
+
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+* @}
+*/
+
+/** @defgroup IWDG_prescaler
+* @{
+*/
+
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Flag
+* @{
+*/
+
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Exported_Functions
+* @{
+*/
+
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#endif /* __HAL_IWDG_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_misc.h

@@ -0,0 +1,166 @@
+/**
+******************************************************************************
+* @file    HAL_misc.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the
+*          miscellaneous firmware library functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup MISC
+* @{
+*/
+
+/** @defgroup MISC_Exported_Types
+* @{
+*/
+
+/**
+* @brief  NVIC Init Structure definition
+*/
+
+typedef struct
+{
+    uint8_t NVIC_IRQChannel;
+    uint8_t NVIC_IRQChannelPreemptionPriority;
+    uint8_t NVIC_IRQChannelSubPriority;
+    FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Exported_Constants
+* @{
+*/
+
+/** @defgroup Vector_Table_Base
+* @{
+*/
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+* @}
+*/
+
+/** @defgroup System_Low_Power
+* @{
+*/
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+* @}
+*/
+
+/** @defgroup Preemption_Priority_Group
+* @{
+*/
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /* 0 bits for pre-emption priority
+4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /* 1 bits for pre-emption priority
+3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /* 2 bits for pre-emption priority
+2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /* 3 bits for pre-emption priority
+1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /* 4 bits for pre-emption priority
+0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x0007FFFF)
+
+/**
+* @}
+*/
+
+/** @defgroup SysTick_clock_source
+* @{
+*/
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Exported_Functions
+* @{
+*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#endif /* __MISC_H */
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_pwr.h

@@ -0,0 +1,155 @@
+/**
+******************************************************************************
+* @file    HAL_pwr.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the PWR firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_PWR_H
+#define __HAL_PWR_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup PWR
+* @{
+*/
+
+/** @defgroup PWR_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Exported_Constants
+* @{
+*/
+
+
+/** @defgroup PVD_detection_level
+* @{
+*/
+
+#define PWR_PVDLevel_1V8          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V1          ((uint32_t)0x00000200)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000400)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x00000600)
+#define PWR_PVDLevel_3V0          ((uint32_t)0x00000800)
+#define PWR_PVDLevel_3V3          ((uint32_t)0x00000A00)
+#define PWR_PVDLevel_3V6          ((uint32_t)0x00000C00)
+#define PWR_PVDLevel_3V9          ((uint32_t)0x00000E00)
+#define PWR_PVDLevel_4V2          ((uint32_t)0x00001000)
+#define PWR_PVDLevel_4V5          ((uint32_t)0x00001200)
+#define PWR_PVDLevel_4V8          ((uint32_t)0x00001400)
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_1V8) || ((LEVEL) == PWR_PVDLevel_2V1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V7)|| \
+                                 ((LEVEL) == PWR_PVDLevel_3V0) || ((LEVEL) == PWR_PVDLevel_3V3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_3V6) || ((LEVEL) == PWR_PVDLevel_3V9)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4V2) || ((LEVEL) == PWR_PVDLevel_4V5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4V8))
+
+
+/**
+* @}
+*/
+
+/** @defgroup Regulator_state_is_STOP_mode
+* @{
+*/
+
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000002)
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+* @}
+*/
+
+/** @defgroup STOP_mode_entry
+* @{
+*/
+
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Flag
+* @{
+*/
+
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Exported_Functions
+* @{
+*/
+
+void PWR_DeInit(void);
+void PWR_BackupAccessCmd(FunctionalState NewState);
+void PWR_PVDCmd(FunctionalState NewState);
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#endif /* __HAL_PWR_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rcc.h

@@ -0,0 +1,425 @@
+/**
+******************************************************************************
+* @file    HAL_rcc.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the RCC firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_RCC_H
+#define __HAL_RCC_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup RCC
+* @{
+*/
+
+/** @defgroup RCC_Exported_Types
+* @{
+*/
+
+typedef struct
+{
+    uint32_t SYSCLK_Frequency;
+    uint32_t HCLK_Frequency;
+    uint32_t PCLK1_Frequency;
+    uint32_t PCLK2_Frequency;
+    uint32_t ADCCLK_Frequency;
+} RCC_ClocksTypeDef;
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Exported_Constants
+* @{
+*/
+
+/** @defgroup HSE_configuration
+* @{
+*/
+
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+
+/**
+* @}
+*/
+
+/** @defgroup PLL_entry_clock_source
+* @{
+*/
+
+#define RCC_PLLSource_HSI_Div4           ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div1) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE_Div2))
+/**
+* @}
+*/
+
+
+/** @defgroup System_clock_source
+* @{
+*/
+
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+* @}
+*/
+
+/** @defgroup AHB_clock_source
+* @{
+*/
+
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+* @}
+*/
+
+/** @defgroup APB1_APB2_clock_source
+* @{
+*/
+
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+
+/**
+* @}
+*/
+
+/** @defgroup PLL_multiplication_factor
+* @{
+*/
+
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
+                             ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
+                             ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
+                             ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
+                             ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
+                             ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
+                             ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
+                             ((MUL) == RCC_PLLMul_16))
+
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Interrupt_source
+* @{
+*/
+
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
+
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
+/**
+* @}
+*/
+
+/** @defgroup USB_clock_source
+* @{
+*/
+
+
+#define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div2     ((uint8_t)0x01)
+#define RCC_USBCLKSource_PLLCLK_Div3     ((uint8_t)0x02)
+#define RCC_USBCLKSource_PLLCLK_Div4     ((uint8_t)0x03)
+#define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \
+                                      ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2))
+/**
+* @}
+*/
+
+/** @defgroup ADC_clock_source
+* @{
+*/
+
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
+                               ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
+/**
+* @}
+*/
+
+/** @defgroup LSE_configuration
+* @{
+*/
+
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+* @}
+*/
+
+/** @defgroup RTC_clock_source
+* @{
+*/
+
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))
+/**
+* @}
+*/
+
+/** @defgroup AHB_peripheral
+* @{
+*/
+
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+//#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))
+/**
+* @}
+*/
+
+/** @defgroup APB2_peripheral
+* @{
+*/
+
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+
+#define RCC_APB2Periph_UART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ALL               ((uint32_t)0x0003FFFD)
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00))
+/**
+* @}
+*/
+
+/** @defgroup APB1_peripheral
+* @{
+*/
+
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+
+#define RCC_APB1Periph_UART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_UART3            ((uint32_t)0x00040000)
+
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1               ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define RCC_APB1Periph_ALL               ((uint32_t)0x3AFEC83F)
+
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00))
+/**
+* @}
+*/
+
+/** @defgroup Clock_source_to_output_on_MCO_pin
+* @{
+*/
+
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+#define RCC_MCO_LSI                      ((uint8_t)0x02)
+#define RCC_MCO_LSE                      ((uint8_t)0x03)
+#define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
+                         ((MCO) == RCC_MCO_SYSCLK)  || ((MCO) == RCC_MCO_HSE) || \
+                         ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\
+                         ((MCO) == RCC_MCO_LSE))
+/**
+* @}
+*/
+
+/** @defgroup RCC_Flag
+* @{
+*/
+
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \
+                           ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \
+                           ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \
+                           ((FLAG) == RCC_FLAG_LPWRRST))
+
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Exported_Functions
+* @{
+*/
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#endif /* __HAL_RCC_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_rtc.h

@@ -0,0 +1,135 @@
+/**
+******************************************************************************
+* @file    HAL_rtc.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the RTC firmware
+*          library.
+******************************************************************************
+* @attention
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+******************************************************************************
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_RTC_H
+#define __HAL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup
+* @{
+*/
+
+/** @addtogroup RTC
+* @{
+*/
+
+/** @defgroup RTC_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Exported_Constants
+* @{
+*/
+
+/** @defgroup RTC_interrupts_define
+* @{
+*/
+
+#define RTC_IT_OW            ((uint16_t)0x0004)  /*!< Overflow interrupt */
+#define RTC_IT_ALR           ((uint16_t)0x0002)  /*!< Alarm interrupt */
+#define RTC_IT_SEC           ((uint16_t)0x0001)  /*!< Second interrupt */
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \
+                           ((IT) == RTC_IT_SEC))
+/**
+* @}
+*/
+
+/** @defgroup RTC_interrupts_flags
+* @{
+*/
+
+#define RTC_FLAG_RTOFF       ((uint16_t)0x0020)  /*!< RTC Operation OFF flag */
+#define RTC_FLAG_RSF         ((uint16_t)0x0008)  /*!< Registers Synchronized flag */
+#define RTC_FLAG_OW          ((uint16_t)0x0004)  /*!< Overflow flag */
+#define RTC_FLAG_ALR         ((uint16_t)0x0002)  /*!< Alarm flag */
+#define RTC_FLAG_SEC         ((uint16_t)0x0001)  /*!< Second flag */
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \
+                               ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \
+                               ((FLAG) == RTC_FLAG_SEC))
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Exported_Functions
+* @{
+*/
+
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void RTC_EnterConfigMode(void);
+void RTC_ExitConfigMode(void);
+uint32_t  RTC_GetCounter(void);
+void RTC_SetCounter(uint32_t CounterValue);
+void RTC_SetPrescaler(uint32_t PrescalerValue);
+void RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t  RTC_GetDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);
+void RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HAL_RTC_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_spi.h

@@ -0,0 +1,418 @@
+/**
+******************************************************************************
+* @file    HAL_spi.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the SPI firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_SPI_H
+#define __HAL_SPI_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup SPI
+* @{
+*/
+
+/** @defgroup SPI_Exported_Types
+* @{
+*/
+
+/**
+* @brief  SPI Init structure definition
+*/
+
+typedef struct
+{
+    uint16_t SPI_Mode;
+    uint16_t SPI_DataSize;
+    uint16_t SPI_DataWidth;
+    uint16_t SPI_CPOL;
+    uint16_t SPI_CPHA;
+    uint16_t SPI_NSS;
+    uint16_t SPI_BaudRatePrescaler;
+    uint16_t SPI_FirstBit;
+} SPI_InitTypeDef;
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Exported_Constants
+* @{
+*/
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == SPI0_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == SPI1_BASE))
+
+#define IS_SPI_2_PERIPH(PERIPH) ((*(uint32_t*)&(PERIPH)) == SPI1_BASE)
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_master_slave_mode
+* @{
+*/
+
+#define SPI_Mode_Master                 ((uint16_t)0x0004)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+* @}
+*/
+
+/** @defgroup SPI_data_size
+* @{
+*/
+
+#define SPI_DataSize_32b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_32b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+
+/**
+* @}
+*/
+
+
+/** @defgroup SPI_7bit_8bit data width
+* @{
+*/
+
+#define SPI_DataWidth_1b                  ((uint16_t)0x0001)
+#define SPI_DataWidth_2b                  ((uint16_t)0x0002)
+#define SPI_DataWidth_3b                  ((uint16_t)0x0003)
+#define SPI_DataWidth_4b                  ((uint16_t)0x0004)
+#define SPI_DataWidth_5b                  ((uint16_t)0x0005)
+#define SPI_DataWidth_6b                  ((uint16_t)0x0006)
+#define SPI_DataWidth_7b                  ((uint16_t)0x0007)
+#define SPI_DataWidth_8b                  ((uint16_t)0x0008)
+#define SPI_DataWidth_9b                  ((uint16_t)0x0009)
+#define SPI_DataWidth_10b                 ((uint16_t)0x000a)
+#define SPI_DataWidth_11b                 ((uint16_t)0x000b)
+#define SPI_DataWidth_12b                 ((uint16_t)0x000c)
+#define SPI_DataWidth_13b                 ((uint16_t)0x000d)
+#define SPI_DataWidth_14b                 ((uint16_t)0x000e)
+#define SPI_DataWidth_15b                 ((uint16_t)0x000f)
+#define SPI_DataWidth_16b                 ((uint16_t)0x0010)
+#define SPI_DataWidth_17b                 ((uint16_t)0x0011)
+#define SPI_DataWidth_18b                 ((uint16_t)0x0012)
+#define SPI_DataWidth_19b                 ((uint16_t)0x0013)
+#define SPI_DataWidth_20b                 ((uint16_t)0x0014)
+#define SPI_DataWidth_21b                 ((uint16_t)0x0015)
+#define SPI_DataWidth_22b                 ((uint16_t)0x0016)
+#define SPI_DataWidth_23b                 ((uint16_t)0x0017)
+#define SPI_DataWidth_24b                 ((uint16_t)0x0018)
+#define SPI_DataWidth_25b                 ((uint16_t)0x0019)
+#define SPI_DataWidth_26b                 ((uint16_t)0x001a)
+#define SPI_DataWidth_27b                 ((uint16_t)0x001b)
+#define SPI_DataWidth_28b                 ((uint16_t)0x001c)
+#define SPI_DataWidth_29b                 ((uint16_t)0x001d)
+#define SPI_DataWidth_30b                 ((uint16_t)0x001e)
+#define SPI_DataWidth_31b                 ((uint16_t)0x001f)
+#define SPI_DataWidth_32b                 ((uint16_t)0x0000)
+#define IS_SPI_DATAWIDRH(WIDTH) (((WIDTH) == SPI_DataWidth_1b) || ((WIDTH) == SPI_DataWidth_2b)||\
+                                 ((WIDTH) == SPI_DataWidth_3b)||((WIDTH) == SPI_DataWidth_4b)||\
+                                 ((WIDTH) == SPI_DataWidth_5b)||((WIDTH) == SPI_DataWidth_6b)||\
+                                 ((WIDTH) == SPI_DataWidth_7b)||((WIDTH) == SPI_DataWidth_8b)||\
+                                 ((WIDTH) == SPI_DataWidth_9b)||((WIDTH) == SPI_DataWidth_10b)||\
+                                 ((WIDTH) == SPI_DataWidth_11b)||((WIDTH) == SPI_DataWidth_12b)||\
+                                 ((WIDTH) == SPI_DataWidth_13b)||((WIDTH) == SPI_DataWidth_14b)||\
+                                 ((WIDTH) == SPI_DataWidth_15b)||((WIDTH) == SPI_DataWidth_16b)||\
+                                 ((WIDTH) == SPI_DataWidth_17b)||((WIDTH) == SPI_DataWidth_18b)||\
+                                 ((WIDTH) == SPI_DataWidth_19b)||((WIDTH) == SPI_DataWidth_20b)||\
+                                 ((WIDTH) == SPI_DataWidth_21b)||((WIDTH) == SPI_DataWidth_22b)||\
+                                 ((WIDTH) == SPI_DataWidth_23b)||((WIDTH) == SPI_DataWidth_24b)||\
+                                 ((WIDTH) == SPI_DataWidth_25b)||((WIDTH) == SPI_DataWidth_26b)||\
+                                 ((WIDTH) == SPI_DataWidth_27b)||((WIDTH) == SPI_DataWidth_28b)||\
+                                 ((WIDTH) == SPI_DataWidth_29b)||((WIDTH) == SPI_DataWidth_30b)||\
+                                 ((WIDTH) == SPI_DataWidth_31b)||((WIDTH) == SPI_DataWidth_32b)||)
+/**
+* @}
+*/
+
+
+/** @defgroup SPI_Clock_Polarity
+* @{
+*/
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+* @}
+*/
+
+/** @defgroup SPI_Clock_Phase
+* @{
+*/
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0001)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0000)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+* @}
+*/
+
+/** @defgroup SPI_Slave_Select_management
+* @{
+*/
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0000)
+#define SPI_NSS_Hard                    ((uint16_t)0x0400)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_NSS_internal_software_mangement
+* @{
+*/
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0001)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFFFE)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_BaudRate_Prescaler_
+* @{
+*/
+
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0002)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0004)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0040)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0080)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0100)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+        ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+* @}
+*/
+
+/** @defgroup SPI_MSB_LSB_transmission
+* @{
+*/
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0004)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_DMA_transfer_requests
+* @{
+*/
+
+#define SPI_DMAReq_EN               		((uint16_t)0x0200)
+#define IS_SPI_DMAREQ(DMAREQ) ((DMAREQ)  == SPI_DMAReq_EN)
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI TX Fifo and RX Fifo trigger level
+* @{
+*/
+#define SPI_TXTLF               		    ((uint16_t)0x0080)
+#define SPI_RXTLF               		    ((uint16_t)0x0020)
+#define IS_SPI_FIFOTRIGGER(TRIGGER) (((TRIGGER)  == SPI_TXTLF) && ((TRIGGER) == SPI_RXTLF))
+
+
+
+
+
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_NSS_internal_software_mangement
+* @{
+*/
+
+#define SPI_CS_BIT0                   ((uint16_t)0xfffe)
+#define SPI_CS_BIT1                   ((uint16_t)0xfffd)
+#define SPI_CS_BIT2                   ((uint16_t)0xfffb)
+#define SPI_CS_BIT3                   ((uint16_t)0xfff7)
+#define SPI_CS_BIT4                   ((uint16_t)0xffef)
+#define SPI_CS_BIT5                   ((uint16_t)0xffdf)
+#define SPI_CS_BIT6                   ((uint16_t)0xffbf)
+#define SPI_CS_BIT7                   ((uint16_t)0xff7f)
+#define IS_SPI_CS(CS)        (((CS) == SPI_CS_BIT0) || ((CS) == SPI_CS_BIT1)||\
+                              ((CS) == SPI_CS_BIT2) || ((CS) == SPI_CS_BIT3)||\
+                              ((CS) == SPI_CS_BIT4) || ((CS) == SPI_CS_BIT5)||\
+                              ((CS) == SPI_CS_BIT6) || ((CS) == SPI_CS_BIT7))
+/**
+* @}
+*/
+
+
+/** @defgroup SPI_direction_transmit_receive
+* @{
+*/
+
+#define SPI_Direction_Rx                ((uint16_t)0x0010)
+#define SPI_Direction_Tx                ((uint16_t)0x0008)
+#define SPI_Disable_Tx                	((uint16_t)0xfff7)
+#define SPI_Disable_Rx                	((uint16_t)0xffef)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx) || \
+                                     ((DIRECTION) == SPI_Disable_Tx) || \
+                                     ((DIRECTION) == SPI_Disable_Rx))
+/**
+* @}
+*/
+
+/** @defgroup SPI_interrupts_definition
+* @{
+*/
+#define SPI_INT_EN                    ((uint16_t)0x0002)
+
+#define SPI_IT_TX                     ((uint8_t)0x01)
+#define SPI_IT_RX                     ((uint8_t)0x02)
+
+#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TX) || \
+                              ((IT) == SPI_IT_RX))
+
+#define SPI_IT_UNDERRUN                ((uint8_t)0x04)
+#define SPI_IT_RXOVER                  ((uint8_t)0x08)
+#define SPI_IT_RXMATCH                 ((uint8_t)0x10)
+#define SPI_IT_RXFULL                  ((uint8_t)0x20)
+#define SPI_IT_TXEPT                   ((uint8_t)0x40)
+
+#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \
+                           ((IT) == SPI_IT_UNDERRUN) || ((IT) == SPI_IT_RXOVER) || \
+                           ((IT) == SPI_IT_RXMATCH) || ((IT) == SPI_IT_RXFULL) || \
+                           ((IT) == SPI_IT_TXEPT))
+/**
+* @}
+*/
+
+/** @defgroup SPI_flags_definition
+* @{
+*/
+
+
+#define SPI_FLAG_RXAVL                ((uint16_t)0x0002)
+#define SPI_FLAG_TXEPT                ((uint16_t)0x0001)
+
+#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_RXAVL) || \
+                               ((FLAG) == SPI_FLAG_TXEPT))
+
+/**
+* @}
+*/
+
+/** @defgroup SPI mode tx data transmit phase adjust set
+*in slave mode according to txedge bit of CCTL register
+* @{
+*/
+
+
+#define SPI_SlaveAdjust_FAST          ((uint16_t)0x0020)
+#define SPI_SlaveAdjust_LOW           ((uint16_t)0xffdf)
+
+#define IS_SPI_SlaveAdjust(ADJUST) (((ADJUST) == SPI_SlaveAdjust_FAST) || \
+                                    ((ADJUST) == SPI_SlaveAdjust_LOW))
+
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Exported_Functions
+* @{
+*/
+
+void SPI_DeInit(SPI_TypeDef* SPIx);
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState);
+void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState);
+void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState);
+void SPI_SendData(SPI_TypeDef* SPIx, uint32_t Data);
+uint32_t SPI_ReceiveData(SPI_TypeDef* SPIx);
+void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected, FunctionalState NewState);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG);
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT);
+void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number);
+void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue);
+#endif /*__HAL_SPI_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_tim.h

@@ -0,0 +1,1036 @@
+/**
+******************************************************************************
+* @file    HAL_tim.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the TIM firmware
+*          library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_TIM_H
+#define __HAL_TIM_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup TIM
+* @{
+*/
+
+/** @defgroup TIM_Exported_Types
+* @{
+*/
+
+/**
+* @brief  TIM Time Base Init structure definition
+*/
+
+typedef struct
+{
+    uint16_t TIM_Prescaler;
+    uint16_t TIM_CounterMode;
+    uint16_t TIM_Period;
+    uint16_t TIM_ClockDivision;
+    uint8_t TIM_RepetitionCounter;
+} TIM_TimeBaseInitTypeDef;
+
+/**
+* @brief  TIM Output Compare Init structure definition
+*/
+
+typedef struct
+{
+    uint16_t TIM_OCMode;
+    uint16_t TIM_OutputState;
+    uint16_t TIM_OutputNState;
+    uint16_t TIM_Pulse;
+    uint16_t TIM_OCPolarity;
+    uint16_t TIM_OCNPolarity;
+    uint16_t TIM_OCIdleState;
+    uint16_t TIM_OCNIdleState;
+} TIM_OCInitTypeDef;
+
+/**
+* @brief  TIM Input Capture Init structure definition
+*/
+
+typedef struct
+{
+    uint16_t TIM_Channel;
+    uint16_t TIM_ICPolarity;
+    uint16_t TIM_ICSelection;
+    uint16_t TIM_ICPrescaler;
+    uint16_t TIM_ICFilter;
+} TIM_ICInitTypeDef;
+
+/**
+* @brief  BDTR structure definition
+*/
+
+typedef struct
+{
+    uint16_t TIM_OSSRState;
+    uint16_t TIM_OSSIState;
+    uint16_t TIM_LOCKLevel;
+    uint16_t TIM_DeadTime;
+    uint16_t TIM_Break;
+    uint16_t TIM_BreakPolarity;
+    uint16_t TIM_AutomaticOutput;
+} TIM_BDTRInitTypeDef;
+
+/** @defgroup TIM_Exported_constants
+* @{
+*/
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
+                                   ((*(uint32_t*)&(PERIPH)) == TIM4_BASE))
+
+#define IS_TIM_18_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE))
+#define IS_TIM_123458_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \
+                                      ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \
+                                      ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
+                                      ((*(uint32_t*)&(PERIPH)) == TIM4_BASE))
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes
+* @{
+*/
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+* @}
+*/
+
+/** @defgroup TIM_One_Pulse_Mode
+* @{
+*/
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Channel
+* @{
+*/
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+        ((CHANNEL) == TIM_Channel_2) || \
+        ((CHANNEL) == TIM_Channel_3))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Clock_Division_CKD
+* @{
+*/
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Counter_Mode
+* @{
+*/
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_Polarity
+* @{
+*/
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_N_Polarity
+* @{
+*/
+
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_states
+* @{
+*/
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_N_States
+* @{
+*/
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Capture_Compare_States
+* @{
+*/
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Capture_Compare_N_States
+* @{
+*/
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+* @}
+*/
+
+/** @defgroup Break_Input_enable_disable
+* @{
+*/
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+* @}
+*/
+
+/** @defgroup Break_Polarity
+* @{
+*/
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+        ((POLARITY) == TIM_BreakPolarity_High))
+/**
+* @}
+*/
+
+/** @defgroup TIM_AOE_Bit_Set_Reset
+* @{
+*/
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+        ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+* @}
+*/
+
+/** @defgroup Lock_levels
+* @{
+*/
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+* @}
+*/
+
+/** @defgroup OSSI:_Off-State_Selection_for_Idle_mode_states
+* @{
+*/
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+* @}
+*/
+
+/** @defgroup OSSR:_Off-State_Selection_for_Run_mode_states
+* @{
+*/
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_Idle_State
+* @{
+*/
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Output_Compare_N_Idle_State
+* @{
+*/
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Input_Capture_Polarity
+* @{
+*/
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Input_Capture_Selection
+* @{
+*/
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001)
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002)
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003)
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Input_Capture_Prescaler
+* @{
+*/
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000)
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004)
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008)
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C)
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+* @}
+*/
+
+/** @defgroup TIM_interrupt_sources
+* @{
+*/
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+#define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
+        (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
+        (((TIM_IT) & (uint16_t)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
+         (((TIM_IT) & (uint16_t)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
+         (((TIM_IT) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000)))
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+* @}
+*/
+
+/** @defgroup TIM_DMA_Base_address
+* @{
+*/
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR))
+/**
+* @}
+*/
+
+/** @defgroup TIM_DMA_Burst_Length
+* @{
+*/
+
+#define TIM_DMABurstLength_1Byte           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Bytes          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Bytes          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Bytes          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Bytes          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Bytes          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Bytes          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Bytes          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Bytes          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Bytes         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Bytes         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Bytes         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Bytes         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Bytes         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Bytes         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Bytes         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Bytes         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Bytes         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Bytes) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Bytes))
+/**
+* @}
+*/
+
+/** @defgroup TIM_DMA_sources
+* @{
+*/
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+#define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
+        (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
+        (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
+         (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
+         (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000)))
+/**
+* @}
+*/
+
+/** @defgroup TIM_External_Trigger_Prescaler
+* @{
+*/
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+        ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+        ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+        ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Internal_Trigger_Selection
+* @{
+*/
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+        ((SELECTION) == TIM_TS_ITR1) || \
+        ((SELECTION) == TIM_TS_ITR2) || \
+        ((SELECTION) == TIM_TS_ITR3) || \
+        ((SELECTION) == TIM_TS_TI1F_ED) || \
+        ((SELECTION) == TIM_TS_TI1FP1) || \
+        ((SELECTION) == TIM_TS_TI2FP2) || \
+        ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+        ((SELECTION) == TIM_TS_ITR1) || \
+        ((SELECTION) == TIM_TS_ITR2) || \
+        ((SELECTION) == TIM_TS_ITR3))
+/**
+* @}
+*/
+
+/** @defgroup TIM_TIx_External_Clock_Source
+* @{
+*/
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
+                                      ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
+/**
+* @}
+*/
+
+/** @defgroup TIM_External_Trigger_Polarity
+* @{
+*/
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Prescaler_Reload_Mode
+* @{
+*/
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+        ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Forced_Action
+* @{
+*/
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Encoder_Mode
+* @{
+*/
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+* @}
+*/
+
+
+/** @defgroup TIM_Event_Source
+* @{
+*/
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
+#define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
+        (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
+        (((EVENT) & (uint16_t)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
+         (((EVENT) & (uint16_t)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
+         (((EVENT) & (uint16_t)0xFFFE) == 0x0000) && ((EVENT) != 0x0000)))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Update_Source
+* @{
+*/
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000)
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001)
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Ouput_Compare_Preload_State
+* @{
+*/
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Ouput_Compare_Fast_State
+* @{
+*/
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Ouput_Compare_Clear_State
+* @{
+*/
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Trigger_Output_Source
+* @{
+*/
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+#define IS_TIM_PERIPH_TRGO(PERIPH, TRGO)  (((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+        (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+        (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
+        (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+        ((TRGO) == TIM_TRGOSource_Reset)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_Enable)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_Update)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_OC1)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\
+        ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\
+          (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \
+          (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \
+         ((TRGO) == TIM_TRGOSource_OC4Ref)))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Slave_Mode
+* @{
+*/
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Master_Slave_Mode
+* @{
+*/
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+* @}
+*/
+
+/** @defgroup TIM_Flags
+* @{
+*/
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+#define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\
+        (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \
+        (((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \
+         (((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\
+        (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \
+         (((TIM_FLAG) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000)))
+#define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG)  (((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) ||\
+        ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \
+        ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\
+        (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\
+         ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \
+         ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\
+        ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
+          ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) ||\
+          ((*(uint32_t*)&(PERIPH))==TIM1_BASE)|| ((*(uint32_t*)&(PERIPH))==TIM8_BASE) || \
+          ((*(uint32_t*)&(PERIPH))==TIM7_BASE) || ((*(uint32_t*)&(PERIPH))==TIM6_BASE)) && \
+         (((TIM_FLAG) == TIM_FLAG_Update))) ||\
+        ((((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE)) &&\
+         (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\
+        ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \
+          ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \
+          ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\
+         (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\
+          ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF))))
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Input_Capture_Filer_Value
+* @{
+*/
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+* @}
+*/
+
+/** @defgroup TIM_External_Trigger_Filter
+* @{
+*/
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Exported_Functions
+* @{
+*/
+
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+
+#endif /*__HAL_TIM_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/
+

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_uart.h

@@ -0,0 +1,247 @@
+/**
+******************************************************************************
+* @file    HAL_uart.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the UART
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_UART_H
+#define __HAL_UART_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup UART
+* @{
+*/
+
+/** @defgroup UART_Exported_Types
+* @{
+*/
+
+/**
+* @brief  UART Init Structure definition
+*/
+
+typedef struct
+{
+    uint32_t UART_BaudRate;
+    uint16_t UART_WordLength;
+    uint16_t UART_StopBits;
+    uint16_t UART_Parity;
+    uint16_t UART_Mode;
+    uint16_t UART_HardwareFlowControl;
+} UART_InitTypeDef;
+
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Exported_Constants
+* @{
+*/
+
+#define IS_UART_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == UART3_BASE))
+#define IS_UART_123_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == UART1_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == UART2_BASE) || \
+                                    ((*(uint32_t*)&(PERIPH)) == UART3_BASE))
+
+/** @defgroup UART_Word_Length
+* @{
+*/
+
+#define UART_WordLength_5b                  ((uint16_t)0x0000)
+#define UART_WordLength_6b                  ((uint16_t)0x0010)
+#define UART_WordLength_7b                  ((uint16_t)0x0020)
+#define UART_WordLength_8b                  ((uint16_t)0x0030)
+
+
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \
+                                     ((LENGTH) == UART_WordLength_6b) || \
+                                     ((LENGTH) == UART_WordLength_7b) || \
+                                     ((LENGTH) == UART_WordLength_8b))
+/**
+* @}
+*/
+
+/** @defgroup UART_Stop_Bits
+* @{
+*/
+
+#define UART_StopBits_1                     ((uint16_t)0x0000)
+#define UART_StopBits_2                     ((uint16_t)0x0004)
+
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
+                                    ((STOPBITS) == UART_StopBits_2))
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Parity
+* @{
+*/
+
+#define UART_Parity_No                      ((uint16_t)0x0000)
+#define UART_Parity_Even                    ((uint16_t)0x0003)
+#define UART_Parity_Odd                     ((uint16_t)0x0001)
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
+                                ((PARITY) == UART_Parity_Even) || \
+                                ((PARITY) == UART_Parity_Odd))
+/**
+* @}
+*/
+
+/** @defgroup UART_Mode
+* @{
+*/
+
+#define UART_Mode_Rx                        ((uint16_t)0x0008)
+#define UART_Mode_Tx                        ((uint16_t)0x0010)
+#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFE7) == 0x00) && ((MODE) != (uint16_t)0x00))
+
+#define UART_EN                             ((uint16_t)0x0001)
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Hardware_Flow_Control
+* @{
+*/
+#define UART_HardwareFlowControl_None       ((uint16_t)0x0000)
+
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+    (((CONTROL) == UART_HardwareFlowControl_None) || \
+     ((CONTROL) == UART_HardwareFlowControl_RTS) || \
+     ((CONTROL) == UART_HardwareFlowControl_CTS) || \
+     ((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
+
+/** @defgroup UART_Interrupt_definition
+* @{
+*/
+
+
+#define UART_IT_ERR            ((uint16_t)0x0020)
+#define UART_IT_PE             ((uint16_t)0x0010)
+#define UART_OVER_ERR          ((uint16_t)0x0008)
+#define UART_TIMEOUT_ERR       ((uint16_t)0x0004)
+#define UART_IT_RXIEN          ((uint16_t)0x0002)
+#define UART_IT_TXIEN          ((uint16_t)0x0001)
+
+#define IS_UART_CONFIG_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \
+                               ((IT) == UART_IT_RXIEN) || ((IT) == UART_IT_ERR))
+
+#define IS_UART_GET_IT(IT) (((IT) == UART_IT_PE) || ((IT) == UART_IT_TXIEN) || \
+                            ((IT) == UART_IT_ERR) || ((IT) == UART_IT_RXIEN) || \
+                            ((IT) == UART_OVER_ERR) || ((IT) == UART_TIMEOUT_ERR))
+
+#define IS_UART_CLEAR_IT(IT) ((IT) == UART_IT_RXIEN)
+
+
+/**
+* @}
+*/
+
+/** @defgroup UART_DMA_Requests
+* @{
+*/
+#define UART_DMAReq_EN                      ((uint16_t)0x0002)
+
+#define IS_UART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFD) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+* @}
+*/
+
+
+/** @defgroup UART_Flags
+* @{
+*/
+
+
+#define UART_FLAG_TXEMPTY                   ((uint16_t)0x0008)
+#define UART_FLAG_TXFULL                    ((uint16_t)0x0004)
+#define UART_FLAG_RXAVL                     ((uint16_t)0x0002)
+#define UART_FLAG_TXEPT                     ((uint16_t)0x0001)
+
+
+#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_TXEMPTY) || ((FLAG) == UART_FLAG_TXFULL) || \
+                            ((FLAG) == UART_FLAG_RXAVL) || ((FLAG) == UART_FLAG_TXEPT))
+
+
+#define IS_UART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x00FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_UART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Exported_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Exported_Functions
+* @{
+*/
+
+void UART_DeInit(UART_TypeDef* UARTx);
+void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
+void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
+void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
+void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState);
+void UART_SendData(UART_TypeDef* UARTx, uint16_t Data);
+uint16_t UART_ReceiveData(UART_TypeDef* UARTx);
+FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG);
+void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG);
+ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT);
+void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT);
+
+#endif /* __HAL_UART_H */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/inc/HAL_wwdg.h

@@ -0,0 +1,106 @@
+/**
+******************************************************************************
+* @file    HAL_wwdg.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the functions prototypes for the WWDG
+*          firmware library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HAL_WWDG_H
+#define __HAL_WWDG_H
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_device.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @addtogroup WWDG
+* @{
+*/
+
+/** @defgroup WWDG_Exported_Types
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Exported_Constants
+* @{
+*/
+
+/** @defgroup WWDG_Prescaler
+* @{
+*/
+
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Exported_Macros
+* @{
+*/
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Exported_Functions
+* @{
+*/
+
+void WWDG_DeInit(void);
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+void WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#endif /* __HAL_WWDG_H */
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_adc.c

@@ -0,0 +1,785 @@
+/**
+******************************************************************************
+* @file    HAL_adc.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the ADC firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_adc.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup ADC
+* @brief ADC driver modules
+* @{
+*/
+
+/** @defgroup ADC_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Private_Defines
+* @{
+*/
+
+
+/* ADCR register Mask */
+#define ADCR_CLEAR_Mask              ((uint32_t)0xFFFFF183)
+
+/* ADCFG register Mask */
+#define ADCFG_CLEAR_Mask             ((uint32_t)0xFFFFFF8F)
+
+/* ADC ADEN mask */
+#define ADCFG_ADEN_Set                ((uint32_t)0x00000001)
+#define ADCFG_ADEN_Reset              ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define ADCR_DMA_Set                 ((uint32_t)0x00000008)
+#define ADCR_DMA_Reset               ((uint32_t)0xFFFFFFF7)
+
+/* ADC Software start mask */
+#define ADCR_SWSTART_Set     ((uint32_t)0x00000100)
+#define ADCR_SWSTART_Reset   ((uint32_t)0xFFFFFEFF)
+
+/* ADC EXTTRIG mask */
+#define ADCR_EXTTRIG_Set             ((uint32_t)0x00000004)
+#define ADCR_EXTTRIG_Reset            ((uint32_t)0xFFFFFFFB)
+
+/*seletec channle enable */
+#define CHEN0_ENABLE								((uint32_t)0x00000001)
+#define CHEN1_ENABLE								((uint32_t)0x00000002)
+#define CHEN2_ENABLE								((uint32_t)0x00000004)
+#define CHEN3_ENABLE								((uint32_t)0x00000008)
+#define CHEN4_ENABLE								((uint32_t)0x00000010)
+#define CHEN5_ENABLE								((uint32_t)0x00000020)
+#define CHEN6_ENABLE								((uint32_t)0x00000040)
+#define CHEN7_ENABLE								((uint32_t)0x00000080)
+#define CHEN8_ENABLE								((uint32_t)0x00000100)
+#define CHALL_ENABLE                				((uint32_t)0x000001ff)
+
+#define CHEN_DISABLE								((uint32_t)0xFFFFFE00)
+
+/* ADC EXTSEL mask */
+#define ADCR_EXTSEL_Reset           				((uint32_t)0xFFFFFF8F)
+
+/* ADC Analog watchdog enable mode mask */
+#define ADCFG_AWDMode_Reset           				((uint32_t)0xFFFFFFFD)
+
+/* ADC AWDCH mask */
+#define ADCR_AWDCH_Reset             				((uint32_t)0xFFFF0FFF)
+
+/* ADC TSPD mask */
+#define ADCHS_TSVREFE_Set            				((uint32_t)0x00000100)
+#define ADCHS_TSVREFE_Reset            				((uint32_t)0xFFFFFEFF)
+
+/* ADC1 DATA register base address */
+#define ADDATA_ADDRESS                  			((uint32_t)0x40012400)
+/**
+* @}
+*/
+
+/** @defgroup ADC_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup ADC_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the ADCx peripheral registers to their default
+*   reset values.
+* @param ADCx: where x can be 1, 2  to select the ADC peripheral.
+* @retval : None
+*/
+void ADC_DeInit(ADC_TypeDef* ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    switch (*(uint32_t*)&ADCx)
+    {
+        case ADC1_BASE:
+            /* Enable ADC1 reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+            /* Release ADC1 from reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+            break;
+
+        case ADC2_BASE:
+            /* Enable ADC2 reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);
+            /* Release ADC2 from reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the ADCx peripheral according to the specified parameters
+*   in the ADC_InitStruct.
+* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+* @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that
+*   contains the configuration information for the specified
+*   ADC peripheral.
+* @retval : None
+*/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+    uint32_t tmpreg1 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
+    assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+    assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
+    assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
+    assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
+    assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
+    /*---------------------------- ADCx ADCFG Configuration -----------------*/
+    /* Get the ADCx ADCFG value */
+    tmpreg1 = ADCx->ADCFG;
+    /* Clear ADCPRE bits */
+    tmpreg1 &= ADCFG_CLEAR_Mask;
+    /* Configure ADCx: AD convertion prescare*/
+    /* Set ADCPRE bit according to ADC_PRESCARE value */
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_PRESCARE) | ADC_InitStruct->ADC_Resolution;
+    /* Write to ADCx ADCFG */
+    ADCx->ADCFG = tmpreg1;
+
+    /*---------------------------- ADCx ADCR Configuration -----------------*/
+    /* Get the ADCx ADCR value */
+    tmpreg1 = ADCx->ADCR;
+    /* Clear ALIGN , ADMD, and TRGEN and TRGSEL bits */
+    tmpreg1 &= ADCR_CLEAR_Mask;
+    /* Configure ADCx: external trigger event and AD conversion mode and ALIGN*/
+    /* Set ALIGN bit according to ADC_DataAlign value */
+    /* Set TRGEN bits according to ADC_ContinuousConvMode value */
+    /* Set TRGSEL bits according to ADC_ExternalTrigConv value */
+
+    tmpreg1 |= ((uint32_t)ADC_InitStruct->ADC_DataAlign) | ADC_InitStruct->ADC_ExternalTrigConv |
+               ((uint32_t)ADC_InitStruct->ADC_Mode) ;
+
+    /* Write to ADCx ADCR */
+    ADCx->ADCR = tmpreg1;
+
+}
+
+/**
+* @brief  Fills each ADC_InitStruct member with its default value.
+* @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+    /* Initialize the ADC_Resolution values */
+    ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+    /* Initialize the ADC_PRESCARE values */
+    ADC_InitStruct->ADC_PRESCARE = ADC_PCLK2_PRESCARE_2;
+    /* Initialize the ADC_Mode member */
+    ADC_InitStruct->ADC_Mode = ADC_Mode_Single;
+    /* Initialize the ADC_ContinuousConvMode member */
+    ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+    /* Initialize the ADC_ExternalTrigConv member */
+    ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+    /* Initialize the ADC_DataAlign member */
+    ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+    /* Initialize the ADC_NbrOfChannel member */
+
+}
+
+/**
+* @brief  Enables or disables the specified ADC peripheral.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param NewState: new state of the ADCx peripheral. This parameter
+*   can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the ADEN bit */
+        ADCx->ADCFG |= ADCFG_ADEN_Set;
+    }
+    else
+    {
+        /* Disable the selected ADC peripheral */
+        ADCx->ADCFG &= ADCFG_ADEN_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified ADC DMA request.
+* @param ADCx: where x can be 1 or 2 to select the ADC peripheral.
+* @param NewState: new state of the selected ADC DMA transfer.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_DMA_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC DMA request */
+        ADCx->ADCR |= ADCR_DMA_Set;
+    }
+    else
+    {
+        /* Disable the selected ADC DMA request */
+        ADCx->ADCR &= ADCR_DMA_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified ADC interrupts.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param ADC_IT: specifies the ADC interrupt sources to be enabled
+*   or disabled.
+*   This parameter can be any combination of the following values:
+* @arg ADC_IT_EOC: End of conversion interrupt mask
+* @arg ADC_IT_AWD: Analog watchdog interrupt mask
+* @param NewState: new state of the specified ADC interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_ADC_IT(ADC_IT));
+    /* Get the ADC IT index */
+    //itmask = (uint8_t)ADC_IT;
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC interrupts */
+        ADCx->ADCR |= ADC_IT;
+    }
+    else
+    {
+        /* Disable the selected ADC interrupts */
+        ADCx->ADCR &= (~(uint32_t)ADC_IT);
+    }
+}
+
+/**
+* @brief  Enables or disables the selected ADC software start conversion .
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param NewState: new state of the selected ADC software start conversion.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC conversion on external event and start the selected
+        ADC conversion */
+        /*Set ADST bit*/
+        ADCx->ADCR |= ADCR_SWSTART_Set;
+    }
+    else
+    {
+        /* Disable the selected ADC conversion on external event and stop the selected
+        ADC conversion */
+        ADCx->ADCR &= ADCR_SWSTART_Reset;
+    }
+}
+
+/**
+* @brief  Gets the selected ADC Software start conversion Status.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @retval : The new state of ADC software start conversion (SET or RESET).
+*/
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    /* Check the status of ADST bit */
+    if ((ADCx->ADCR & ADCR_SWSTART_Set) != (uint32_t)RESET)
+    {
+        /* ADST bit is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADST bit is reset */
+        bitstatus = RESET;
+    }
+    /* Return the ADST bit status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Configures for the selected ADC  channel its corresponding
+*   rank in the sequencer and its sample time.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param ADC_Channel: the ADC channel to configure.
+*   This parameter can be one of the following values:
+* @arg ADC_Channel_0: ADC Channel0 selected
+* @arg ADC_Channel_1: ADC Channel1 selected
+* @arg ADC_Channel_2: ADC Channel2 selected
+* @arg ADC_Channel_3: ADC Channel3 selected
+* @arg ADC_Channel_4: ADC Channel4 selected
+* @arg ADC_Channel_5: ADC Channel5 selected
+* @arg ADC_Channel_6: ADC Channel6 selected
+* @arg ADC_Channel_7: ADC Channel7 selected
+* @arg ADC_Channel_8: ADC Channel8 selected
+* @retval : None
+*/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_CHANNEL(ADC_Channel));
+    assert_param(IS_ADC_REGULAR_RANK(Rank));
+    assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+    tmpreg = ADCx->ADCFG;
+    tmpreg &= ~(ADC_SMPR_SMP << 10);
+    ADCx->ADCFG = tmpreg | ((ADC_SampleTime & ADC_SMPR_SMP) << 10);
+    switch(ADC_Channel)
+    {
+        /* set the CHEN0 bit for channel 0 enable*/
+        case ADC_Channel_0: ADCx->ADCHS |= CHEN0_ENABLE;
+            break;
+        /* set the CHEN1 bit for channel 1 enable*/
+        case ADC_Channel_1: ADCx->ADCHS |= CHEN1_ENABLE;
+            break;
+        /* set the CHEN2 bit for channel 2 enable*/
+        case ADC_Channel_2: ADCx->ADCHS |= CHEN2_ENABLE;
+            break;
+        /* set the CHEN3 bit for channel 3 enable*/
+        case ADC_Channel_3: ADCx->ADCHS |= CHEN3_ENABLE;
+            break;
+        /* set the CHEN4 bit for channel 4 enable*/
+        case ADC_Channel_4: ADCx->ADCHS |= CHEN4_ENABLE;
+            break;
+        /* set the CHEN5 bit for channel 5 enable*/
+        case ADC_Channel_5: ADCx->ADCHS |= CHEN5_ENABLE;
+            break;
+        /* set the CHEN6 bit for channel 6 enable*/
+        case ADC_Channel_6: ADCx->ADCHS |= CHEN6_ENABLE;
+            break;
+        /* set the CHEN7 bit for channel 7 enable*/
+        case ADC_Channel_7: ADCx->ADCHS |= CHEN7_ENABLE;
+            break;
+        /* set the SENSOREN bit for channel 8 enable*/
+        case ADC_Channel_8: ADCx->ADCHS |= CHEN8_ENABLE;      //SENSOREN or VREFINT
+            break;
+        case ADC_Channel_All: ADCx->ADCHS |= CHALL_ENABLE;    //SENSOREN or VREFINT
+            break;
+        default:
+            ADCx->ADCHS &= CHEN_DISABLE;
+            break;
+    }
+}
+
+/**
+* @brief  Enables or disables the ADCx conversion through external trigger.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param NewState: new state of the selected ADC external trigger
+*   start of conversion.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC conversion on external event */
+        ADCx->ADCR |= ADCR_EXTTRIG_Set;
+    }
+    else
+    {
+        /* Disable the selected ADC conversion on external event */
+        ADCx->ADCR &= ADCR_EXTTRIG_Reset;
+    }
+}
+
+/**
+* @brief  Returns the last ADCx conversion result data for regular channel.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @retval : The Data conversion value.
+*/
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    /* Return the selected ADC conversion value */
+    return (uint16_t) ADCx->ADDATA;
+}
+
+/**
+* @brief  Returns the last ADC conversion result data in dual mode.
+* @retval : The Data conversion value.
+*/
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+    /* Return the dual mode conversion value */
+    return (*(__IO uint32_t *) ADDATA_ADDRESS);
+}
+
+/**
+* @brief  Configures the ADCx external trigger for injected channels conversion.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to
+*   start injected conversion.
+*   This parameter can be one of the following values:
+* @arg ADC_ExternalTrigConv_T1_CC1: Timer1 capture
+*   compare1 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T1_CC2: Timer1 capture
+*   compare2 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T1_CC3: Timer1 capture
+*   compare3 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T2_CC2: Timer2 capture
+*   compare2 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T3_TRGO: Timer3 TRGO event
+*   selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T4_CC4: Timer4 capture
+*   compare4 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_T3_CC1: Timer3 capture
+*   compare1 selected (for ADC1)
+* @arg ADC_ExternalTrigConv_EXTI_11: EXTI line 11 event
+*   cselected (for ADC1)
+* @arg ADC_ExternalTrigConv_T1_TRGO: Timer1 TRGO event
+*   selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T1_CC4: Timer1 capture
+*   compare4 selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T2_TRGO: Timer2 TRGO event
+*   selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T2_CC1: Timer2 capture
+*   compare1 selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T3_CC4: Timer3 capture
+*   compare4 selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T4_TRGO: Timer4 TRGO event
+*   selected (for ADC2)
+* @arg ADC_ExternalTrigConv_T3_CC1: Timer3 capture
+*   compare1 selected (for ADC2)
+* @arg ADC_ExternalTrigConv_EXTI_15: EXTI line 15 event
+*   cselected (for ADC2)
+* @retval : None
+*/
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+    /* Get the old register value */
+    tmpreg = ADCx->ADCR;
+    /* Clear the old external event selection for injected group */
+    tmpreg &= ADCR_EXTSEL_Reset;
+    /* Set the external event selection for injected group */
+    tmpreg |= ADC_ExternalTrigInjecConv;
+    /* Store the new register value */
+    ADCx->ADCR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the ADCx injected channels conversion
+*   through external trigger
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param NewState: new state of the selected ADC external trigger
+*   start of injected conversion.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected ADC external event selection for injected group */
+        ADCx->ADCR |= ADCR_EXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->ADCR &= ADCR_EXTTRIG_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the analog watchdog on single/all regular
+*   or injected channels
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+*   This parameter can be one of the following values:
+* @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on
+*   a single regular channel
+* @arg ADC_AnalogWatchdog_None: No channel guarded by the
+*   analog watchdog
+*   analog watchdog
+* @retval : None
+*/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+    /* Get the old register value */
+    tmpreg = ADCx->ADCFG;
+    /* Clear ADWEN bit */
+    tmpreg &= ADCFG_AWDMode_Reset;
+    /* Set the analog watchdog enable mode */
+    tmpreg |= ADC_AnalogWatchdog;
+    /* Store the new register value */
+    ADCx->ADCFG = tmpreg;
+}
+
+/**
+* @brief  Configures the high and low thresholds of the analog watchdog.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param HighThreshold: the ADC analog watchdog High threshold value.
+*   This parameter must be a 12bit value.
+* @param LowThreshold: the ADC analog watchdog Low threshold value.
+*   This parameter must be a 12bit value.
+* @retval : None
+*/
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+    uint32_t tempThreshold;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_THRESHOLD(HighThreshold));
+    assert_param(IS_ADC_THRESHOLD(LowThreshold));
+    /* Get the ADCx high threshold */
+    tempThreshold = HighThreshold;
+    /* Set the ADCx high threshold and the ADCx low threshold */
+    ADCx->ADCMPR = (tempThreshold << 16) | LowThreshold;
+}
+
+/**
+* @brief  Configures the analog watchdog guarded single channel
+* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+* @param ADC_Channel: the ADC channel to configure for the analog
+*   watchdog.
+*   This parameter can be one of the following values:
+* @arg ADC_Channel_0: ADC Channel0 selected
+* @arg ADC_Channel_1: ADC Channel1 selected
+* @arg ADC_Channel_2: ADC Channel2 selected
+* @arg ADC_Channel_3: ADC Channel3 selected
+* @arg ADC_Channel_4: ADC Channel4 selected
+* @arg ADC_Channel_5: ADC Channel5 selected
+* @arg ADC_Channel_6: ADC Channel6 selected
+* @arg ADC_Channel_7: ADC Channel7 selected
+* @arg ADC_Channel_8: ADC Channel8 selected
+* @arg ADC_Channel_All: ADC all Channel selected
+* @retval : None
+*/
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_CHANNEL(ADC_Channel));
+    /* Get the old register value */
+    tmpreg = ADCx->ADCR;
+    /* Clear the Analog watchdog channel select bits */
+    tmpreg &= ADCR_AWDCH_Reset;
+    /* Set the Analog watchdog channel */
+    tmpreg |= (ADC_Channel << 12);
+    /* Store the new register value */
+    ADCx->ADCR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the temperature sensor and Vrefint channel.
+* @param NewState: new state of the temperature sensor.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the temperature sensor and Vrefint channel*/
+        ADC1->ADCFG |= ADCFG_TVSEN ;
+        ADC2->ADCFG |= ADCFG_TVSEN ;//next
+    }
+    else
+    {
+        /* Disable the temperature sensor and Vrefint channel*/
+        ADC1->ADCFG &= ~ ADCFG_TVSEN;
+        ADC2->ADCFG &= ~ ADCFG_TVSEN;
+    }
+}
+
+/**
+* @brief  Checks whether the specified ADC flag is set or not.
+* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+* @param ADC_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg ADC_FLAG_AWD: Analog watchdog flag
+* @arg ADC_FLAG_EOC: End of conversion flag
+* @arg ADC_FLAG_BUSY: AD conversion busy flag
+* @retval : The new state of ADC_FLAG (SET or RESET).
+*/
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+    /* Check the status of the specified ADC flag */
+    if ((ADCx->ADSTA & ADC_FLAG) != (uint8_t)RESET)
+    {
+        /* ADC_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADC_FLAG is reset */
+        bitstatus = RESET;
+    }
+
+    /* Return the ADC_FLAG status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the ADCx's pending flags.
+* @param ADCx: where x can be 1, 2 to select the ADC peripheral.
+* @param ADC_FLAG: specifies the flag to clear.
+*   This parameter can be any combination of the following values:
+* @arg ADC_FLAG_AWD: Analog watchdog flag
+* @arg ADC_FLAG_EOC: End of conversion flag
+* @retval : None
+*/
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+    /* Clear the selected ADC flags */
+    ADCx->ADSTA |= ADC_FLAG;
+}
+
+/**
+* @brief  Checks whether the specified ADC interrupt has occurred or not.
+* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+* @param ADC_IT: specifies the ADC interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg ADC_IT_EOC: End of conversion interrupt mask
+* @arg ADC_IT_AWD: Analog watchdog interrupt mask
+* @retval : The new state of ADC_IT (SET or RESET).
+*/
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_GET_IT(ADC_IT));
+
+    /* Check the status of the specified ADC interrupt */
+    if (((ADCx->ADSTA & ADC_IT)) != (uint32_t)RESET)
+    {
+        /* ADC_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* ADC_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the ADC_IT status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the ADCx’s interrupt pending bits.
+* @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+* @param ADC_IT: specifies the ADC interrupt pending bit to clear.
+*   This parameter can be any combination of the following values:
+* @arg ADC_IT_EOC: End of conversion interrupt mask
+* @arg ADC_IT_AWD: Analog watchdog interrupt mask
+* @retval : None
+*/
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+
+    /* Check the parameters */
+    assert_param(IS_ADC_ALL_PERIPH(ADCx));
+    assert_param(IS_ADC_IT(ADC_IT));
+    /* Clear the selected ADC interrupt pending bits */
+    ADCx->ADSTA = ADC_IT;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_bkp.c

@@ -0,0 +1,300 @@
+/**
+******************************************************************************
+* @file    HAL_bkp.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the BKP firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_bkp.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup BKP
+* @brief BKP driver modules
+* @{
+*/
+
+/** @defgroup BKP_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Private_Defines
+* @{
+*/
+
+/* ------------ BKP registers bit address in the alias region --------------- */
+#define BKP_OFFSET        (BKP_BASE - PERIPH_BASE)
+
+/* --- CR Register ----*/
+
+/* Alias word address of TPAL bit */
+#define CR_OFFSET         (BKP_OFFSET + 0x30)
+#define TPAL_BitNumber    0x01
+#define CR_TPAL_BB        (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))
+
+/* Alias word address of TPE bit */
+#define TPE_BitNumber     0x00
+#define CR_TPE_BB         (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of TPIE bit */
+#define CSR_OFFSET        (BKP_OFFSET + 0x34)
+#define TPIE_BitNumber    0x02
+#define CSR_TPIE_BB       (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))
+
+/* Alias word address of TIF bit */
+#define TIF_BitNumber     0x09
+#define CSR_TIF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))
+
+/* Alias word address of TEF bit */
+#define TEF_BitNumber     0x08
+#define CSR_TEF_BB        (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))
+
+/* ---------------------- BKP registers bit mask ------------------------ */
+
+/* RTCCR register bit mask */
+#define RTCCR_CAL_Mask    ((uint16_t)0xFF80)
+#define RTCCR_Mask        ((uint16_t)0xFC7F)
+
+/* CSR register bit mask */
+#define CSR_CTE_Set       ((uint16_t)0x0001)
+#define CSR_CTI_Set       ((uint16_t)0x0002)
+
+/**
+* @}
+*/
+
+
+/** @defgroup BKP_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup BKP_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the BKP peripheral registers to their default
+*   reset values.
+* @param  None
+* @retval : None
+*/
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+/**
+* @brief  Configures the Tamper Pin active level.
+* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
+*   This parameter can be one of the following values:
+* @arg BKP_TamperPinLevel_High: Tamper pin active on high level
+* @arg BKP_TamperPinLevel_Low: Tamper pin active on low level
+* @retval : None
+*/
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+    /* Check the parameters */
+    assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));
+    *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;
+}
+
+/**
+* @brief  Enables or disables the Tamper Pin activation.
+* @param NewState: new state of the Tamper Pin activation.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;
+}
+
+/**
+* @brief  Enables or disables the Tamper Pin Interrupt.
+* @param NewState: new state of the Tamper Pin Interrupt.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void BKP_ITConfig(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;
+}
+
+/**
+* @brief  Select the RTC output source to output on the Tamper pin.
+* @param BKP_RTCOutputSource: specifies the RTC output source.
+*   This parameter can be one of the following values:
+* @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.
+* @arg BKP_RTCOutputSource_CalibClock: output the RTC clock
+*   with frequency divided by 64 on the Tamper pin.
+* @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse
+*   signal on the Tamper pin.
+* @arg BKP_RTCOutputSource_Second: output the RTC Second pulse
+*   signal on the Tamper pin.
+* @retval : None
+*/
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+    uint16_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));
+    tmpreg = BKP->RTCCR;
+    /* Clear CCO, ASOE and ASOS bits */
+    tmpreg &= RTCCR_Mask;
+
+    /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */
+    tmpreg |= BKP_RTCOutputSource;
+    /* Store the new value */
+    BKP->RTCCR = tmpreg;
+}
+
+/**
+* @brief  Sets RTC Clock Calibration value.
+* @param CalibrationValue: specifies the RTC Clock Calibration value.
+*   This parameter must be a number between 0 and 0x7F.
+* @retval : None
+*/
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+    uint16_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));
+    tmpreg = BKP->RTCCR;
+    /* Clear CAL[6:0] bits */
+    tmpreg &= RTCCR_CAL_Mask;
+    /* Set CAL[6:0] bits according to CalibrationValue value */
+    tmpreg |= CalibrationValue;
+    /* Store the new value */
+    BKP->RTCCR = tmpreg;
+}
+
+/**
+* @brief  Writes user data to the specified Data Backup Register.
+* @param BKP_DR: specifies the Data Backup Register.
+*   This parameter can be BKP_DRx where x:[1, 42]
+* @param Data: data to write
+* @retval : None
+*/
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_BKP_DR(BKP_DR));
+    *(__IO uint16_t *) (BKP_BASE + BKP_DR) = Data;
+}
+
+/**
+* @brief  Reads data from the specified Data Backup Register.
+* @param BKP_DR: specifies the Data Backup Register.
+*   This parameter can be BKP_DRx where x:[1, 42]
+* @retval : The content of the specified Data Backup Register
+*/
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+    /* Check the parameters */
+    assert_param(IS_BKP_DR(BKP_DR));
+    return (*(__IO uint16_t *) (BKP_BASE + BKP_DR));
+}
+
+/**
+* @brief  Checks whether the Tamper Pin Event flag is set or not.
+* @param  None
+* @retval : The new state of the Tamper Pin Event flag (SET or RESET).
+*/
+FlagStatus BKP_GetFlagStatus(void)
+{
+    return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);
+}
+
+/**
+* @brief  Clears Tamper Pin Event pending flag.
+* @param  None
+* @retval : None
+*/
+void BKP_ClearFlag(void)
+{
+    /* Set CTE bit to clear Tamper Pin Event flag */
+    BKP->CSR |= CSR_CTE_Set;
+}
+
+/**
+* @brief  Checks whether the Tamper Pin Interrupt has occurred or not.
+* @param  None
+* @retval : The new state of the Tamper Pin Interrupt (SET or RESET).
+*/
+ITStatus BKP_GetITStatus(void)
+{
+    return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);
+}
+
+/**
+* @brief  Clears Tamper Pin Interrupt pending bit.
+* @param  None
+* @retval : None
+*/
+void BKP_ClearITPendingBit(void)
+{
+    /* Set CTI bit to clear Tamper Pin Interrupt pending bit */
+    BKP->CSR |= CSR_CTI_Set;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_can.c

@@ -0,0 +1,971 @@
+/**
+******************************************************************************
+* @file    HAL_can.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the CAN firmware functions.
+******************************************************************************
+* @attention
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_can.h"
+#include "HAL_rcc.h"
+
+/**
+* @brief: Deinitialinzes the CAN registers to their default reset values
+* @retval: None
+*/
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    switch (*(uint32_t*)&CANx)
+    {
+        case CAN1_BASE:
+            /* Enable CAN1 reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+            /* Release CAN1 from reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+            break;
+        default:
+            break;
+    }
+
+}
+
+/**
+* @brief  Initializes the CAN peripheral according to the specified
+*   parameters in the CAN_InitStruct.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
+*   contains the configuration information for the CAN peripheral.
+* @retval : Constant indicates initialization succeed which will be
+*   CANINITFAILED or CANINITOK.
+*/
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_Basic_InitTypeDef* CAN_Basic_InitStruct)
+{
+    uint8_t InitStatus = CANINITFAILED;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SJW));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->BRP));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->SAM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG2));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_Basic_InitStruct->TESG1));
+
+    CANx->BTR0 = ((uint32_t)(CAN_Basic_InitStruct->SJW) << 6) | ((uint32_t)(CAN_Basic_InitStruct->BRP));
+    CANx->BTR1 = ((uint32_t)(CAN_Basic_InitStruct->SAM) << 7) | ((uint32_t)(CAN_Basic_InitStruct->TESG2) << 4) | \
+                 ((uint32_t)(CAN_Basic_InitStruct->TESG1));
+    if(CAN_Basic_InitStruct->GTS == ENABLE)
+    {
+        CANx->CMR |= (uint32_t)CAN_SleepMode;
+    }
+    else
+    {
+        CANx->CMR &= ~(uint32_t)CAN_SleepMode;
+    }
+
+    CANx->CDR |= ((CAN_Basic_InitStruct->CBP) << 6) | ((CAN_Basic_InitStruct->RXINTEN) << 5) | \
+                 ((CAN_Basic_InitStruct->CLOSE_OPEN_CLK) << 3) | (CAN_Basic_InitStruct->CDCLK);
+
+    InitStatus = CANINITOK;
+    return InitStatus;
+}
+
+/**
+* @brief  Configures the CAN_Basic reception filter according to the specified
+*         parameters in the CAN_Basic_FilterInitStruct.
+* @param  CAN_Basic_FilterInitStruct: pointer to a CAN_Basic_FilterInitTypeDef structure that
+*         contains the configuration information.
+* @retval None
+*/
+void CAN_FilterInit(CAN_Basic_FilterInitTypeDef* CAN_Basic_FilterInitStruct)
+{
+    /* Filter Mode */
+    CAN1->ACR = CAN_Basic_FilterInitStruct->CAN_FilterId;
+    CAN1->AMR = CAN_Basic_FilterInitStruct->CAN_FilterMaskId;
+}
+
+
+/**
+* @brief  Fills each CAN_Basic_InitStruct member with its default value.
+* @param CAN_Basic_InitStruct : pointer to a CAN_Basic_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void CAN_StructInit(CAN_Basic_InitTypeDef* CAN_Basic_InitStruct)
+{
+    /*--------------- Reset CAN_Basic init structure parameters values -----------------*/
+
+
+    /* initialize the BRP member(where can be set with (0..63))*/
+    CAN_Basic_InitStruct->BRP = 0x0;
+    /* initialize the SJW member(where can be set with (0..3)) */
+    CAN_Basic_InitStruct->SJW = 0x0;
+    /* Initialize the TESG1 member(where can be set with (0..15)) */
+    CAN_Basic_InitStruct->TESG1 = 0x0;
+    /* Initialize the TESG2 member(where can be set with(0..7)) */
+    CAN_Basic_InitStruct->TESG2 = 0x0;
+    /* Initialize the SAM member(where can be set (SET or RESET)) */
+    CAN_Basic_InitStruct->SAM = RESET;
+    /* Initialize the GTS member to Sleep Mode(where can be set (ENABLE or DISABLE)) */
+    CAN_Basic_InitStruct->GTS = DISABLE;
+    /* Initialize the external pin CLKOUT frequence */
+    CAN_Basic_InitStruct->CDCLK = 0x0;
+    /* Initialize the external clk is open or close */
+    CAN_Basic_InitStruct->CLOSE_OPEN_CLK = 0x0;
+    /* Initialize the TX1 pin work as rx interrupt output */
+    CAN_Basic_InitStruct->RXINTEN = 0x0;
+    /* Initialize the CBP of CDR register */
+    CAN_Basic_InitStruct->CBP = 0x0;
+}
+
+/**
+* @brief  Enables or disables the specified CAN interrupts.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @param CAN_IT: specifies the CAN interrupt sources to be enabled or
+*   disabled.
+*   This parameter can be: CAN_IT_OIE, CAN_IT_EIE, CAN_IT_TIE,
+*   CAN_IT_RIE,.
+* @param Newstate: new state of the CAN interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None.
+*/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState Newstate)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_ITConfig(CAN_IT));
+    assert_param(IS_FUNCTIONAL_STATE(Newstate));
+    if (Newstate != DISABLE)
+    {
+        /* Enable the selected CAN interrupt */
+        CANx->CR |= CAN_IT;
+    }
+    else
+    {
+        /* Disable the selected CAN interrupt */
+        CANx->CR &= ~CAN_IT;
+    }
+}
+
+
+/**
+* @brief  Initiates and transmits a CAN frame message.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+* @retval CANTXOK if the CAN driver transmits the message
+*/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanBasicTxMsg* BasicTxMessage)
+{
+    /* TXOK and TME bits */
+    uint8_t state = 0;
+    /* Check the parameters */
+    assert_param(IS_CAN_RTR(BasicTxMessage->RTR));
+    assert_param(IS_CAN_DLC(BasicTxMessage->DLC));
+
+    CANx->TXID0 = (BasicTxMessage->IDH);
+    CANx->TXID1 = (BasicTxMessage->IDL << 5) | (BasicTxMessage->RTR << 4) | (BasicTxMessage->DLC);
+    if((FunctionalState)(BasicTxMessage->RTR) != ENABLE)
+    {
+        CANx->TXDR0 = BasicTxMessage->Data[0];
+        CANx->TXDR1 = BasicTxMessage->Data[1];
+        CANx->TXDR2 = BasicTxMessage->Data[2];
+        CANx->TXDR3 = BasicTxMessage->Data[3];
+        CANx->TXDR4 = BasicTxMessage->Data[4];
+        CANx->TXDR5 = BasicTxMessage->Data[5];
+        CANx->TXDR6 = BasicTxMessage->Data[6];
+        CANx->TXDR7 = BasicTxMessage->Data[7];
+    }
+
+    CANx->CMR = CAN_CMR_TR;
+
+    return state;
+}
+
+/**
+* @brief  Cancels a transmit request.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+
+* @retval None
+*/
+void CAN_CancelTransmit(CAN_TypeDef* CANx)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+    /* abort transmission */
+    CANx->CMR = CAN_AT;
+
+}
+
+/**
+* @brief  Releases the specified receive FIFO.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @retval None
+*/
+void CAN_FIFORelease(CAN_TypeDef* CANx)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Release FIFO */
+    CANx->CMR |= (uint32_t)CAN_RRB;
+
+}
+
+/**
+* @brief  Receives a correct CAN frame.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
+*         CAN DLC, CAN data and FMI number.
+* @retval None
+*/
+void CAN_Receive(CAN_TypeDef* CANx, CanBasicRxMsg* BasicRxMessage)
+{
+    uint16_t tempid;
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_FIFO(FIFONumber));
+    BasicRxMessage->RTR = (uint8_t)((CANx->RXID1) >> 4) & 0x1;
+    BasicRxMessage->DLC = (uint8_t)((CANx->RXID1) & 0xf);
+    tempid = (uint16_t)(((CANx->RXID1) & 0xe0) >> 5);
+    tempid |= (uint16_t)(CANx->RXID0 << 3);
+    BasicRxMessage->ID = tempid;
+    BasicRxMessage->Data[0] = CAN1->RXDR0;
+    BasicRxMessage->Data[1] = CAN1->RXDR1;
+    BasicRxMessage->Data[2] = CAN1->RXDR2;
+    BasicRxMessage->Data[3] = CAN1->RXDR3;
+    BasicRxMessage->Data[4] = CAN1->RXDR4;
+    BasicRxMessage->Data[5] = CAN1->RXDR5;
+    BasicRxMessage->Data[6] = CAN1->RXDR6;
+    BasicRxMessage->Data[7] = CAN1->RXDR7;
+    CAN_FIFORelease( CANx);
+}
+
+/**
+* @brief: Select the Sleep mode or not in Basic workmode
+* @param: NewState to go into the Sleep mode or go out
+* @retval: None
+*/
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+    uint8_t sleepstatus = CANSLEEPFAILED;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    CANx->CMR |= CAN_SleepMode;
+    if((CANx->CMR & 0x10) == CAN_SleepMode)
+    {
+        sleepstatus =  CANSLEEPOK;
+    }
+    /* At this step, sleep mode status */
+    return (uint8_t)sleepstatus;
+
+}
+
+/**
+* @brief  Wakes the CAN up.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @retval : CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other
+*   case.
+*/
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+    uint8_t wakeupstatus = CANWAKEUPFAILED;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Wake up request */
+    CANx->CMR &= ~CAN_SleepMode;
+
+    /* Sleep mode status */
+    if((CANx->CMR & 0x01) == 0)
+    {
+        /* Sleep mode exited */
+        wakeupstatus = CANWAKEUPOK;
+    }
+    /* At this step, sleep mode status */
+    return (uint8_t)wakeupstatus;
+}
+
+
+/**
+* @brief  Checks whether the specified CAN flag is set or not.
+* @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+* @param  CAN_FLAG: specifies the flag to check.
+*          This parameter can be one of the following values:
+*            @arg CAN_STATUS_RBS: Receive buffer status
+*            @arg CAN_STATUS_DOS: Data overflow status
+*            @arg CAN_STATUS_TBS: Transmit buffer status
+*            @arg CAN_STATUS_TCS: Transmit complete status
+*            @arg CAN_STATUS_RS: Receiving status
+*            @arg CAN_STATUS_TS: Transmiting status
+*            @arg CAN_STATUS_ES: Error status
+*            @arg CAN_STATUS_BS: bus status, close or open
+* @retval The new state of CAN_FLAG (SET or RESET).
+*/
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+
+
+    if((CANx->SR & CAN_FLAG) == CAN_FLAG)
+    {
+        /* CAN_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* CAN_FLAG is reset */
+        bitstatus = RESET;
+    }
+    /* Return the CAN_FLAG status */
+    return bitstatus;
+}
+
+/**
+* @brief  Checks whether the specified CAN interrupt has occurred or not.
+* @param CANx: where x can be 1 to select the CAN peripheral.
+* @param  CAN_IT: specifies the CAN interrupt source to check.
+*          This parameter can be one of the following values:
+*            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+*            @arg CAN_IT_TI: Transmit Interrupt
+*            @arg CAN_IT_EI: ERROR Interrupt
+*            @arg CAN_IT_DOI: Data voerflow Interrupt
+*            @arg CAN_IT_WUI: Wakeup Interrupt
+*            @arg CAN_IT_ALL: use it can enble all Interrupt
+* @retval The current state of CAN_IT (SET or RESET).
+*/
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+    ITStatus itstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+    assert_param(IS_CAN_IT(CAN_IT));
+
+    /* check the interrupt enable bit */
+    if((CANx->IR & CAN_IT) != CAN_IT)
+    {
+        itstatus = RESET;
+    }
+    else
+    {
+        itstatus = SET;
+    }
+
+    return itstatus;
+}
+
+
+/**
+* @brief: Select the can work as peli mode or basic mode
+* @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+* @param  CAN_MODE: specifies the work mode:CAN_BASICMode,CAN_PELIMode
+* @retval: None
+*/
+void CAN_Mode_Cmd(CAN_TypeDef* CANx, uint32_t CAN_MODE)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    CANx->CDR |= CAN_MODE;
+}
+
+
+/**
+* @brief: Select the Reset mode or not
+* @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+* @param: NewState to go into the Reset mode or go out
+* @retval: None
+*/
+void CAN_ResetMode_Cmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    if(NewState == ENABLE)
+    {
+        CANx->CR |= CAN_ResetMode;
+    }
+    else
+    {
+        CANx->CR &= ~CAN_ResetMode;
+    }
+}
+
+/**
+* @brief  Clear the data overflow.
+* @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+* @retval None
+*/
+void CAN_ClearDataOverflow(CAN_TypeDef* CANx)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    CANx->CMR |= (uint32_t)CAN_CDO;
+
+}
+
+/**
+* @brief  Clears the CAN's IT pending.
+* @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+* @retval None
+*/
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx)
+{
+    uint32_t temp = 0;
+    temp = temp;
+    temp = CANx->IR; //read this register clear all interrupt
+
+}
+
+
+
+/**
+* @brief: Select the Sleep mode or not in Peli workmode
+* @param: NewState to go into the Sleep mode or go out
+* @retval: None
+*/
+void CAN_Peli_SleepMode_Cmd(FunctionalState NewState)
+{
+    if(NewState == ENABLE)
+        CAN1_PELI->MOD |= CAN_SleepMode;
+    else
+        CAN1_PELI->MOD &= ~CAN_SleepMode;
+}
+
+
+/**
+* @brief  Fills each CAN1_PELI_InitStruct member with its default value.
+* @param CAN_Peli_InitStruct : pointer to a CAN_Peli_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void CAN_Peli_StructInit(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct)
+{
+    /*--------------- Reset CAN_Peli init structure parameters values -----------------*/
+
+    /* initialize the BRP member(where can be set with (0..63))*/
+    CAN_Peli_InitStruct->BRP = 0x0;
+    /* initialize the SJW member(where can be set with (0..3)) */
+    CAN_Peli_InitStruct->SJW = 0x0;
+    /* Initialize the TESG1 member(where can be set with (0..15)) */
+    CAN_Peli_InitStruct->TESG1 = 0x0;
+    /* Initialize the TESG2 member(where can be set with(0..7)) */
+    CAN_Peli_InitStruct->TESG2 = 0x0;
+    /* Initialize the SAM member(where can be set (SET or RESET)) */
+    CAN_Peli_InitStruct->SAM = RESET;
+    /* Initialize the LOM member*/
+    CAN_Peli_InitStruct->LOM = DISABLE;
+    /* Initialize the STM member*/
+    CAN_Peli_InitStruct->STM = DISABLE;
+    /* Initialize the SM member*/
+    CAN_Peli_InitStruct->SM = DISABLE;
+    CAN_Peli_InitStruct->SRR = DISABLE;
+    CAN_Peli_InitStruct->EWLR = 0x96;
+}
+
+/**
+* @brief  Initializes the CAN_Peli peripheral according to the specified
+*         parameters in the CAN_Peli_InitStruct.
+* @param  CAN_Basic_InitStruct: pointer to a CAN_Peli_InitTypeDef structure that contains
+*         the configuration information for the CAN peripheral in the peli workmode.
+* @retval None
+*/
+void CAN_Peli_Init(CAN_Peli_InitTypeDef* CAN_Peli_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SJW));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->BRP));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->SAM));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG2));
+    assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->TESG1));
+
+    CAN1_PELI->BTR0 = ((uint32_t)CAN_Peli_InitStruct->SJW << 6) | ((uint32_t)CAN_Peli_InitStruct->BRP);
+    CAN1_PELI->BTR1 = ((uint32_t)CAN_Peli_InitStruct->SAM << 7) | ((uint32_t)CAN_Peli_InitStruct->TESG2 << 4) | \
+                      ((uint32_t)CAN_Peli_InitStruct->TESG1);
+    if(CAN_Peli_InitStruct->LOM == ENABLE)
+        CAN1_PELI->MOD |= (uint32_t)CAN_ListenOnlyMode;
+    else
+        CAN1_PELI->MOD &= ~(uint32_t)CAN_ListenOnlyMode;
+    if(CAN_Peli_InitStruct->STM == ENABLE)
+        CAN1_PELI->MOD |= (uint32_t)CAN_SeftTestMode;
+    else
+        CAN1_PELI->MOD &= ~(uint32_t)CAN_SeftTestMode;
+    if(CAN_Peli_InitStruct->SM == ENABLE)
+        CAN1_PELI->MOD |= (uint32_t)CAN_SleepMode;
+    else
+        CAN1_PELI->MOD &= ~(uint32_t)CAN_SleepMode;
+    CAN1_PELI->EWLR = (uint32_t)CAN_Peli_InitStruct->EWLR;
+}
+
+
+
+/**
+* @brief  Configures the CAN_Peli reception filter according to the specified
+*         parameters in the CAN_Peli_FilterInitStruct.
+* @param  CAN_Peli_FilterInitStruct: pointer to a CAN_Peli_FilterInitTypeDef structure that
+*         contains the configuration information.
+* @retval None
+*/
+void CAN_Peli_FilterInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct)
+{
+    if(CAN_Peli_FilterInitStruct->AFM == CAN_FilterMode_Singal)
+        CAN1_PELI->MOD |= (uint32_t)CAN_FilterMode_Singal;
+    else
+        CAN1_PELI->MOD &= (uint32_t)CAN_FilterMode_Double;
+
+    CAN1_PELI->FF = CAN_Peli_FilterInitStruct->CAN_FilterId0;
+    CAN1_PELI->ID0 = CAN_Peli_FilterInitStruct->CAN_FilterId1;
+    CAN1_PELI->ID1 = CAN_Peli_FilterInitStruct->CAN_FilterId2;
+    CAN1_PELI->DATA0 = CAN_Peli_FilterInitStruct->CAN_FilterId3;
+
+    CAN1_PELI->DATA1 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId0;
+    CAN1_PELI->DATA2 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId1;
+    CAN1_PELI->DATA3 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId2;
+    CAN1_PELI->DATA4 = CAN_Peli_FilterInitStruct->CAN_FilterMaskId3;
+}
+
+/**
+* @brief  Fills each CAN_Peli_FilterInitStruct member with its default value.
+* @param  CAN_Peli_FilterInitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
+* @retval None
+*/
+void CAN_Peli_FilterStructInit(CAN_Peli_FilterInitTypeDef* CAN_Peli_FilterInitStruct)
+{
+    CAN_Peli_FilterInitStruct->CAN_FilterId0 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterId1 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterId2 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterId3 = 0;
+
+    CAN_Peli_FilterInitStruct->CAN_FilterMaskId0 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterMaskId1 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterMaskId2 = 0;
+    CAN_Peli_FilterInitStruct->CAN_FilterMaskId3 = 0;
+}
+
+
+/**
+* @brief  Initiates and transmits a CAN frame message.
+* @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+* @retval None
+*/
+void CAN_Peli_Transmit(CanPeliTxMsg* PeliTxMessage)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_RTR(PeliTxMessage->RTR));
+    assert_param(IS_CAN_DLC(PeliTxMessage->DLC));
+
+    CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC);
+    if(((FunctionalState)PeliTxMessage->FF) != ENABLE)
+    {
+        CAN1_PELI->ID0 = (PeliTxMessage->IDHH);
+        //    CAN1_PELI->ID1 = ((PeliTxMessage->IDHL)<<5);
+        CAN1_PELI->ID1 = (PeliTxMessage->IDHL & 0xE0);
+        if((FunctionalState)(PeliTxMessage->RTR) != ENABLE)
+        {
+            CAN1_PELI->DATA0 = PeliTxMessage->Data[0];
+            CAN1_PELI->DATA1 = PeliTxMessage->Data[1];
+            CAN1_PELI->DATA2 = PeliTxMessage->Data[2];
+            CAN1_PELI->DATA3 = PeliTxMessage->Data[3];
+            CAN1_PELI->DATA4 = PeliTxMessage->Data[4];
+            CAN1_PELI->DATA5 = PeliTxMessage->Data[5];
+            CAN1_PELI->DATA6 = PeliTxMessage->Data[6];
+            CAN1_PELI->DATA7 = PeliTxMessage->Data[7];
+        }
+    }
+    else
+    {
+        CAN1_PELI->ID0 = PeliTxMessage->IDHH;
+        CAN1_PELI->ID1 = PeliTxMessage->IDHL;
+        CAN1_PELI->DATA0 = PeliTxMessage->IDLH;
+        CAN1_PELI->DATA1 = PeliTxMessage->IDLL;
+        if((FunctionalState)(PeliTxMessage->RTR) != ENABLE)
+        {
+            CAN1_PELI->DATA2 = PeliTxMessage->Data[0];
+            CAN1_PELI->DATA3 = PeliTxMessage->Data[1];
+            CAN1_PELI->DATA4 = PeliTxMessage->Data[2];
+            CAN1_PELI->DATA5 = PeliTxMessage->Data[3];
+            CAN1_PELI->DATA6 = PeliTxMessage->Data[4];
+            CAN1_PELI->DATA7 = PeliTxMessage->Data[5];
+            CAN1_PELI->DATA8 = PeliTxMessage->Data[6];
+            CAN1_PELI->DATA9 = PeliTxMessage->Data[7];
+        }
+    }
+    if(CAN1_PELI->MOD & CAN_MOD_STM)
+    {
+        CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT;
+    }
+    else
+    {
+        CAN1->CMR = CAN_TR | CAN_AT;
+    }
+
+}
+
+
+
+/**
+* @brief  Initiates and transmits a CAN frame message.
+* @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+* @retval None
+*/
+void CAN_Peli_TransmitRepeat(CanPeliTxMsg* PeliTxMessage)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_RTR(PeliTxMessage->RTR));
+    assert_param(IS_CAN_DLC(PeliTxMessage->DLC));
+
+    CAN1_PELI->FF = (PeliTxMessage->FF << 7) | (PeliTxMessage->RTR << 6) | (PeliTxMessage->DLC);
+    if(((FunctionalState)PeliTxMessage->FF) != ENABLE)
+    {
+        CAN1_PELI->ID0 = (PeliTxMessage->IDHH);
+        CAN1_PELI->ID1 = ((PeliTxMessage->IDHL) << 5);
+        if((FunctionalState)(PeliTxMessage->RTR) != ENABLE)
+        {
+            CAN1_PELI->DATA0 = PeliTxMessage->Data[0];
+            CAN1_PELI->DATA1 = PeliTxMessage->Data[1];
+            CAN1_PELI->DATA2 = PeliTxMessage->Data[2];
+            CAN1_PELI->DATA3 = PeliTxMessage->Data[3];
+            CAN1_PELI->DATA4 = PeliTxMessage->Data[4];
+            CAN1_PELI->DATA5 = PeliTxMessage->Data[5];
+            CAN1_PELI->DATA6 = PeliTxMessage->Data[6];
+            CAN1_PELI->DATA7 = PeliTxMessage->Data[7];
+        }
+    }
+    else
+    {
+        CAN1_PELI->ID0 = PeliTxMessage->IDHH;
+        CAN1_PELI->ID1 = PeliTxMessage->IDHL;
+        CAN1_PELI->DATA0 = PeliTxMessage->IDLH;
+        CAN1_PELI->DATA1 = PeliTxMessage->IDLL;
+        if((FunctionalState)(PeliTxMessage->RTR) != ENABLE)
+        {
+            CAN1_PELI->DATA2 = PeliTxMessage->Data[0];
+            CAN1_PELI->DATA3 = PeliTxMessage->Data[1];
+            CAN1_PELI->DATA4 = PeliTxMessage->Data[2];
+            CAN1_PELI->DATA5 = PeliTxMessage->Data[3];
+            CAN1_PELI->DATA6 = PeliTxMessage->Data[4];
+            CAN1_PELI->DATA7 = PeliTxMessage->Data[5];
+            CAN1_PELI->DATA8 = PeliTxMessage->Data[6];
+            CAN1_PELI->DATA9 = PeliTxMessage->Data[7];
+        }
+    }
+
+    if(CAN1_PELI->MOD & CAN_MOD_STM)
+    {
+        CAN1->CMR = CAN_CMR_GTS | CAN_CMR_AT;
+    }
+    else
+    {
+        CAN1->CMR = CAN_CMR_TR;
+    }
+}
+
+/** @defgroup CAN_Group3 CAN Frames Reception functions
+*  @brief    CAN Frames Reception functions
+*
+@verbatim
+===============================================================================
+##### CAN Frames Reception functions #####
+===============================================================================
+[..] This section provides functions allowing to
+(+) Receive a correct CAN frame.
+(+) Release a specified receive FIFO
+(+) Return the number of the pending received CAN frames.
+
+@endverbatim
+* @{
+*/
+
+
+/**
+* @brief  Receives a correct CAN frame.
+* @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
+*         CAN DLC, CAN data and FMI number.
+* @retval None
+*/
+void CAN_Peli_Receive(CanPeliRxMsg* PeliRxMessage)
+{
+    uint32_t tempid;
+    PeliRxMessage->FF = (CAN1_PELI->FF) >> 7;
+    PeliRxMessage->RTR = ((CAN1_PELI->FF) >> 6) & 0x1;
+    PeliRxMessage->DLC = (CAN1_PELI->FF) & 0xf;
+
+    if(((FunctionalState)PeliRxMessage->FF) != ENABLE)
+    {
+        tempid = (uint32_t)(CAN1_PELI->ID1 >> 5);
+        tempid |= (uint32_t)(CAN1_PELI->ID0 << 3);
+        PeliRxMessage->ID = tempid;
+        PeliRxMessage->Data[0] = CAN1_PELI->DATA0;
+        PeliRxMessage->Data[1] = CAN1_PELI->DATA1;
+        PeliRxMessage->Data[2] = CAN1_PELI->DATA2;
+        PeliRxMessage->Data[3] = CAN1_PELI->DATA3;
+        PeliRxMessage->Data[4] = CAN1_PELI->DATA4;
+        PeliRxMessage->Data[5] = CAN1_PELI->DATA5;
+        PeliRxMessage->Data[6] = CAN1_PELI->DATA6;
+        PeliRxMessage->Data[7] = CAN1_PELI->DATA7;
+    }
+    else
+    {
+        tempid = (uint32_t)((CAN1_PELI->DATA1 & 0xf8) >> 3);
+        tempid |= (uint32_t)(CAN1_PELI->DATA0 << 5);
+        tempid |= (uint32_t)(CAN1_PELI->ID1 << 13);
+        tempid |= (uint32_t)(CAN1_PELI->ID0 << 21);
+        PeliRxMessage->ID = tempid;
+        PeliRxMessage->Data[0] = CAN1_PELI->DATA2;
+        PeliRxMessage->Data[1] = CAN1_PELI->DATA3;
+        PeliRxMessage->Data[2] = CAN1_PELI->DATA4;
+        PeliRxMessage->Data[3] = CAN1_PELI->DATA5;
+        PeliRxMessage->Data[4] = CAN1_PELI->DATA6;
+        PeliRxMessage->Data[5] = CAN1_PELI->DATA7;
+        PeliRxMessage->Data[6] = CAN1_PELI->DATA8;
+        PeliRxMessage->Data[7] = CAN1_PELI->DATA9;
+    }
+    CAN_FIFORelease( CAN1);
+}
+
+
+/**
+* @brief  Get available current informatoin in receive FIFO only in Peli workmode.
+* @retval The value in reg RMC
+*/
+uint32_t CAN_Peli_GetRxFIFOInfo(void)
+{
+    return CAN1_PELI->RMC;
+}
+
+
+/** @defgroup CAN_Group5 CAN Bus Error management functions
+*  @brief    CAN Bus Error management functions
+*
+@verbatim
+===============================================================================
+##### CAN Bus Error management functions #####
+===============================================================================
+
+@endverbatim
+* @{
+*/
+
+/**
+* @brief  Returns the CAN's last error code (LEC).
+* @retval Error code:
+*          - CAN_ERRORCODE_NoErr: No Error
+*          - CAN_ERRORCODE_StuffErr: Stuff Error
+*          - CAN_ERRORCODE_FormErr: Form Error
+*          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+*          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+*          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+*          - CAN_ERRORCODE_CRCErr: CRC Error
+*          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
+*/
+uint8_t CAN_Peli_GetLastErrorCode(void)
+{
+    uint8_t errorcode = 0;
+
+    /* Get the error code*/
+    errorcode = ((uint8_t)CAN1_PELI->ECC);
+
+    /* Return the error code*/
+    return errorcode;
+}
+/**
+* @brief  Returns the CAN Receive Error Counter (REC).
+* @note   In case of an error during reception, this counter is incremented
+*         by 1 or by 8 depending on the error condition as defined by the CAN
+*         standard. After every successful reception, the counter is
+*         decremented by 1 or reset to 120 if its value was higher than 128.
+*         When the counter value exceeds 127, the CAN controller enters the
+*         error passive state.
+* @retval CAN Receive Error Counter.
+*/
+uint8_t CAN_Peli_GetReceiveErrorCounter(void)
+{
+    uint8_t counter = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Get the Receive Error Counter*/
+    counter = (uint8_t)(CAN1_PELI->RXERR);
+
+    /* Return the Receive Error Counter*/
+    return counter;
+}
+
+
+/**
+* @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+* @retval LSB of the 8-bit CAN Transmit Error Counter.
+*/
+uint8_t CAN_Peli_GetLSBTransmitErrorCounter(void)
+{
+    uint8_t counter = 0;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_ALL_PERIPH(CANx));
+
+    /* Get the LSB of the 8-bit CAN Transmit Error Counter(TEC) */
+    counter = (uint8_t)(CAN1_PELI->TXERR);
+
+    /* Return the LSB of the 8-bit CAN Transmit Error Counter(TEC) */
+    return counter;
+}
+/** @defgroup CAN_Group6 Interrupts and flags management functions
+*  @brief   Interrupts and flags management functions
+*
+@verbatim
+===============================================================================
+##### Interrupts and flags management functions #####
+===============================================================================
+[..] This section provides functions allowing to configure the CAN Interrupts
+and to get the status and clear flags and Interrupts pending bits.
+[..] The CAN provides 14 Interrupts sources and 15 Flags:
+
+*** Flags ***
+=============
+*/
+/**
+* @brief  Enables or disables the specified CAN interrupts in peli workmode.
+* @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+*          This parameter can be:
+*            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+*            @arg CAN_IT_TI: Transmit Interrupt
+*            @arg CAN_IT_EI: ERROR Interrupt
+*            @arg CAN_IT_DOI: Data voerflow Interrupt
+*            @arg CAN_IT_WUI: Wakeup Interrupt
+*            @arg CAN_IT_EPI(only Peli): passive error Interrupt
+*            @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
+*            @arg CAN_IT_BEI(only Peli): bus error Interrupt
+@arg CAN_IT_ALL: use it can enble all Interrupt
+* @param  NewState: new state of the CAN interrupts.
+*          This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void CAN_Peli_ITConfig(uint32_t CAN_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_CAN_IT(CAN_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected CAN interrupt */
+        CAN1_PELI->IER |= CAN_IT;
+    }
+    else
+    {
+        /* Disable the selected CAN interrupt */
+        CAN1_PELI->IER &= ~CAN_IT;
+    }
+}
+
+
+/**
+* @brief  Checks whether the specified CAN interrupt has occurred or not.
+* @param  CAN_IT: specifies the CAN interrupt source to check.
+*          This parameter can be one of the following values:
+*            @arg CAN_IT_RI: Receive FIFO not empty Interrupt
+*            @arg CAN_IT_TI: Transmit Interrupt
+*            @arg CAN_IT_EI: ERROR Interrupt
+*            @arg CAN_IT_DOI: Data voerflow Interrupt
+*            @arg CAN_IT_WUI: Wakeup Interrupt
+*            @arg CAN_IT_EPI(only Peli): passive error Interrupt
+*            @arg CAN_IT_ALI(only Peli): arbiter lose Interrupt
+*            @arg CAN_IT_BEI(only Peli): bus error Interrupt
+@arg CAN_IT_ALL: use it can enble all Interrupt
+* @retval The current state of CAN_IT (SET or RESET).
+*/
+ITStatus CAN_Peli_GetITStatus(uint32_t CAN_IT)
+{
+    ITStatus itstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_CAN_IT(CAN_IT));
+
+    /* check the interrupt enable bit */
+    if((CAN1_PELI->IR & CAN_IT) != CAN_IT)
+    {
+        itstatus = RESET;
+    }
+    else
+    {
+        itstatus = SET;
+    }
+
+    return itstatus;
+}
+
+/**
+* @brief  Config CAN_Peli_InitTypeDef baud parameter.
+* @param  CAN_Peli_InitTypeDef: CAN struct.
+* @param  SrcClk: CAN module clock.
+* @param  baud: specified baud.
+* @retval The current state of CAN_IT (SET or RESET).
+*/
+void CAN_AutoCfg_BaudParam(CAN_Peli_InitTypeDef  *CAN_Peli_InitStruct, unsigned int SrcClk, unsigned int baud )
+{
+    unsigned int i, value = baud, record = 1;
+    unsigned int remain = 0, sumPrescaler = 0;
+    while(( baud == 0 ) || ( SrcClk == 0 )); //防止波特率及时钟为0
+    sumPrescaler = SrcClk / baud; //总分频
+    sumPrescaler = sumPrescaler / 2; //
+    for( i = 25; i > 3; i -- )
+    {
+        remain = sumPrescaler - ((sumPrescaler / i) * i);
+        if( remain == 0 )		//整除
+        {
+            record = i;
+            break;
+        }
+        else
+        {
+            if(remain < value)
+            {
+                value = remain;
+                record = i;
+            }
+        }
+    }
+    CAN_Peli_InitStruct->SJW = 0;
+    CAN_Peli_InitStruct->BRP = (sumPrescaler / record) - 1;
+    CAN_Peli_InitStruct->TESG2 = (record - 3) / 3;
+    CAN_Peli_InitStruct->TESG1 = (record - 3) - CAN_Peli_InitStruct->TESG2;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/
+

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_crc.c

@@ -0,0 +1,164 @@
+/**
+******************************************************************************
+* @file    HAL_crc.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the CRC firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_crc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup CRC
+* @brief CRC driver modules
+* @{
+*/
+
+/** @defgroup CRC_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Private_Defines
+* @{
+*/
+
+/* CR register bit mask */
+
+#define CR_RESET_Set    ((uint32_t)0x00000001)
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup CRC_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Resets the CRC Data register (DR).
+* @param  None
+* @retval : None
+*/
+void CRC_ResetDR(void)
+{
+    /* Reset CRC generator */
+    CRC->CR = CR_RESET_Set;
+}
+
+/**
+* @brief  Computes the 32-bit CRC of a given data word(32-bit).
+* @param Data: data word(32-bit) to compute its CRC
+* @retval : 32-bit CRC
+*/
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+    CRC->DR = Data;
+    CRC->DR = CRC_GetCRC();//__NOP();//
+    return (CRC->DR);
+}
+
+/**
+* @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+* @param pBuffer: pointer to the buffer containing the data to be
+*   computed
+* @param BufferLength: length of the buffer to be computed
+* @retval : 32-bit CRC
+*/
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for(index = 0; index < BufferLength; index++)
+    {
+        CRC->DR = pBuffer[index];
+    }
+    return (CRC->DR);
+}
+
+/**
+* @brief  Returns the current CRC value.
+* @param  None
+* @retval : 32-bit CRC
+*/
+uint32_t CRC_GetCRC(void)
+{
+    return (CRC->DR);
+}
+
+/**
+* @brief  Stores a 8-bit data in the Independent Data(ID) register.
+* @param IDValue: 8-bit value to be stored in the ID register
+* @retval : None
+*/
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+    CRC->IDR = IDValue;
+}
+
+/**
+* @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+* @param  None
+* @retval : 8-bit value of the ID register
+*/
+uint8_t CRC_GetIDRegister(void)
+{
+    return (CRC->IDR);
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_dma.c

@@ -0,0 +1,545 @@
+/**
+******************************************************************************
+* @file    HAL_dma.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the DMA firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_dma.h"
+
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup DMA
+* @brief DMA driver modules
+* @{
+*/
+
+/** @defgroup DMA_Private_TypesDefinitions
+* @{
+*/
+/**
+* @}
+*/
+
+/** @defgroup DMA_Private_Defines
+* @{
+*/
+
+/* DMA ENABLE mask */
+#define CCR_ENABLE_Set          ((uint32_t)0x00000001)
+#define CCR_ENABLE_Reset        ((uint32_t)0xFFFFFFFE)
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask    ((uint32_t)0x0000000F)
+#define DMA1_Channel2_IT_Mask    ((uint32_t)0x000000F0)
+#define DMA1_Channel3_IT_Mask    ((uint32_t)0x00000F00)
+#define DMA1_Channel4_IT_Mask    ((uint32_t)0x0000F000)
+#define DMA1_Channel5_IT_Mask    ((uint32_t)0x000F0000)
+#define DMA1_Channel6_IT_Mask    ((uint32_t)0x00F00000)
+#define DMA1_Channel7_IT_Mask    ((uint32_t)0x0F000000)
+
+
+
+
+
+
+/* DMA registers Masks */
+#define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup DMA_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the DMAy Channelx registers to their default reset
+*   values.
+* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+*   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
+*   DMA Channel.
+* @retval : None
+*/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+    /* Disable the selected DMAy Channelx */
+    DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+    /* Reset DMAy Channelx control register */
+    DMAy_Channelx->CCR  = 0;
+
+    /* Reset DMAy Channelx remaining bytes register */
+    DMAy_Channelx->CNDTR = 0;
+
+    /* Reset DMAy Channelx peripheral address register */
+    DMAy_Channelx->CPAR  = 0;
+
+    /* Reset DMAy Channelx memory address register */
+    DMAy_Channelx->CMAR = 0;
+    switch (*(uint32_t*)&DMAy_Channelx)
+    {
+        case DMA1_Channel1_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel1 */
+            DMA1->IFCR |= DMA1_Channel1_IT_Mask;
+            break;
+        case DMA1_Channel2_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel2 */
+            DMA1->IFCR |= DMA1_Channel2_IT_Mask;
+            break;
+        case DMA1_Channel3_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel3 */
+            DMA1->IFCR |= DMA1_Channel3_IT_Mask;
+            break;
+        case DMA1_Channel4_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel4 */
+            DMA1->IFCR |= DMA1_Channel4_IT_Mask;
+            break;
+        case DMA1_Channel5_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel5 */
+            DMA1->IFCR |= DMA1_Channel5_IT_Mask;
+            break;
+        case DMA1_Channel6_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel6 */
+            DMA1->IFCR |= DMA1_Channel6_IT_Mask;
+            break;
+        case DMA1_Channel7_BASE:
+            /* Reset interrupt pending bits for DMA1 Channel7 */
+            DMA1->IFCR |= DMA1_Channel7_IT_Mask;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the DMAy Channelx according to the specified
+*   parameters in the DMA_InitStruct.
+* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+*   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
+*   DMA Channel.
+* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
+*   contains the configuration information for the specified
+*   DMA Channel.
+* @retval : None
+*/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+    assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+    assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+    assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+    assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+    assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+    assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+    assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+    assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+    assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+    /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
+    /* Get the DMAy_Channelx CCR value */
+    tmpreg = DMAy_Channelx->CCR;
+    /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+    tmpreg &= CCR_CLEAR_Mask;
+    /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+    /* Set DIR bit according to DMA_DIR value */
+    /* Set CIRC bit according to DMA_Mode value */
+    /* Set PINC bit according to DMA_PeripheralInc value */
+    /* Set MINC bit according to DMA_MemoryInc value */
+    /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+    /* Set MSIZE bits according to DMA_MemoryDataSize value */
+    /* Set PL bits according to DMA_Priority value */
+    /* Set the MEM2MEM bit according to DMA_M2M value */
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+    /* Write to DMAy Channelx CCR */
+    DMAy_Channelx->CCR = tmpreg;
+    /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
+    /* Write to DMAy Channelx CNDTR */
+    DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+    /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
+    /* Write to DMAy Channelx CPAR */
+    DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
+    /* Write to DMAy Channelx CMAR */
+    DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+* @brief  Fills each DMA_InitStruct member with its default value.
+* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+    /*-------------- Reset DMA init structure parameters values ------------------*/
+    /* Initialize the DMA_PeripheralBaseAddr member */
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    /* Initialize the DMA_MemoryBaseAddr member */
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    /* Initialize the DMA_DIR member */
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    /* Initialize the DMA_BufferSize member */
+    DMA_InitStruct->DMA_BufferSize = 0;
+    /* Initialize the DMA_PeripheralInc member */
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    /* Initialize the DMA_MemoryInc member */
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    /* Initialize the DMA_PeripheralDataSize member */
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    /* Initialize the DMA_MemoryDataSize member */
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    /* Initialize the DMA_Mode member */
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    /* Initialize the DMA_Priority member */
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    /* Initialize the DMA_M2M member */
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+* @brief  Enables or disables the specified DMAy Channelx.
+* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+*   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
+*   DMA Channel.
+* @param NewState: new state of the DMAy Channelx.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected DMAy Channelx */
+        DMAy_Channelx->CCR |= CCR_ENABLE_Set;
+    }
+    else
+    {
+        /* Disable the selected DMAy Channelx */
+        DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified DMAy Channelx interrupts.
+* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+*   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
+*   DMA Channel.
+* @param DMA_IT: specifies the DMA interrupts sources to be enabled
+*   or disabled.
+*   This parameter can be any combination of the following values:
+* @arg DMA_IT_TC:  Transfer complete interrupt mask
+* @arg DMA_IT_HT:  Half transfer interrupt mask
+* @arg DMA_IT_TE:  Transfer error interrupt mask
+* @param NewState: new state of the specified DMA interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+    assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected DMA interrupts */
+        DMAy_Channelx->CCR |= DMA_IT;
+    }
+    else
+    {
+        /* Disable the selected DMA interrupts */
+        DMAy_Channelx->CCR &= ~DMA_IT;
+    }
+}
+
+/**
+* @brief  Returns the number of remaining data units in the current
+*   DMAy Channelx transfer.
+* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+*   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
+*   DMA Channel.
+* @retval : The number of remaining data units in the current DMAy Channelx
+*   transfer.
+*/
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+    /* Return the number of remaining data units for DMAy Channelx */
+    return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+* @brief  Checks whether the specified DMAy Channelx flag is set or not.
+* @param DMA_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+* @retval : The new state of DMA_FLAG (SET or RESET).
+*/
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+
+    /* Check the status of the specified DMA flag */
+    if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+    {
+        /* DMA_FLAG is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DMA_FLAG is reset */
+        bitstatus = RESET;
+    }
+
+    /* Return the DMA_FLAG status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the DMAy Channelx's pending flags.
+* @param DMA_FLAG: specifies the flag to clear.
+*   This parameter can be any combination (for the same DMA) of
+*   the following values:
+* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+* @retval : None
+*/
+void DMA_ClearFlag(uint32_t DMA_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+    /* Clear the selected DMA flags */
+    DMA1->IFCR = DMA_FLAG;
+}
+
+/**
+* @brief  Checks whether the specified DMAy Channelx interrupt has
+*   occurred or not.
+* @param DMA_IT: specifies the DMA interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+* @retval : The new state of DMA_IT (SET or RESET).
+*/
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_DMA_GET_IT(DMA_IT));
+
+    /* Get DMA1 ISR register value */
+    tmpreg = DMA1->ISR ;
+
+    /* Check the status of the specified DMA interrupt */
+    if ((tmpreg & DMA_IT) != (uint32_t)RESET)
+    {
+        /* DMA_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* DMA_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the DMA_IT status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the DMAy Channelx’s interrupt pending bits.
+* @param DMA_IT: specifies the DMA interrupt pending bit to clear.
+*   This parameter can be any combination (for the same DMA) of
+*   the following values:
+* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+* @retval : None
+*/
+void DMA_ClearITPendingBit(uint32_t DMA_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+
+    /* Clear the selected DMA interrupt pending bits */
+    DMA1->IFCR = DMA_IT;
+
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_exti.c

@@ -0,0 +1,262 @@
+/**
+******************************************************************************
+* @file    HAL_exti.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the EXTI firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_exti.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup EXTI
+* @brief EXTI driver modules
+* @{
+*/
+
+/** @defgroup EXTI_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Private_Defines
+* @{
+*/
+
+#define EXTI_LineNone    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup EXTI_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the EXTI peripheral registers to their default
+*   reset values.
+* @param  None
+* @retval : None
+*/
+void EXTI_DeInit(void)
+{
+    EXTI->IMR = 0x00000000;
+    EXTI->EMR = 0x00000000;
+    EXTI->RTSR = 0x00000000;
+    EXTI->FTSR = 0x00000000;
+    EXTI->PR = 0x001FFFFF;
+}
+
+/**
+* @brief  Initializes the EXTI peripheral according to the specified
+*   parameters in the EXTI_InitStruct.
+* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+*   that contains the configuration information for the EXTI
+*   peripheral.
+* @retval : None
+*/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+    assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+    assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
+    assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+    if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+
+        *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) |= EXTI_InitStruct->EXTI_Line;
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+
+        /* Select the trigger for the selected external interrupts */
+        if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            /* Rising Falling edge */
+            EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Trigger) |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        /* Disable the selected external lines */
+        *(__IO uint32_t *)(EXTI_BASE + (uint32_t)EXTI_InitStruct->EXTI_Mode) &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/**
+* @brief  Fills each EXTI_InitStruct member with its reset value.
+* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LineNone;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+* @brief  Generates a Software interrupt.
+* @param EXTI_Line: specifies the EXTI lines to be enabled or
+*   disabled.
+*   This parameter can be any combination of EXTI_Linex where
+*   x can be (0..18).
+* @retval : None
+*/
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+* @brief  Checks whether the specified EXTI line flag is set or not.
+* @param EXTI_Line: specifies the EXTI line flag to check.
+*   This parameter can be:
+* @arg EXTI_Linex: External interrupt line x where x(0..18)
+* @retval : The new state of EXTI_Line (SET or RESET).
+*/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+    if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the EXTI’s line pending flags.
+* @param EXTI_Line: specifies the EXTI lines flags to clear.
+*   This parameter can be any combination of EXTI_Linex where
+*   x can be (0..18).
+* @retval : None
+*/
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->PR = EXTI_Line;
+}
+
+/**
+* @brief  Checks whether the specified EXTI line is asserted or not.
+* @param EXTI_Line: specifies the EXTI line to check.
+*   This parameter can be:
+* @arg EXTI_Linex: External interrupt line x where x(0..18)
+* @retval : The new state of EXTI_Line (SET or RESET).
+*/
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+    /* Check the parameters */
+    assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+    enablestatus =  EXTI->IMR & EXTI_Line;
+    if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the EXTI’s line pending bits.
+* @param EXTI_Line: specifies the EXTI lines to clear.
+*   This parameter can be any combination of EXTI_Linex where
+*   x can be (0..18).
+* @retval : None
+*/
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+    /* Check the parameters */
+    assert_param(IS_EXTI_LINE(EXTI_Line));
+
+    EXTI->PR = EXTI_Line;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_flash.c

@@ -0,0 +1,930 @@
+/**
+******************************************************************************
+* @file    HAL_flash.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the FLASH firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_flash.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup FLASH
+* @brief FLASH driver modules
+* @{
+*/
+
+/** @defgroup FLASH_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Private_Defines
+* @{
+*/
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask         ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask          ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask          ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask          ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set                ((uint32_t)0x00000001)
+#define CR_PG_Reset              ((uint32_t)0x00001FFE)
+#define CR_PER_Set               ((uint32_t)0x00000002)
+#define CR_PER_Reset             ((uint32_t)0x00001FFD)
+#define CR_MER_Set               ((uint32_t)0x00000004)
+#define CR_MER_Reset             ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set             ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset           ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set             ((uint32_t)0x00000020)
+#define CR_OPTER_Reset           ((uint32_t)0x00001FDF)
+#define CR_STRT_Set              ((uint32_t)0x00000040)
+#define CR_LOCK_Set              ((uint32_t)0x00000080)
+
+/* FLASH Mask */
+#define RDPRT_Mask               ((uint32_t)0x00000002)
+#define WRP0_Mask                ((uint32_t)0x000000FF)
+#define WRP1_Mask                ((uint32_t)0x0000FF00)
+#define WRP2_Mask                ((uint32_t)0x00FF0000)
+#define WRP3_Mask                ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define RDP_Key                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+
+/* Delay definition */
+#define EraseTimeout             ((uint32_t)0x00000FFF)
+#define ProgramTimeout           ((uint32_t)0x0000000F)
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Private_FunctionPrototypes
+* @{
+*/
+
+static void delay(void);
+/**
+* @}
+*/
+
+/** @defgroup FLASH_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Sets the code latency value.
+* @param FLASH_Latency: specifies the FLASH Latency value.
+*   This parameter can be one of the following values:
+* @arg FLASH_Latency_0: FLASH Zero Latency cycle
+* @arg FLASH_Latency_1: FLASH One Latency cycle
+* @arg FLASH_Latency_2: FLASH Two Latency cycles
+* @arg FLASH_Latency_3: FLASH Three Latency cycles
+* @retval : None
+*/
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+    uint32_t tmpreg = 0;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+    /* Read the ACR register */
+    tmpreg = FLASH->ACR;
+
+    /* Sets the Latency value */
+    tmpreg &= ACR_LATENCY_Mask;
+    tmpreg |= FLASH_Latency;
+
+    /* Write the ACR register */
+    FLASH->ACR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the Half cycle flash access.
+* @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+*   This parameter can be one of the following values:
+* @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+* @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+* @retval : None
+*/
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));
+
+    /* Enable or disable the Half cycle access */
+    FLASH->ACR &= ACR_HLFCYA_Mask;
+    FLASH->ACR |= FLASH_HalfCycleAccess;
+}
+
+/**
+* @brief  Enables or disables the Prefetch Buffer.
+* @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.
+*   This parameter can be one of the following values:
+* @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable
+* @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable
+* @retval : None
+*/
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));
+
+    /* Enable or disable the Prefetch Buffer */
+    FLASH->ACR &= ACR_PRFTBE_Mask;
+    FLASH->ACR |= FLASH_PrefetchBuffer;
+}
+
+/**
+* @brief  Unlocks the FLASH Program Erase Controller.
+* @param  None
+* @retval : None
+*/
+void FLASH_Unlock(void)
+{
+    /* Authorize the FPEC Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/**
+* @brief  Locks the FLASH Program Erase Controller.
+* @param  None
+* @retval : None
+*/
+void FLASH_Lock(void)
+{
+    /* Set the Lock Bit to lock the FPEC and the FCR */
+    FLASH->CR |= CR_LOCK_Set;
+}
+
+/**
+* @brief  Erases a specified FLASH page.
+* @param Page_Address: The page address to be erased.
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_FLASH_ADDRESS(Page_Address));
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* if the previous operation is completed, proceed to erase the page */
+        FLASH->CR |= CR_PER_Set;
+        FLASH->AR = Page_Address;
+        FLASH->CR |= CR_STRT_Set;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+        if(status != FLASH_BUSY)
+        {
+            /* if the erase operation is completed, disable the PER Bit */
+            FLASH->CR &= CR_PER_Reset;
+        }
+    }
+
+    /* Return the Erase Status */
+    return status;
+}
+
+/**
+* @brief  Erases all FLASH pages.
+* @param  None
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* if the previous operation is completed, proceed to erase all pages */
+        FLASH->AR = 0x08000000;
+        FLASH->CR |= CR_MER_Set;
+        FLASH->CR |= CR_STRT_Set;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+        if(status != FLASH_BUSY)
+        {
+            /* if the erase operation is completed, disable the MER Bit */
+            FLASH->CR &= CR_MER_Reset;
+        }
+    }
+
+    /* Return the Erase Status */
+    return status;
+}
+
+/**
+* @brief  Erases the FLASH option bytes.
+* @param  None
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        /* Authorize the small information block programming */
+        FLASH->OPTKEYR = FLASH_KEY1;
+        FLASH->OPTKEYR = FLASH_KEY2;
+
+        /* if the previous operation is completed, proceed to erase the option bytes */
+        FLASH->CR |= CR_OPTER_Set;
+        FLASH->AR = 0x1FFFF800;
+        FLASH->CR |= CR_STRT_Set;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CR &= CR_OPTER_Reset;
+
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= CR_OPTPG_Set;
+
+            /* Enable the readout access */
+            OB->RDP = RDP_Key;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_BUSY)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if (status != FLASH_BUSY)
+            {
+                /* Disable the OPTPG Bit */
+                FLASH->CR &= CR_OPTPG_Reset;
+            }
+        }
+    }
+    /* Return the erase status */
+    return status;
+}
+
+/**
+* @brief  Programs a word at a specified address.
+* @param Address: specifies the address to be programmed.
+* @param Data: specifies the data to be programmed.
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_FLASH_ADDRESS(Address));
+
+
+
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* if the previous operation is completed, proceed to program the new first
+        half word */
+        FLASH->CR |= CR_PG_Set;
+
+        *(__IO uint16_t*)Address = (uint16_t)Data;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            /* if the previous operation is completed, proceed to program the new second
+            half word */
+            *(__IO uint16_t*)(Address + 2) = Data >> 16;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_BUSY)
+            {
+                /* Disable the PG Bit */
+                FLASH->CR &= CR_PG_Reset;
+            }
+        }
+        else
+        {
+            if (status != FLASH_BUSY)
+            {
+                /* Disable the PG Bit */
+                FLASH->CR &= CR_PG_Reset;
+            }
+        }
+    }
+
+
+    /* Return the Program Status */
+    return status;
+}
+
+/**
+* @brief  Programs a half word at a specified address.
+* @param Address: specifies the address to be programmed.
+* @param Data: specifies the data to be programmed.
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_FLASH_ADDRESS(Address));
+
+
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* if the previous operation is completed, proceed to program the new data */
+        FLASH->CR |= CR_PG_Set;
+
+        *(__IO uint16_t*)Address = Data;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        if(status != FLASH_BUSY)
+        {
+            /* if the program operation is completed, disable the PG Bit */
+            FLASH->CR &= CR_PG_Reset;
+        }
+    }
+
+
+    /* Return the Program Status */
+    return status;
+}
+
+/**
+* @brief  Programs a half word at a specified Option Byte Data address.
+* @param Address: specifies the address to be programmed.
+*   This parameter can be 0x1FFFF804 or 0x1FFFF806.
+* @param Data: specifies the data to be programmed.
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_OB_DATA_ADDRESS(Address));
+
+
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        /* Authorize the small information block programming */
+        FLASH->OPTKEYR = FLASH_KEY1;
+        FLASH->OPTKEYR = FLASH_KEY2;
+        /* Enables the Option Bytes Programming operation */
+        FLASH->CR |= CR_OPTPG_Set;
+        *(__IO uint16_t*)Address = Data;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        if(status != FLASH_BUSY)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= CR_OPTPG_Reset;
+        }
+    }
+
+
+
+    /* Return the Option Byte Data Program Status */
+    return status;
+}
+
+/**
+* @brief  Write protects the desired pages
+* @param FLASH_Pages: specifies the address of the pages to be
+*   write protected. This parameter can be:
+* @arg For microcontroller Medium-density devices (FLASH page size equal to 1 KB)
+* A value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages124to127
+* @arg For microcontroller High-density devices (FLASH page size equal to 2 KB)
+* A value between FLASH_WRProt_Pages0to1 and  FLASH_WRProt_Pages60to61
+* or FLASH_WRProt_Pages62to255
+* @arg FLASH_WRProt_AllPages
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+    uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));
+
+
+
+    FLASH_Pages = (uint32_t)(~FLASH_Pages);
+    WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+    WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+    WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+    WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Authorizes the small information block programming */
+        FLASH->OPTKEYR = FLASH_KEY1;
+        FLASH->OPTKEYR = FLASH_KEY2;
+        FLASH->CR |= CR_OPTPG_Set;
+        if(WRP0_Data != 0xFF)
+        {
+            OB->WRP0 = WRP0_Data;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+        if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+        {
+            OB->WRP1 = WRP1_Data;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+        if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+        {
+            OB->WRP2 = WRP2_Data;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+
+        if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
+        {
+            OB->WRP3 = WRP3_Data;
+
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+
+        if(status != FLASH_BUSY)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= CR_OPTPG_Reset;
+        }
+    }
+
+
+
+    /* Return the write protection operation Status */
+    return status;
+}
+
+/**
+* @brief  Enables or disables the read out protection.
+*   If the user has already programmed the other option bytes before
+*   calling this function, he must re-program them since this
+*   function erases all option bytes.
+* @param Newstate: new state of the ReadOut Protection.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        /* Authorizes the small information block programming */
+        FLASH->OPTKEYR = FLASH_KEY1;
+        FLASH->OPTKEYR = FLASH_KEY2;
+        FLASH->AR = 0x1ffff800;
+        FLASH->CR |= CR_OPTER_Set;
+        FLASH->CR |= CR_STRT_Set;
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+        if(status == FLASH_COMPLETE)
+        {
+            /* if the erase operation is completed, disable the OPTER Bit */
+            FLASH->CR &= CR_OPTER_Reset;
+            /* Enable the Option Bytes Programming operation */
+            FLASH->CR |= CR_OPTPG_Set;
+            if(NewState != DISABLE)
+            {
+                OB->RDP = 0x00;
+            }
+            else
+            {
+                OB->RDP = RDP_Key;
+            }
+            /* Wait for last operation to be completed */
+            status = FLASH_WaitForLastOperation(EraseTimeout);
+
+            if(status != FLASH_BUSY)
+            {
+                /* if the program operation is completed, disable the OPTPG Bit */
+                FLASH->CR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_BUSY)
+            {
+                /* Disable the OPTER Bit */
+                FLASH->CR &= CR_OPTER_Reset;
+            }
+        }
+    }
+
+
+
+    /* Return the protection operation Status */
+    return status;
+}
+
+/**
+* @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP /
+*   RST_STDBY.
+* @param OB_IWDG: Selects the IWDG mode
+*   This parameter can be one of the following values:
+* @arg OB_IWDG_SW: Software IWDG selected
+* @arg OB_IWDG_HW: Hardware IWDG selected
+* @param OB_STOP: Reset event when entering STOP mode.
+*   This parameter can be one of the following values:
+* @arg OB_STOP_NoRST: No reset generated when entering in STOP
+* @arg OB_STOP_RST: Reset generated when entering in STOP
+* @param OB_STDBY: Reset event when entering Standby mode.
+*   This parameter can be one of the following values:
+* @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    /* Check the parameters */
+    assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+    assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+    assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+
+
+    /* Authorize the small information block programming */
+    FLASH->OPTKEYR = FLASH_KEY1;
+    FLASH->OPTKEYR = FLASH_KEY2;
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        /* Enable the Option Bytes Programming operation */
+        FLASH->CR |= CR_OPTPG_Set;
+
+        OB->USER = ( OB_IWDG | OB_STOP | OB_STDBY) | (uint16_t)0xF8;
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        if(status != FLASH_BUSY)
+        {
+            /* if the program operation is completed, disable the OPTPG Bit */
+            FLASH->CR &= CR_OPTPG_Reset;
+        }
+    }
+
+
+
+    /* Return the Option Byte program Status */
+    return status;
+}
+
+/**
+* @brief  Returns the FLASH User Option Bytes values.
+* @param  None
+* @retval : The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+*   and RST_STDBY(Bit2).
+*/
+uint32_t FLASH_GetUserOptionByte(void)
+{
+    /* Return the User Option Byte */
+    return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/**
+* @brief  Returns the FLASH Write Protection Option Bytes Register value.
+* @param  None
+* @retval : The FLASH Write Protection  Option Bytes Register value
+*/
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+    /* Return the Falsh write protection Register value */
+    return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+* @brief  Checks whether the FLASH Read Out Protection Status is set
+*   or not.
+* @param  None
+* @retval : FLASH ReadOut Protection Status(SET or RESET)
+*/
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/**
+* @brief  Checks whether the FLASH Prefetch Buffer status is set or not.
+* @param  None
+* @retval : FLASH Prefetch Buffer Status (SET or RESET).
+*/
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+* @brief  Enables or disables the specified FLASH interrupts.
+* @param FLASH_IT: specifies the FLASH interrupt sources to be
+*   enabled or disabled.
+*   This parameter can be any combination of the following values:
+* @arg FLASH_IT_ERROR: FLASH Error Interrupt
+* @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+* @param NewState: new state of the specified Flash interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void FLASH_ITConfig(uint16_t FLASH_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_IT(FLASH_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if(NewState != DISABLE)
+    {
+        /* Enable the interrupt sources */
+        FLASH->CR |= FLASH_IT;
+    }
+    else
+    {
+        /* Disable the interrupt sources */
+        FLASH->CR &= ~(uint32_t)FLASH_IT;
+    }
+}
+
+/**
+* @brief  Checks whether the specified FLASH flag is set or not.
+* @param FLASH_FLAG: specifies the FLASH flag to check.
+*   This parameter can be one of the following values:
+* @arg FLASH_FLAG_BSY: FLASH Busy flag
+* @arg FLASH_FLAG_PGERR: FLASH Program error flag
+* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+* @arg FLASH_FLAG_OPTERR:  FLASH Option Byte error flag
+* @retval : The new state of FLASH_FLAG (SET or RESET).
+*/
+FlagStatus FLASH_GetFlagStatus(uint16_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;
+    if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+    {
+        if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    /* Return the new state of FLASH_FLAG (SET or RESET) */
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the FLASH’s pending flags.
+* @param FLASH_FLAG: specifies the FLASH flags to clear.
+*   This parameter can be any combination of the following values:
+* @arg FLASH_FLAG_BSY: FLASH Busy flag
+* @arg FLASH_FLAG_PGERR: FLASH Program error flag
+* @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag
+* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+* @retval : None
+*/
+void FLASH_ClearFlag(uint16_t FLASH_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;
+
+    /* Clear the flags */
+    FLASH->SR = FLASH_FLAG;
+}
+
+/**
+* @brief  Returns the FLASH Status.
+* @param  None
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP or FLASH_COMPLETE
+*/
+FLASH_Status FLASH_GetStatus(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if(FLASH->SR & FLASH_FLAG_PGERR)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if(FLASH->SR & FLASH_FLAG_WRPRTERR)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    /* Return the Flash Status */
+    return flashstatus;
+}
+
+/**
+* @brief  Waits for a Flash operation to complete or a TIMEOUT to occur.
+* @param Timeout: FLASH progamming Timeout
+* @retval : FLASH Status: The returned value can be: FLASH_BUSY,
+*   FLASH_ERROR_PG, FLASH_ERROR_WRP, FLASH_COMPLETE or
+*   FLASH_TIMEOUT.
+*/
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+
+
+    /* Check for the Flash Status */
+    status = FLASH_GetStatus();
+    /* Wait for a Flash operation to complete or a TIMEOUT to occur */
+    while((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        delay();
+        status = FLASH_GetStatus();
+        Timeout--;
+    }
+    if(Timeout == 0x00 )
+    {
+        status = FLASH_TIMEOUT;
+    }
+
+
+
+    /* Return the operation status */
+    return status;
+}
+
+/**
+* @brief  Inserts a time delay.
+* @param  None
+* @retval : None
+*/
+static void delay(void)
+{
+    __IO uint32_t i = 0;
+    for(i = 0xFF; i != 0; i--)
+    {
+    }
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_gpio.c

@@ -0,0 +1,574 @@
+/**
+******************************************************************************
+* @file    HAL_gpio.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the GPIO firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_gpio.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup GPIO
+* @brief GPIO driver modules
+* @{
+*/
+
+/** @defgroup GPIO_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Private_Defines
+* @{
+*/
+
+/* ------------ RCC registers bit address in the alias region ----------------*/
+#define AFIO_OFFSET                 (AFIO_BASE - PERIPH_BASE)
+
+/* --- EVENTCR Register -----*/
+
+/* Alias word address of EVOE bit */
+#define EVCR_OFFSET                 (AFIO_OFFSET + 0x00)
+#define EVOE_BitNumber              ((uint8_t)0x07)
+#define EVCR_EVOE_BB                (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
+#define EVCR_PORTPINCONFIG_MASK     ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xFFFFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup GPIO_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the GPIOx peripheral registers to their default
+*   reset values.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @retval : None
+*/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    switch (*(uint32_t*)&GPIOx)
+    {
+        case GPIOA_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+            break;
+        case GPIOB_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+            break;
+        case GPIOC_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+            break;
+        case GPIOD_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Deinitializes the Alternate Functions (remap, event control
+*   and EXTI configuration) registers to their default reset
+*   values.
+* @param  None
+* @retval : None
+*/
+void GPIO_AFIODeInit(void)
+{
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/**
+* @brief  Initializes the GPIOx peripheral according to the specified
+*   parameters in the GPIO_InitStruct.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+*   contains the configuration information for the specified GPIO
+*   peripheral.
+* @retval : None
+*/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+    uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+    uint32_t tmpreg = 0x00, pinmask = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+    assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+
+    /*---------------------------- GPIO Mode Configuration -----------------------*/
+    currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+    if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+    {
+        /* Check the parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+        /* Output mode */
+        currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+    }
+    /*---------------------------- GPIO CRL Configuration ------------------------*/
+    /* Configure the eight low port pins */
+    if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+    {
+        tmpreg = GPIOx->CRL;
+        for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = ((uint32_t)0x01) << pinpos;
+            /* Get the port pins position */
+            currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+            if (currentpin == pos)
+            {
+                pos = pinpos << 2;
+                /* Clear the corresponding low control register bits */
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                /* Write the mode configuration in the corresponding bits */
+                tmpreg |= (currentmode << pos);
+                /* Reset the corresponding ODR bit */
+                if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BRR = (((uint32_t)0x01) << pinpos);
+                }
+                else
+                {
+                    /* Set the corresponding ODR bit */
+                    if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                    {
+                        GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
+                    }
+                }
+            }
+        }
+        GPIOx->CRL = tmpreg;
+    }
+    /*---------------------------- GPIO CRH Configuration ------------------------*/
+    /* Configure the eight high port pins */
+    if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+    {
+        tmpreg = GPIOx->CRH;
+        for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = (((uint32_t)0x01) << (pinpos + 0x08));
+            /* Get the port pins position */
+            currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+            if (currentpin == pos)
+            {
+                pos = pinpos << 2;
+                /* Clear the corresponding high control register bits */
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                /* Write the mode configuration in the corresponding bits */
+                tmpreg |= (currentmode << pos);
+                /* Reset the corresponding ODR bit */
+                if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+                /* Set the corresponding ODR bit */
+                if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                {
+                    GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+            }
+        }
+        GPIOx->CRH = tmpreg;
+    }
+}
+
+/**
+* @brief  Fills each GPIO_InitStruct member with its default value.
+* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+    /* Reset GPIO init structure parameters values */
+    GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/**
+* @brief  Reads the specified input port pin.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin:  specifies the port bit to read.
+*   This parameter can be GPIO_Pin_x where x can be (0..15).
+* @retval : The input port pin value.
+*/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Reads the specified GPIO input data port.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @retval : GPIO input data port value.
+*/
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+* @brief  Reads the specified output data port bit.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin:  specifies the port bit to read.
+*   This parameter can be GPIO_Pin_x where x can be (0..15).
+* @retval : The output port pin value.
+*/
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+    if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Reads the specified GPIO output data port.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @retval : GPIO output data port value.
+*/
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+* @brief  Sets the selected data port bits.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin: specifies the port bits to be written.
+*   This parameter can be any combination of GPIO_Pin_x where
+*   x can be (0..15).
+* @retval : None
+*/
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+* @brief  Clears the selected data port bits.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin: specifies the port bits to be written.
+*   This parameter can be any combination of GPIO_Pin_x where
+*   x can be (0..15).
+* @retval : None
+*/
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+* @brief  Sets or clears the selected data port bit.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin: specifies the port bit to be written.
+*   This parameter can be one of GPIO_Pin_x where x can be (0..15).
+* @param BitVal: specifies the value to be written to the selected bit.
+*   This parameter can be one of the BitAction enum values:
+* @arg Bit_RESET: to clear the port pin
+* @arg Bit_SET: to set the port pin
+* @retval : None
+*/
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+    assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+    if (BitVal != Bit_RESET)
+    {
+        GPIOx->BSRR = GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->BRR = GPIO_Pin;
+    }
+}
+
+/**
+* @brief  Writes data to the specified GPIO data port.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param PortVal: specifies the value to be written to the port output
+*   data register.
+* @retval : None
+*/
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+    GPIOx->ODR = PortVal;
+}
+
+/**
+* @brief  Locks GPIO Pins configuration registers.
+* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
+* @param GPIO_Pin: specifies the port bit to be written.
+*   This parameter can be any combination of GPIO_Pin_x where
+*   x can be (0..15).
+* @retval : None
+*/
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+    uint32_t tmp = 0x00010000;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+    assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+    tmp |= GPIO_Pin;
+    /* Set LCKK bit */
+    GPIOx->LCKR = tmp;
+    /* Reset LCKK bit */
+    GPIOx->LCKR =  GPIO_Pin;
+    /* Set LCKK bit */
+    GPIOx->LCKR = tmp;
+    /* Read LCKK bit*/
+    tmp = GPIOx->LCKR;
+    /* Read LCKK bit*/
+    tmp = GPIOx->LCKR;
+}
+
+/**
+* @brief  Selects the GPIO pin used as Event output.
+* @param GPIO_PortSource: selects the GPIO port to be used as source
+*   for Event output.
+*   This parameter can be GPIO_PortSourceGPIOx where x can be
+*   (A..E).
+* @param GPIO_PinSource: specifies the pin for the Event output.
+*   This parameter can be GPIO_PinSourcex where x can be (0..15).
+* @retval : None
+*/
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmpreg = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));
+    assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+    tmpreg = AFIO->EVCR;
+    /* Clear the PORT[6:4] and PIN[3:0] bits */
+    tmpreg &= EVCR_PORTPINCONFIG_MASK;
+    tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+    tmpreg |= GPIO_PinSource;
+    AFIO->EVCR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the Event Output.
+* @param NewState: new state of the Event output.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;
+}
+
+/**
+* @brief  Changes the mapping of the specified pin.
+* @param GPIO_Remap: selects the pin to remap.
+*   This parameter can be one of the following values:
+* @arg GPIO_Remap_SPI1
+* @arg GPIO_Remap_I2C1
+* @arg GPIO_Remap_UART1
+* @arg GPIO_Remap_UART2
+* @arg GPIO_PartialRemap_UART3
+* @arg GPIO_FullRemap_UART3
+* @arg GPIO_PartialRemap_TIM1
+* @arg GPIO_FullRemap_TIM1
+* @arg GPIO_PartialRemap1_TIM2
+* @arg GPIO_PartialRemap2_TIM2
+* @arg GPIO_FullRemap_TIM2
+* @arg GPIO_PartialRemap_TIM3
+* @arg GPIO_FullRemap_TIM3
+* @arg GPIO_Remap_TIM4
+* @arg GPIO_Remap1_CAN1
+* @arg GPIO_Remap2_CAN1
+* @arg GPIO_Remap_PD01
+* @arg GPIO_Remap_TIM5CH4_LSI
+* @arg GPIO_Remap_ADC1_ETRGINJ
+* @arg GPIO_Remap_ADC1_ETRGREG
+* @arg GPIO_Remap_ADC2_ETRGINJ
+* @arg GPIO_Remap_ADC2_ETRGREG
+* @arg GPIO_Remap_SWJ_NoJTRST
+* @arg GPIO_Remap_SWJ_JTAGDisable
+* @arg GPIO_Remap_SWJ_Disable
+* @param NewState: new state of the port pin remapping.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+    uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_REMAP(GPIO_Remap));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmpreg = AFIO->MAPR;
+    tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+    tmp = GPIO_Remap & LSB_MASK;
+    if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+    {
+        tmpreg &= DBGAFR_SWJCFG_MASK;
+        AFIO->MAPR &= DBGAFR_SWJCFG_MASK;
+    }
+    else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+    {
+        tmp1 = ((uint32_t)0x03) << tmpmask;
+        tmpreg &= ~tmp1;
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+    else
+    {
+        tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+    if (NewState != DISABLE)
+    {
+        tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
+    }
+    AFIO->MAPR = tmpreg;
+}
+
+/**
+* @brief  Selects the GPIO pin used as EXTI Line.
+* @param GPIO_PortSource: selects the GPIO port to be used as
+*   source for EXTI lines.
+*   This parameter can be GPIO_PortSourceGPIOx where x can be
+*   (A..G).
+* @param GPIO_PinSource: specifies the EXTI line to be configured.
+*   This parameter can be GPIO_PinSourcex where x can be (0..15).
+* @retval : None
+*/
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmp = 0x00;
+    /* Check the parameters */
+    assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));
+    assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+
+    tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_i2c.c

@@ -0,0 +1,818 @@
+/**
+******************************************************************************
+* @file    HAL_i2c.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the I2C firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_i2c.h"
+#include "HAL_rcc.h"
+
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup I2C
+* @brief I2C driver modules
+* @{
+*/
+
+/** @defgroup I2C_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Private_Defines
+* @{
+*/
+
+/*I2c Enable disable*/
+#define IC_ENABLE_Reset         ((uint16_t)0xFFFE)
+#define IC_ENABLE_Set           ((uint16_t)0x0001)
+#define IC_CON_RESET						((uint16_t)0xFE8A)
+#define INTR_MASK               ((uint16_t)0xC000)
+
+/*I2c DMA  reset*/
+#define DMA_CR_TDMAE_RDMAE_Reset ((uint16_t)0xFFFC)
+
+/* I2C START mask */
+#define IC_CON_START_Set           ((uint16_t)0x0020)
+#define IC_CON_START_Reset         ((uint16_t)0xFFDF)
+
+/* I2C STOP mask */
+#define IC_DATA_CMD_STOP_Set     ((uint16_t)0x0200)
+#define IC_DATA_CMD_STOP_Reset   ((uint16_t)0xFDFF)
+
+/* I2C ADD2 mask */
+#define IC_TAR_Reset         ((uint16_t)0xFF00)
+
+/* I2C IC_10BITADDR_MASTER bit mask */
+#define IC_TAR_ENDUAL_Set         ((uint16_t)0x1000)
+#define IC_TAR_ENDUAL_Reset       ((uint16_t)0xEFFF)
+
+/* I2C SPECIAL、GC_OR_START bits mask */
+#define IC_TAR_GC_Set            ((uint16_t)0x0800)
+#define IC_TAR_GC_Reset          ((uint16_t)0xF7FF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask               ((uint32_t)0x00793FFF)
+
+
+static uint8_t I2C_CMD_DIR = 0;
+
+/*新增加的用户变量，外部调用时需要更新该变量值*/
+uint16_t I2C_DMA_DIR = 0;
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup I2C_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the I2Cx peripheral registers to their default
+*   reset values.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @retval : None
+*/
+void I2C_DeInit(I2C_TypeDef* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    switch (*(uint32_t*)&I2Cx)
+    {
+        case I2C1_BASE:
+            /* Enable I2C1 reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+            /* Release I2C1 from reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+            break;
+        case I2C2_BASE:
+            /* Enable I2C2 reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+            /* Release I2C2 from reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the I2Cx peripheral according to the specified
+*   parameters in the I2C_InitStruct.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
+*   contains the configuration information for the specified
+*   I2C peripheral.
+* @retval : None
+*/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
+{
+
+    uint16_t tmpreg = 0;
+    uint32_t pclk1 = 8000000;
+    uint32_t minSclLowTime = 0;
+    uint32_t i2cPeriod = 0;
+    uint32_t pclk1Period = 0;
+    RCC_ClocksTypeDef  rcc_clocks;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+    assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));
+    /*---------------------------- I2Cx IC_ENABLE Configuration ------------------------*/
+    /* Disable the selected I2C peripheral */
+    I2Cx->IC_ENABLE &= IC_ENABLE_Reset;
+
+    /* Get pclk1 frequency value */
+    RCC_GetClocksFreq(&rcc_clocks);
+    pclk1 = rcc_clocks.PCLK1_Frequency;
+
+    /* Set pclk1 period value */
+    pclk1Period = 1000000000 / pclk1;
+
+    i2cPeriod = 1000000000 / I2C_InitStruct->I2C_ClockSpeed; //ns unit
+    tmpreg = 0;
+    /* Configure speed in standard mode */
+    if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+    {
+        /* Standard mode speed calculate */
+        minSclLowTime = 4700; //ns unit
+        tmpreg = minSclLowTime / pclk1Period;
+        /* Write to I2Cx IC_SS_SCL_LCNT */
+        I2Cx->IC_SS_SCL_LCNT = tmpreg;
+        tmpreg = (i2cPeriod - pclk1Period * I2Cx->IC_SS_SCL_LCNT) / pclk1Period;
+        /* Write to I2Cx IC_SS_SCL_HCNT */
+        I2Cx->IC_SS_SCL_HCNT = tmpreg;
+
+
+    }
+    else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+    {
+        /* Configure speed in fast mode */
+        minSclLowTime = 1300; //ns unit
+        tmpreg = minSclLowTime / pclk1Period;
+        /* Write to I2Cx IC_FS_SCL_LCNT */
+        I2Cx->IC_FS_SCL_LCNT = tmpreg;
+        tmpreg = (i2cPeriod - pclk1Period * I2Cx->IC_FS_SCL_LCNT) / pclk1Period;
+        /* Write to I2Cx IC_FS_SCL_HCNT */
+        I2Cx->IC_FS_SCL_HCNT = tmpreg;
+    }
+
+    /*Get the I2Cx IC_CON value */
+    tmpreg = I2Cx->IC_CON;
+    /*Clear TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
+    tmpreg &= IC_CON_RESET;
+    /*Set TX_EMPTY_CTRL,IC_SLAVE_DISABLE,IC_RESTART_EN,IC_10BITADDR_SLAVE,SPEED,MASTER_MODE bits*/
+    tmpreg = TX_EMPTY_CTRL | IC_SLAVE_DISABLE | IC_RESTART_EN | IC_7BITADDR_MASTER | I2C_InitStruct->I2C_Speed | I2C_InitStruct->I2C_Mode;
+    /* Write to I2Cx IC_CON */
+    I2Cx->IC_CON = tmpreg;
+
+    /*---------------------------- I2Cx IC_INTR_MASK Configuration ------------------------*/
+    /* Get the I2Cx IC_INTR_MASK value */
+    tmpreg = I2Cx->IC_INTR_MASK;
+    /* clear the I2Cx IC_INTR_MASK value */
+    tmpreg &= INTR_MASK;
+    /* Write to IC_INTR_MASK */
+    I2Cx->IC_INTR_MASK = tmpreg;
+
+    /* Write to IC_RX_TL  */
+    I2Cx->IC_RX_TL = 0x0; //rxfifo depth is 1
+    /* Write to IC_TX_TL  */
+    I2Cx->IC_TX_TL = 0x1; //tcfifo depth is 1
+
+}
+
+/**
+* @brief  Fills each I2C_InitStruct member with its default value.
+* @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+    /*---------------- Reset I2C init structure parameters values ----------------*/
+    /* Initialize the I2C_Mode member */
+    I2C_InitStruct->I2C_Mode = I2C_Mode_MASTER;
+    /* Initialize the I2C_OwnAddress member */
+    I2C_InitStruct->I2C_OwnAddress = 0xA8;
+    /* Initialize the I2C_Speed member */
+    I2C_InitStruct->I2C_Speed = I2C_Speed_STANDARD;
+    /* initialize the I2C_ClockSpeed member */
+    I2C_InitStruct->I2C_ClockSpeed = 100000;
+}
+
+/**
+* @brief  Enables or disables the specified I2C peripheral.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param NewState: new state of the I2Cx peripheral. This parameter
+*   can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C peripheral */
+        I2Cx->IC_ENABLE |= IC_ENABLE_Set;
+    }
+    else
+    {
+        /* Disable the selected I2C peripheral */
+        I2Cx->IC_ENABLE &= IC_ENABLE_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified I2C DMA requests.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param	DMA_Direcction : TDMAE_SET,RDMAE_SET
+*   This parameter can be any combination of the following values:
+* @arg TDMAE_SET	:DMA TX set
+* @arg RDMAE_SET	:DMA RX set
+* @param NewState: new state of the I2C DMA transfer.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C DMA requests */
+        if(I2C_DMA_DIR == TDMAE_SET)
+        {
+            /* Enable the selected I2C TX DMA requests */
+            I2Cx->IC_DMA_CR |= TDMAE_SET;
+        }
+        else if(I2C_DMA_DIR == RDMAE_SET)
+        {
+            /* Enable the selected I2C TX DMA requests */
+            I2Cx->IC_DMA_CR |= RDMAE_SET;
+        }
+    }
+    else
+    {
+        /* Disable the selected I2C DMA requests */
+        I2Cx->IC_DMA_CR &= DMA_CR_TDMAE_RDMAE_Reset;
+    }
+}
+
+
+/**
+* @brief  Generates I2Cx communication START condition.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param NewState: new state of the I2C START condition generation.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None.
+*/
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Generate a START condition */
+        I2Cx->IC_CON |= IC_CON_START_Set;
+    }
+    else
+    {
+        /* Disable the START condition generation */
+        I2Cx->IC_CON &= IC_CON_START_Reset;
+    }
+}
+
+/**
+* @brief  Generates I2Cx communication STOP condition.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param NewState: new state of the I2C STOP condition generation.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None.
+*/
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    u16 overTime = 3000;
+    I2Cx->IC_ENABLE |= 0x02;
+    while(I2Cx->IC_ENABLE & 0x02)
+    {
+        if(0 == overTime --)
+        {
+            break;
+        }
+    }
+    I2Cx->IC_CLR_TX_ABRT;
+}
+
+/**
+* @brief  Configures the specified I2C own address2.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param Address: specifies the 7bit I2C own address2.
+* @retval : None.
+*/
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+//void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+    uint16_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    /* Get the old register value */
+    tmpreg = I2Cx->IC_TAR;
+    /* Reset I2Cx Own address2 bit [7:0] */
+    tmpreg &= IC_TAR_Reset;
+    /* Set I2Cx Own address2 */
+    tmpreg |= Address >> 1;
+    /* Store the new register value */
+    I2Cx->IC_TAR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the specified I2C dual addressing mode.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param NewState: new state of the I2C dual addressing mode.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable dual addressing mode */
+        I2Cx->IC_TAR |= IC_TAR_ENDUAL_Set;
+    }
+    else
+    {
+        /* Disable dual addressing mode */
+        I2Cx->IC_TAR &= IC_TAR_ENDUAL_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified I2C general call feature.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param NewState: new state of the I2C General call.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable generall call */
+        I2Cx->IC_TAR |= IC_TAR_GC_Set;
+    }
+    else
+    {
+        /* Disable generall call */
+        I2Cx->IC_TAR &= IC_TAR_GC_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified I2C interrupts.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_IT: specifies the I2C interrupts sources to be enabled
+*   or disabled.
+*   This parameter can be any combination of the following values:
+* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt mask
+* @arg I2C_IT_RX_OVER : RX  Buffer Overrun interrupt mask
+* @arg I2C_IT_RX_FULL : Rx buffer full interrupt mask
+* @arg I2C_IT_TX_OVER : TX  Buffer Overrun interrupt mask
+* @arg I2C_IT_TX_EMPTY	: TX_FIFO empty interrupt mask
+* @arg I2C_IT_RD_REQ	: I2C work as slave or master interrupt mask
+* @arg I2C_IT_TX_ABRT	: TX error interrupt  mask(Master mode)
+* @arg I2C_IT_RX_DONE	: Master not ack interrupt mask(slave mode)
+* @arg I2C_IT_ACTIVITY	: I2C activity interrupt mask
+* @arg I2C_IT_STOP_DET	: stop condition  interrupt mask
+* @arg I2C_IT_START_DET	: start condition  interrupt mask
+* @arg I2C_IT_GEN_CALL	: a general call address and ack interrupt mask
+* @param NewState: new state of the specified I2C interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+    if(I2C_IT == I2C_IT_RX_FULL)
+    {
+        I2Cx->IC_DATA_CMD = CMD_READ;
+    }
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK |= I2C_IT;
+    }
+    else
+    {
+        /* Disable the selected I2C interrupts */
+        I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT;
+    }
+}
+
+/**
+* @brief  Sends a data byte through the I2Cx peripheral.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param Data: Byte to be transmitted..
+* @retval : None
+*/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    /* Write in the IC_DATA_CMD register the data to be sent */
+    I2Cx->IC_DATA_CMD = CMD_WRITE | Data;
+}
+
+/**
+* @brief  Returns the most recent received data by the I2Cx peripheral.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @retval : The value of the received data.
+
+*/
+void I2C_ReadCmd(I2C_TypeDef* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+    I2Cx->IC_DATA_CMD = CMD_READ;
+}
+
+/**
+* @brief  Returns the most recent received data by the I2Cx peripheral.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @retval : The value of the received data.
+*/
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    I2C_CMD_DIR = 0;
+    /* Return the data in the IC_DATA_CMD register */
+    return (uint8_t)I2Cx->IC_DATA_CMD;
+}
+
+/**
+* @brief  Transmits the address byte to select the slave device.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param Address: specifies the slave address which will be transmitted
+* @param I2C_Direction: specifies whether the I2C device will be a
+*   Transmitter or a Receiver.
+*   This parameter can be one of the following values
+* @arg I2C_Direction_Transmitter: Transmitter mode
+* @arg I2C_Direction_Receiver: Receiver mode
+* @retval : None.
+*/
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+    /* Store the new register value */
+    I2Cx->IC_TAR = Address >> 1;
+}
+
+/**
+* @brief  Reads the specified I2C register and returns its value.
+* @param I2C_Register: specifies the register to read.
+*   This parameter can be one of the following values:
+* @retval : The value of the read register.
+*/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_REGISTER(I2C_Register));
+    /* Return the selected register value */
+    return (*(__IO uint16_t *)(*((__IO uint32_t *)&I2Cx) + I2C_Register));
+}
+
+/**
+* @brief  Returns the last I2Cx Event.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @retval : The last event
+*/
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    /* Read the I2Cx status register */
+    flag1 = I2Cx->IC_RAW_INTR_STAT;
+
+    /* Get the last event value from I2C status register */
+    lastevent = (flag1 ) & FLAG_Mask;
+    /* Return status */
+    return lastevent;
+}
+
+
+
+/**
+* @brief  Checks whether the last I2Cx Event is equal to the one passed
+*   as parameter.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_EVENT: specifies the event to be checked.
+*   This parameter can be one of the following values:
+* @arg I2C_EVENT_RX_UNDER: Rx Buffer is empty event
+* @arg I2C_EVENT_RX_OVER : RX  Buffer Overrun event
+* @arg I2C_EVENTT_RX_FULL : Rx buffer full event
+* @arg I2C_EVENT_TX_OVER : TX  Buffer Overrun event
+* @arg I2C_EVENT_TX_EMPTY	: TX_FIFO empty event
+* @arg I2C_EVENT_RD_REQ	: I2C work as slave or master event
+* @arg I2C_EVENT_TX_ABRT	: TX error event(Master mode)
+* @arg I2C_EVENT_RX_DONE	: Master not ack event(slave mode)
+* @arg I2C_EVENT_ACTIVITY	: I2C activity event
+* @arg I2C_EVENT_STOP_DET	: stop condition  event
+* @arg I2C_EVENT_START_DET	: start condition  event
+* @arg I2C_EVENT_GEN_CALL	: a general call address and ack event
+* - SUCCESS: Last event is equal to the I2C_EVENT
+* - ERROR: Last event is different from the I2C_EVENT
+*/
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0;
+    ErrorStatus status = ERROR;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+    if((I2C_EVENT == I2C_EVENT_RX_FULL) && (I2C_CMD_DIR == 0))
+    {
+        I2Cx->IC_DATA_CMD = CMD_READ;
+        I2C_CMD_DIR = 1;
+    }
+    /* Read the I2Cx status register */
+    flag1 = I2Cx->IC_RAW_INTR_STAT;
+    //flag1 = I2Cx->IC_INTR_STAT;
+    /* Get the last event value from I2C status register */
+    lastevent = (flag1 ) & I2C_EVENT;
+
+    /* Check whether the last event is equal to I2C_EVENT */
+    if (lastevent == I2C_EVENT )
+        //if((I2Cx->IC_RAW_INTR_STAT & I2C_EVENT) != (uint32_t)RESET)
+    {
+        /* SUCCESS: last event is equal to I2C_EVENT */
+        status = SUCCESS;
+    }
+    else
+    {
+        /* ERROR: last event is different from I2C_EVENT */
+        status = ERROR;
+    }
+    /* Return status */
+    return status;
+
+}
+
+/**
+* @brief  Checks whether the specified I2C flag is set or not.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag
+* @arg I2C_FLAG_RX_OVER : RX  Buffer Overrun flag
+* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
+* @arg I2C_FLAG_TX_OVER : TX  Buffer Overrun flag
+* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
+* @arg I2C_FLAG_RD_REQ	: I2C work as slave or master flag
+* @arg I2C_FLAG_TX_ABRT	: TX error flag(Master mode)
+* @arg I2C_FLAG_RX_DONE	: Master not ack flag(slave mode)
+* @arg I2C_FLAG_ACTIVITY: I2C activity flag
+* @arg I2C_FLAG_STOP_DET: stop condition  flag
+* @arg I2C_FLAG_START_DET: start condition  flag
+* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
+* @retval : The new state of I2C_FLAG (SET or RESET).
+*/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+    if(I2C_FLAG & 0x8000)
+    {
+        if((I2Cx->IC_STATUS & I2C_FLAG) != (uint32_t)RESET)
+        {
+            /* I2C_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* I2C_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((I2C_FLAG == I2C_FLAG_RX_FULL) && (I2C_CMD_DIR == 0))
+        {
+            I2Cx->IC_DATA_CMD = CMD_READ;
+            I2C_CMD_DIR = 1;
+        }
+        /* Check the status of the specified I2C flag */
+        if((I2Cx->IC_RAW_INTR_STAT & I2C_FLAG) != (uint32_t)RESET)
+        {
+            /* I2C_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* I2C_FLAG is reset */
+            bitstatus = RESET;
+        }
+    }
+
+    /* Return the I2C_FLAG status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the I2Cx's pending flags.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_FLAG: specifies the flag to clear.
+*   This parameter can be any combination of the following values:
+* @arg I2C_FLAG_RX_UNDER: Rx Buffer is empty flag
+* @arg I2C_FLAG_RX_OVER : RX  Buffer Overrun flag
+* @arg I2C_FLAG_RX_FULL : Rx buffer full flag
+* @arg I2C_FLAG_TX_OVER : TX  Buffer Overrun flag
+* @arg I2C_FLAG_TX_EMPTY: TX_FIFO empty flag
+* @arg I2C_FLAG_RD_REQ	: I2C work as slave or master flag
+* @arg I2C_FLAG_TX_ABRT	: TX error flag(Master mode)
+* @arg I2C_FLAG_RX_DONE	: Master not ack flag(slave mode)
+* @arg I2C_FLAG_ACTIVITY: I2C activity flag
+* @arg I2C_FLAG_STOP_DET: stop condition  flag
+* @arg I2C_FLAG_START_DET: start condition  flag
+* @arg I2C_FLAG_GEN_CALL : a general call address and ack flag
+* @retval : None
+*/
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+    if((I2C_FLAG & I2C_FLAG_RX_UNDER) 	== I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;}
+    if((I2C_FLAG & I2C_FLAG_RX_OVER)	== I2C_FLAG_RX_OVER)  {I2Cx->IC_CLR_RX_OVER;}
+    if((I2C_FLAG & I2C_FLAG_TX_OVER) 	== I2C_FLAG_TX_OVER)  {I2Cx->IC_CLR_TX_OVER;}
+    if((I2C_FLAG & I2C_FLAG_RD_REQ) 	== I2C_FLAG_RD_REQ)   {I2Cx->IC_CLR_RD_REQ;}
+    if((I2C_FLAG & I2C_FLAG_TX_ABRT) 	== I2C_FLAG_TX_ABRT)  {I2Cx->IC_CLR_TX_ABRT;}
+    if((I2C_FLAG & I2C_FLAG_RX_DONE) 	== I2C_FLAG_RX_DONE)  {I2Cx->IC_CLR_RX_DONE;}
+    if((I2C_FLAG & I2C_FLAG_ACTIVITY) 	== I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;}
+    if((I2C_FLAG & I2C_FLAG_STOP_DET) 	== I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;}
+    if((I2C_FLAG & I2C_FLAG_START_DET) 	== I2C_FLAG_START_DET) {I2Cx->IC_CLR_START_DET;}
+    if((I2C_FLAG & I2C_FLAG_GEN_CALL) 	== I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;}
+}
+
+/**
+* @brief  Checks whether the specified I2C interrupt has occurred or not.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_IT: specifies the interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt
+* @arg I2C_IT_RX_OVER : RX  Buffer Overrun interrupt
+* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
+* @arg I2C_IT_TX_OVER : TX  Buffer Overrun interrupt
+* @arg I2C_IT_TX_EMPTY	: TX_FIFO empty interrupt
+* @arg I2C_IT_RD_REQ	: I2C work as slave or master interrupt
+* @arg I2C_IT_TX_ABRT	: TX error interrupt  (Master mode)
+* @arg I2C_IT_RX_DONE	: Master not ack interrupt (slave mode)
+* @arg I2C_IT_ACTIVITY	: I2C activity interrupt
+* @arg I2C_IT_STOP_DET	: stop condition  interrupt
+* @arg I2C_IT_START_DET	: start condition  interrupt
+* @arg I2C_IT_GEN_CALL	: a general call address and ack interrupt
+* @retval : The new state of I2C_IT (SET or RESET).
+*/
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_GET_IT(I2C_IT));
+
+    /* Check the status of the specified I2C flag */
+    if((I2Cx->IC_RAW_INTR_STAT & I2C_IT) != (uint32_t)RESET)
+    {
+        /* I2C_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* I2C_IT is reset */
+        bitstatus = RESET;
+    }
+
+    /* Return the I2C_IT status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the I2Cx interrupt pending bits.
+* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+* @param I2C_IT: specifies the interrupt pending bit to clear.
+*   This parameter can be any combination of the following values:
+* @arg I2C_IT_RX_UNDER: Rx Buffer is empty interrupt
+* @arg I2C_IT_RX_OVER : RX  Buffer Overrun interrupt
+* @arg I2C_IT_RX_FULL : Rx buffer full interrupt
+* @arg I2C_IT_TX_OVER : TX  Buffer Overrun interrupt
+* @arg I2C_IT_TX_EMPTY	: TX_FIFO empty interrupt
+* @arg I2C_IT_RD_REQ	: I2C work as slave or master interrupt
+* @arg I2C_IT_TX_ABRT	: TX error interrupt  (Master mode)
+* @arg I2C_IT_RX_DONE	: Master not ack interrupt (slave mode)
+* @arg I2C_IT_ACTIVITY	: I2C activity interrupt
+* @arg I2C_IT_STOP_DET	: stop condition  interrupt
+* @arg I2C_IT_START_DET	: start condition  interrupt
+* @arg I2C_IT_GEN_CALL	: a general call address and ack interrupt
+* @retval : None
+*/
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+    assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+    if((I2C_IT & I2C_IT_RX_UNDER) 	== I2C_FLAG_RX_UNDER) {I2Cx->IC_CLR_RX_UNDER;}
+    if((I2C_IT & I2C_IT_RX_OVER)	== I2C_FLAG_RX_OVER)  {I2Cx->IC_CLR_RX_OVER;}
+    if((I2C_IT & I2C_IT_TX_OVER) 	== I2C_FLAG_TX_OVER)  {I2Cx->IC_CLR_TX_OVER;}
+    if((I2C_IT & I2C_IT_RD_REQ) 	== I2C_FLAG_RD_REQ)   {I2Cx->IC_CLR_RD_REQ;}
+    if((I2C_IT & I2C_IT_TX_ABRT) 	== I2C_FLAG_TX_ABRT)  {I2Cx->IC_CLR_TX_ABRT;}
+    if((I2C_IT & I2C_IT_RX_DONE) 	== I2C_FLAG_RX_DONE)  {I2Cx->IC_CLR_RX_DONE;}
+    if((I2C_IT & I2C_IT_ACTIVITY) 	== I2C_FLAG_ACTIVITY) {I2Cx->IC_CLR_ACTIVITY;}
+    if((I2C_IT & I2C_IT_STOP_DET) 	== I2C_FLAG_STOP_DET) {I2Cx->IC_CLR_STOP_DET;}
+    if((I2C_IT & I2C_IT_START_DET) 	== I2C_FLAG_START_DET) {I2Cx->IC_CLR_START_DET;}
+    if((I2C_IT & I2C_IT_GEN_CALL) 	== I2C_FLAG_GEN_CALL) {I2Cx->IC_CLR_GEN_CALL;}
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_iwdg.c

@@ -0,0 +1,194 @@
+/**
+******************************************************************************
+* @file    HAL_iwdg.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the IWDG firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_iwdg.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup IWDG
+* @brief IWDG driver modules
+* @{
+*/
+
+/** @defgroup IWDG_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Private_Defines
+* @{
+*/
+
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_Reload    ((uint16_t)0xAAAA)
+#define KR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup IWDG_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Enables or disables write access to IWDG_PR and IWDG_RLR
+*   registers.
+* @param IWDG_WriteAccess: new state of write access to IWDG_PR and
+*   IWDG_RLR registers.
+*   This parameter can be one of the following values:
+* @arg IWDG_WriteAccess_Enable: Enable write access to
+*   IWDG_PR and IWDG_RLR registers
+* @arg IWDG_WriteAccess_Disable: Disable write access to
+*   IWDG_PR and IWDG_RLR registers
+* @retval : None
+*/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+    IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+* @brief  Sets IWDG Prescaler value.
+* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+*   This parameter can be one of the following values:
+* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+* @retval : None
+*/
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+    IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+* @brief  Sets IWDG Reload value.
+* @param Reload: specifies the IWDG Reload value.
+*   This parameter must be a number between 0 and 0x0FFF.
+* @retval : None
+*/
+void IWDG_SetReload(uint16_t Reload)
+{
+    /* Check the parameters */
+    assert_param(IS_IWDG_RELOAD(Reload));
+    IWDG->RLR = Reload;
+}
+
+/**
+* @brief  Reloads IWDG counter with value defined in the reload register
+*   (write access to IWDG_PR and IWDG_RLR registers disabled).
+* @param  None
+* @retval : None
+*/
+void IWDG_ReloadCounter(void)
+{
+    IWDG->KR = KR_KEY_Reload;
+}
+
+/**
+* @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers
+*   disabled).
+* @param  None
+* @retval : None
+*/
+void IWDG_Enable(void)
+{
+    IWDG->KR = KR_KEY_Enable;
+}
+
+/**
+* @brief  Checks whether the specified IWDG flag is set or not.
+* @param IWDG_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+* @arg IWDG_FLAG_RVU: Reload Value Update on going
+* @retval : The new state of IWDG_FLAG (SET or RESET).
+*/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+    if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the flag status */
+    return bitstatus;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_misc.c

@@ -0,0 +1,217 @@
+/**
+******************************************************************************
+* @file    HAL_misc.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the miscellaneous firmware functions (add-on
+*          to CMSIS functions).
+******************************************************************************
+* @attention
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_misc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup MISC
+* @brief MISC driver modules
+* @{
+*/
+
+/** @defgroup MISC_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Private_Defines
+* @{
+*/
+
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+/**
+* @}
+*/
+
+/** @defgroup MISC_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup MISC_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Configures the priority grouping: pre-emption priority and subpriority.
+* @param  NVIC_PriorityGroup: specifies the priority grouping bits length.
+*   This parameter can be one of the following values:
+*     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+*                                4 bits for subpriority
+*     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+*                                3 bits for subpriority
+*     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+*                                2 bits for subpriority
+*     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+*                                1 bits for subpriority
+*     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+*                                0 bits for subpriority
+* @retval None
+*/
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+
+
+    /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+    SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+* @brief  Initializes the NVIC peripheral according to the specified
+*         parameters in the NVIC_InitStruct.
+* @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+*         the configuration information for the specified NVIC peripheral.
+* @retval None
+*/
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+    uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+
+
+    if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        /* Compute the Corresponding IRQ Priority --------------------------------*/
+        tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
+        tmppre = (0x4 - tmppriority);
+        tmpsub = tmpsub >> tmppriority;
+
+        tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+        tmppriority |=  NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+        tmppriority = tmppriority << 0x04;
+
+        NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+        /* Enable the Selected IRQ Channels --------------------------------------*/
+        NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+            (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+    }
+    else
+    {
+        /* Disable the Selected IRQ Channels -------------------------------------*/
+        NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+            (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+    }
+
+    tmppre = NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05];
+}
+
+/**
+* @brief  Sets the vector table location and Offset.
+* @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+*   This parameter can be one of the following values:
+*     @arg NVIC_VectTab_RAM
+*     @arg NVIC_VectTab_FLASH
+* @param  Offset: Vector Table base offset field. This value must be a multiple
+*         of 0x200.
+* @retval None
+*/
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+    SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+* @brief  Selects the condition for the system to enter low power mode.
+* @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+*   This parameter can be one of the following values:
+*     @arg NVIC_LP_SEVONPEND
+*     @arg NVIC_LP_SLEEPDEEP
+*     @arg NVIC_LP_SLEEPONEXIT
+* @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+
+
+    if (NewState != DISABLE)
+    {
+        SCB->SCR |= LowPowerMode;
+    }
+    else
+    {
+        SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+    }
+}
+
+/**
+* @brief  Configures the SysTick clock source.
+* @param  SysTick_CLKSource: specifies the SysTick clock source.
+*   This parameter can be one of the following values:
+*     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+*     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+* @retval None
+*/
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+    /* Check the parameters */
+
+    if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+    {
+        SysTick->CTRL |= SysTick_CLKSource_HCLK;
+    }
+    else
+    {
+        SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+    }
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_pwr.c

@@ -0,0 +1,346 @@
+/**
+******************************************************************************
+* @file    HAL_pwr.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the PWR firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_pwr.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup PWR
+* @brief PWR driver modules
+* @{
+*/
+
+/** @defgroup PWR_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Private_Defines
+* @{
+*/
+
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_PDDS_Set              ((uint32_t)0x00000002)
+#define CR_DS_Mask               ((uint32_t)0xFFFFFFFC)
+#define CR_CWUF_Set              ((uint32_t)0x00000004)
+#define CR_PLS_Mask              ((uint32_t)0xFFFFE1FF)
+
+/* --------- Cortex System Control register bit mask ---------------- */
+
+/* Cortex System Control register address */
+#define SCB_SysCtrl              ((uint32_t)0xE000ED10)
+
+/* SLEEPDEEP bit mask */
+#define SysCtrl_SLEEPDEEP_Set    ((uint32_t)0x00000004)
+/**
+* @}
+*/
+
+/** @defgroup PWR_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup PWR_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the PWR peripheral registers to their default
+*   reset values.
+* @param  None
+* @retval : None
+*/
+void PWR_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+* @brief  Enables or disables access to the RTC and backup registers.
+* @param NewState: new state of the access to the RTC and backup
+*   registers. This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+    if(NewState != DISABLE)
+    {
+        PWR->CR |= 0x00000100;
+    }
+    else
+    {
+        PWR->CR &= 0xfffffeff;
+    }
+
+}
+
+/**
+* @brief  Enables or disables the Power Voltage Detector(PVD).
+* @param NewState: new state of the PVD.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void PWR_PVDCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if(NewState == ENABLE)
+    {
+        PWR->CR |= 0x00000010;
+    }
+    else
+    {
+        PWR->CR &= 0xffffffef;
+    }
+
+}
+
+/**
+* @brief  Configures the voltage threshold detected by the Power Voltage
+*   Detector(PVD).
+* @param PWR_PVDLevel: specifies the PVD detection level
+*   This parameter can be one of the following values:
+* @arg PWR_PVDLevel_1V8: PVD detection level set to 2.8V
+* @arg PWR_PVDLevel_2V1: PVD detection level set to 2.1V
+* @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
+* @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
+* @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V
+* @arg PWR_PVDLevel_3V3: PVD detection level set to 3.3V
+* @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V
+* @arg PWR_PVDLevel_3V9: PVD detection level set to 3.9V
+* @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V
+* @arg PWR_PVDLevel_4V5: PVD detection level set to 4.5V
+* @arg PWR_PVDLevel_4V8: PVD detection level set to 4.8V
+* @retval : None
+*/
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+    tmpreg = PWR->CR;
+    /* Clear PLS[12:9] bits */
+    tmpreg &= CR_PLS_Mask;
+    /* Set PLS[12:9] bits according to PWR_PVDLevel value */
+    tmpreg |= PWR_PVDLevel;
+    /* Store the new value */
+    PWR->CR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the WakeUp Pin functionality.
+* @param NewState: new state of the WakeUp Pin functionality.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if(NewState != DISABLE)
+    {
+        PWR->CSR |= 0x00000100;
+    }
+    else
+    {
+        PWR->CSR &= 0xfffffeff;
+    }
+}
+
+/**
+* @brief  Enters STOP mode.
+* @param PWR_Regulator: specifies the regulator state in STOP mode.
+*   This parameter can be one of the following values:
+* @arg PWR_Regulator_ON: STOP mode with regulator ON
+* @arg PWR_Regulator_LowPower: STOP mode with
+*   regulator in low power mode
+* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or
+*   WFE instruction.
+*   This parameter can be one of the following values:
+* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+* @retval : None
+*/
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+    assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+
+    /* Select the regulator state in STOP mode ---------------------------------*/
+    tmpreg = PWR->CR;
+    /* Clear PDDS and LPDS bits */
+    tmpreg &= CR_DS_Mask;
+    /* Set LPDS bit according to PWR_Regulator value */
+    tmpreg |= PWR_Regulator;
+    /* Store the new value */
+    PWR->CR = tmpreg;
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+
+    SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
+
+    /* Select STOP mode entry --------------------------------------------------*/
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        /* Request Wait For Interrupt */
+        __WFI();
+    }
+    else
+    {
+        /* Request Wait For Event */
+        __WFE();
+    }
+}
+
+/**
+* @brief  Enters STANDBY mode.
+* @param  None
+* @retval : None
+*/
+void PWR_EnterSTANDBYMode(void)
+{
+    /* Clear Wake-up flag */
+    PWR->CR |= CR_CWUF_Set;
+    /* Select STANDBY mode */
+    PWR->CR |= CR_PDDS_Set;
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+
+    SCB->SCR |= SysCtrl_SLEEPDEEP_Set;
+    /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+    __force_stores();
+#endif
+    /* Request Wait For Interrupt */
+    __WFI();
+}
+
+/**
+* @brief  Checks whether the specified PWR flag is set or not.
+* @param PWR_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg PWR_FLAG_WU: Wake Up flag
+* @arg PWR_FLAG_SB: StandBy flag
+* @arg PWR_FLAG_PVDO: PVD Output
+* @retval : The new state of PWR_FLAG (SET or RESET).
+*/
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+
+    if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the flag status */
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the PWR's pending flags.
+* @param PWR_FLAG: specifies the flag to clear.
+*   This parameter can be one of the following values:
+* @arg PWR_FLAG_WU: Wake Up flag
+* @arg PWR_FLAG_SB: StandBy flag
+* @retval : None
+*/
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+
+    PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rcc.c

@@ -0,0 +1,1149 @@
+/**
+******************************************************************************
+* @file    HAL_rcc.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the RCC firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup RCC
+* @brief RCC driver modules
+* @{
+*/
+
+/** @defgroup RCC_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Private_Defines
+* @{
+*/
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of HSION bit */
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+
+/* Alias word address of USBPRE bit */
+#define CFGR_OFFSET               (RCC_OFFSET + 0x04)
+#define USBPRE_BitNumber          0x16
+#define CFGR_USBPRE_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET               (RCC_OFFSET + 0x20)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+
+/* --- CSR Register ---*/
+
+/* Alias word address of LSION bit */
+#define CSR_OFFSET                (RCC_OFFSET + 0x24)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+
+/* ---------------------- RCC registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
+#define CR_HSEBYP_Set             ((uint32_t)0x00040000)
+#define CR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
+#define CR_HSEON_Set              ((uint32_t)0x00010000)
+#define CR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
+
+/* CFGR register bit mask */
+#define CFGR_PLL_Mask             ((uint32_t)0xFFC0FFFF)
+#define CFGR_PLLMull_Mask         ((uint32_t)0x003C0000)
+#define CFGR_PLLSRC_Mask          ((uint32_t)0x00010000)
+#define CFGR_PLLXTPRE_Mask        ((uint32_t)0x00020000)
+#define CFGR_SWS_Mask             ((uint32_t)0x0000000C)
+#define CFGR_SW_Mask              ((uint32_t)0xFFFFFFFC)
+#define CFGR_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
+#define CFGR_HPRE_Set_Mask        ((uint32_t)0x000000F0)
+#define CFGR_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
+#define CFGR_PPRE1_Set_Mask       ((uint32_t)0x00000700)
+#define CFGR_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
+#define CFGR_PPRE2_Set_Mask       ((uint32_t)0x00003800)
+#define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
+#define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
+
+/* CSR register bit mask */
+#define CSR_RMVF_Set              ((uint32_t)0x01000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                 ((uint8_t)0x1F)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
+
+/* CFGR register byte 4 (Bits[31:24]) base address */
+#define CFGR_BYTE4_ADDRESS        ((uint32_t)0x40021007)
+
+/* BDCR register base address */
+#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
+
+#ifndef HSEStartUp_TimeOut
+/* Time out for HSE start up */
+#define HSEStartUp_TimeOut        ((uint16_t)0x0500)
+#endif
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Private_Variables
+* @{
+*/
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RCC_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Resets the RCC clock configuration to the default reset state.
+* @param  None
+* @retval : None
+*/
+void RCC_DeInit(void)
+{
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+    /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
+    RCC->CFGR &= (uint32_t)0xF8FF0000;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
+    RCC->CFGR &= (uint32_t)0xFF80FFFF;
+    /* Disable all interrupts */
+    RCC->CIR = 0x00000000;
+}
+
+/**
+* @brief  Configures the External High Speed oscillator (HSE).
+*   HSE can not be stopped if it is used directly or through the
+*   PLL as system clock.
+* @param RCC_HSE: specifies the new state of the HSE.
+*   This parameter can be one of the following values:
+* @arg RCC_HSE_OFF: HSE oscillator OFF
+* @arg RCC_HSE_ON: HSE oscillator ON
+* @arg RCC_HSE_Bypass: HSE oscillator bypassed with external
+*   clock
+* @retval : None
+*/
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_HSE));
+    /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+    /* Reset HSEON bit */
+    RCC->CR &= CR_HSEON_Reset;
+    /* Reset HSEBYP bit */
+    RCC->CR &= CR_HSEBYP_Reset;
+    /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
+    switch(RCC_HSE)
+    {
+        case RCC_HSE_ON:
+            /* Set HSEON bit */
+            RCC->CR |= CR_HSEON_Set;
+            break;
+
+        case RCC_HSE_Bypass:
+            /* Set HSEBYP and HSEON bits */
+            RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Waits for HSE start-up.
+* @param  None
+* @retval : An ErrorStatus enumuration value:
+* - SUCCESS: HSE oscillator is stable and ready to use
+* - ERROR: HSE oscillator not yet ready
+*/
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+    ErrorStatus status = ERROR;
+    FlagStatus HSEStatus = RESET;
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+        StartUpCounter++;
+    }
+    while((HSEStatus == RESET) && (StartUpCounter != HSEStartUp_TimeOut));
+    if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+    return (status);
+}
+
+/**
+* @brief  Adjusts the Internal High Speed oscillator (HSI) calibration
+*   value.
+* @param HSICalibrationValue: specifies the calibration trimming value.
+*   This parameter must be a number between 0 and 0x1F.
+* @retval : None
+*/
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+    tmpreg = RCC->CR;
+    /* Clear HSITRIM[4:0] bits */
+    tmpreg &= CR_HSITRIM_Mask;
+    /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+    tmpreg |= (uint32_t)HSICalibrationValue << 3;
+    /* Store the new value */
+    RCC->CR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the Internal High Speed oscillator (HSI).
+*   HSI can not be stopped if it is used directly or through the
+*   PLL as system clock.
+* @param NewState: new state of the HSI.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_HSICmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if(NewState == ENABLE)
+    {
+        RCC->CR |= 0x01;
+    }
+    else
+    {
+        RCC->CR &= 0xfffffffe;
+    }
+}
+/**
+* @brief  Configures the PLL clock source and DM DN factor.
+*   This function must be used only when the PLL is disabled.
+* @param RCC_PLLSource: specifies the PLL entry clock source.
+*   This parameter can be one of the following values:
+* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
+*   by 2 selected as PLL clock entry
+* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
+*   as PLL clock entry
+* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
+*   by 2 selected as PLL clock entry
+* @param RCC_PLLDN: specifies the PLL multiplication factor.
+*   This parameter can be RCC_PLLMul_x where x:[31:26]
+* @param RCC_PLLDM: specifies the PLL Divsior factor.
+*   This parameter can be RCC_Divsior_x where x:[22:20]
+* @retval : None
+*/
+void RCC_PLLDMDNConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLDN, uint32_t RCC_PLLDM)
+{
+    uint32_t tmpreg0 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+    assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+    tmpreg0 = RCC->CR;
+
+    /* Clear PLLDN, PLLDM bits */
+    /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    tmpreg0 &= 0x038fffff;
+
+    /* Set the PLL configuration bits */
+    tmpreg0 |= (RCC_PLLDN << 26) | (RCC_PLLDM << 20);
+
+    RCC->CR = tmpreg0;
+}
+
+
+/**
+* @brief  Configures the PLL clock source and multiplication factor.
+*   This function must be used only when the PLL is disabled.
+* @param RCC_PLLSource: specifies the PLL entry clock source.
+*   This parameter can be one of the following values:
+* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided
+*   by 2 selected as PLL clock entry
+* @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected
+*   as PLL clock entry
+* @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided
+*   by 2 selected as PLL clock entry
+* @param RCC_PLLMul: specifies the PLL multiplication factor.
+*   This parameter can be RCC_PLLMul_x where x:[31:26][22:20]
+* @retval : None
+*/
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+    assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
+    tmpreg = RCC->CFGR;
+    /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+    tmpreg &= CFGR_PLL_Mask;
+    /* Set the PLL configuration bits */
+    tmpreg |= RCC_PLLSource;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+
+    if(RCC_PLLMul == RCC_PLLMul_2)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000003); //Frclk*8/4
+    }
+    if(RCC_PLLMul == RCC_PLLMul_3)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000005, 0x00000001);//Frclk*6/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_4)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000007, 0x00000001);//Frclk*8/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_5)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000009, 0x00000001);//Frclk*10/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_6)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000B, 0x00000001);//Frclk*12/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_7)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000D, 0x00000001);//Frclk*14/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_8)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000000F, 0x00000001);//Frclk*16/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_9)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000011, 0x00000001);//Frclk*18/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_10)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000013, 0x00000001);//Frclk*20/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_11)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000015, 0x00000001);//Frclk*22/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_12)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000017, 0x00000001);//Frclk*24/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_13)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x00000019, 0x00000001);//Frclk*26/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_14)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001B, 0x00000001);//Frclk*28/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_15)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001D, 0x00000001);//Frclk*30/2
+    }
+    if(RCC_PLLMul == RCC_PLLMul_16)
+    {
+        RCC_PLLDMDNConfig(RCC_PLLSource, 0x0000001F, 0x00000001);//Frclk*32/2
+    }
+}
+
+
+/**
+* @brief  Enables or disables the PLL.
+*   The PLL can not be disabled if it is used as system clock.
+* @param NewState: new state of the PLL.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_PLLCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        RCC->CR |= 0x01000000;
+    }
+    else
+    {
+        RCC->CR &= 0xfeffffff;
+    }
+}
+
+/**
+* @brief  Configures the system clock (SYSCLK).
+* @param RCC_SYSCLKSource: specifies the clock source used as system
+*   clock. This parameter can be one of the following values:
+* @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
+* @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
+* @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
+* @retval : None
+*/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+    tmpreg = RCC->CFGR;
+    /* Clear SW[1:0] bits */
+    tmpreg &= CFGR_SW_Mask;
+    /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+    tmpreg |= RCC_SYSCLKSource;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+}
+
+/**
+* @brief  Returns the clock source used as system clock.
+* @param  None
+* @retval : The clock source used as system clock. The returned value can
+*   be one of the following:
+* - 0x00: HSI/6 used as system clock
+* - 0x04: HSE used as system clock
+* - 0x08: PLL used as system clock
+*/
+uint8_t RCC_GetSYSCLKSource(void)
+{
+    return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
+}
+
+/**
+* @brief  Configures the AHB clock (HCLK).
+* @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
+*                    the system clock (SYSCLK).
+*   This parameter can be one of the following values:
+* @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+* @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+* @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+* @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+* @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+* @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+* @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+* @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+* @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+* @retval : None
+*/
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+    tmpreg = RCC->CFGR;
+    /* Clear HPRE[3:0] bits */
+    tmpreg &= CFGR_HPRE_Reset_Mask;
+    /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+    tmpreg |= RCC_SYSCLK;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+}
+
+/**
+* @brief  Configures the Low Speed APB clock (PCLK1).
+* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
+*                  the AHB clock (HCLK).
+*   This parameter can be one of the following values:
+* @arg RCC_HCLK_Div1: APB1 clock = HCLK
+* @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
+* @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
+* @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
+* @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+* @retval : None
+*/
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_PCLK(RCC_HCLK));
+    tmpreg = RCC->CFGR;
+    /* Clear PPRE1[2:0] bits */
+    tmpreg &= CFGR_PPRE1_Reset_Mask;
+    /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+    tmpreg |= RCC_HCLK;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+}
+
+/**
+* @brief  Configures the High Speed APB clock (PCLK2).
+* @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
+*                  the AHB clock (HCLK).
+*   This parameter can be one of the following values:
+* @arg RCC_HCLK_Div1: APB2 clock = HCLK
+* @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
+* @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
+* @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
+* @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+* @retval : None
+*/
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_PCLK(RCC_HCLK));
+    tmpreg = RCC->CFGR;
+    /* Clear PPRE2[2:0] bits */
+    tmpreg &= CFGR_PPRE2_Reset_Mask;
+    /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+    tmpreg |= RCC_HCLK << 3;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+}
+
+/**
+* @brief  Enables or disables the specified RCC interrupts.
+* @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+*   This parameter can be any combination of the following values:
+* @arg RCC_IT_LSIRDY: LSI ready interrupt
+* @arg RCC_IT_LSERDY: LSE ready interrupt
+* @arg RCC_IT_HSIRDY: HSI ready interrupt
+* @arg RCC_IT_HSERDY: HSE ready interrupt
+* @arg RCC_IT_PLLRDY: PLL ready interrupt
+* @param NewState: new state of the specified RCC interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_IT(RCC_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
+        RCC->CIR &= ~((uint32_t)0x1f) << 8;
+        RCC->CIR |= ((uint32_t)RCC_IT) << 8;
+    }
+    else
+    {
+        /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
+        RCC->CIR &= ~((uint32_t)RCC_IT << 8);
+    }
+}
+
+/**
+* @brief  Configures the USB clock (USBCLK).
+* @param RCC_USBCLKSource: specifies the USB clock source. This clock is
+*                          derived from the PLL output.
+*   This parameter can be one of the following values:
+* @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+*                                     clock source
+* @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
+* @retval : None
+*/
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
+    RCC->CFGR &= ~(3 << 22);
+    RCC->CFGR |= RCC_USBCLKSource << 22;
+}
+
+/**
+* @brief  Configures the ADC clock (ADCCLK).
+* @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
+*                   the APB2 clock (PCLK2).
+*   This parameter can be one of the following values:
+* @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
+* @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
+* @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
+* @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
+* @retval : None
+*/
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
+    tmpreg = RCC->CFGR;
+    /* Clear ADCPRE[1:0] bits */
+    tmpreg &= CFGR_ADCPRE_Reset_Mask;
+    /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
+    tmpreg |= RCC_PCLK2;
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+}
+
+/**
+* @brief  Configures the External Low Speed oscillator (LSE).
+* @param RCC_LSE: specifies the new state of the LSE.
+*   This parameter can be one of the following values:
+* @arg RCC_LSE_OFF: LSE oscillator OFF
+* @arg RCC_LSE_ON: LSE oscillator ON
+* @arg RCC_LSE_Bypass: LSE oscillator bypassed with external
+*   clock
+* @retval : None
+*/
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_LSE));
+
+    /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+    switch(RCC_LSE)
+    {
+        case RCC_LSE_ON:
+            /* Set LSEON bit */
+            RCC->BDCR |= RCC_LSE_ON;
+            break;
+
+        case RCC_LSE_Bypass:
+            /* Set LSEBYP and LSEON bits */
+            RCC->BDCR |= RCC_LSE_Bypass | RCC_LSE_ON;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+*   LSI can not be disabled if the IWDG is running.
+* @param NewState: new state of the LSI.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_LSICmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        RCC->CSR |= 0x00000001;
+    }
+    else
+    {
+        RCC->CSR &= 0xfffffffe;
+    }
+}
+
+/**
+* @brief  Configures the RTC clock (RTCCLK).
+*   Once the RTC clock is selected it can’t be changed unless the
+*   Backup domain is reset.
+* @param RCC_RTCCLKSource: specifies the RTC clock source.
+*   This parameter can be one of the following values:
+* @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+* @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+* @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128
+*   selected as RTC clock
+* @retval : None
+*/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+    /* Select the RTC clock source */
+    RCC->BDCR |= RCC_RTCCLKSource;
+}
+
+/**
+* @brief  Enables or disables the RTC clock.
+*   This function must be used only after the RTC clock was
+*   selected using the RCC_RTCCLKConfig function.
+* @param NewState: new state of the RTC clock.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        RCC->BDCR |= 0x00008000;
+    }
+    else
+    {
+        RCC->BDCR &= 0xffff7fff;
+    }
+}
+
+/**
+* @brief  Returns the frequencies of different on chip clocks.
+* @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which
+*   will hold the clocks frequencies.
+* @retval : None
+*/
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+    uint32_t tmp = 0, pllmull1 = 0, pllmull2 = 0, pllsource = 0, presc = 0;
+    /* Get SYSCLK source -------------------------------------------------------*/
+    tmp = RCC->CFGR & CFGR_SWS_Mask;
+    switch (tmp)
+    {
+        case 0x00:  /* HSI used as system clock */
+            RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
+            break;
+        case 0x04:  /* HSE used as system clock */
+            RCC_Clocks->SYSCLK_Frequency = HSE_Value;
+            break;
+        case 0x08:  /* PLL used as system clock */
+            /* Get PLL clock source and multiplication factor ----------------------*/
+            //pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
+            //pllmull = ( pllmull >> 18) + 2;
+            pllmull1 = ((RCC->CR & 0xfc000000) >> 26) + 1;
+            pllmull2 = ((RCC->CR & 0x00700000) >> 20) + 1;
+            pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
+            if (pllsource == 0x00)
+            {
+                /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+                RCC_Clocks->SYSCLK_Frequency = 2 * (HSI_Value_Pll_ON >> 1) * pllmull1 / pllmull2;
+            }
+            else
+            {
+                /* HSE selected as PLL clock entry */
+                if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
+                {
+                    /* HSE oscillator clock divided by 2 */
+                    RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull1 / pllmull2;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull1 / pllmull2;
+                }
+            }
+            break;
+        default:
+            RCC_Clocks->SYSCLK_Frequency = HSI_Value_Pll_OFF;
+            break;
+    }
+    /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
+    /* Get HCLK prescaler */
+    tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    /* HCLK clock frequency */
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    /* Get PCLK1 prescaler */
+    tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    /* PCLK1 clock frequency */
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    /* Get PCLK2 prescaler */
+    tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    /* PCLK2 clock frequency */
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    /* Get ADCCLK prescaler */
+    tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    /* ADCCLK clock frequency */
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/**
+* @brief  Enables or disables the AHB peripheral clock.
+* @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
+*   This parameter can be any combination of the following values:
+* @arg RCC_AHBPeriph_DMA1
+* @arg RCC_AHBPeriph_DMA2
+* @arg RCC_AHBPeriph_SRAM
+* @arg RCC_AHBPeriph_FLITF
+* @arg RCC_AHBPeriph_CRC
+* @arg RCC_AHBPeriph_FSMC
+* @arg RCC_AHBPeriph_SDIO
+*   SRAM and FLITF clock can be disabled only during sleep mode.
+* @param NewState: new state of the specified peripheral clock.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        RCC->AHBENR |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBENR &= ~RCC_AHBPeriph;
+    }
+}
+
+/**
+* @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+* @param RCC_APB2Periph: specifies the APB2 peripheral to gates its
+*   clock.
+*   This parameter can be any combination of the following values:
+* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+*   RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
+*   RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
+*   RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+*   RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1,
+*   RCC_APB2Periph_ALL
+* @param NewState: new state of the specified peripheral clock.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        RCC->APB2ENR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2ENR &= ~RCC_APB2Periph;
+    }
+}
+
+/**
+* @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+* @param RCC_APB1Periph: specifies the APB1 peripheral to gates its
+*   clock.
+*   This parameter can be any combination of the following values:
+* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+*   RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+*   RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+*   RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
+*   RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+*   RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+*   RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
+* @param NewState: new state of the specified peripheral clock.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        RCC->APB1ENR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1ENR &= ~RCC_APB1Periph;
+    }
+}
+
+/**
+* @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+* @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
+*   This parameter can be any combination of the following values:
+* @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
+*   RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_ADC1,
+*   RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
+*   RCC_APB2Periph_TIM8, RCC_APB2Periph_UART1, RCC_APB2Periph_ADC3,
+*   RCC_APB2Periph_ALL
+* @param NewState: new state of the specified peripheral reset.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        RCC->APB2RSTR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2RSTR &= ~RCC_APB2Periph;
+    }
+}
+
+/**
+* @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+* @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
+*   This parameter can be any combination of the following values:
+* @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
+*   RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
+*   RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
+*   RCC_APB1Periph_UART2, RCC_APB1Periph_UART3, RCC_APB1Periph_UART4,
+*   RCC_APB1Periph_UART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
+*   RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
+*   RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_ALL
+* @param NewState: new state of the specified peripheral clock.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        RCC->APB1RSTR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1RSTR &= ~RCC_APB1Periph;
+    }
+}
+
+/**
+* @brief  Forces or releases the Backup domain reset.
+* @param NewState: new state of the Backup domain reset.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+* @brief  Enables or disables the Clock Security System.
+* @param NewState: new state of the Clock Security System..
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+* @brief  Selects the clock source to output on MCO pin.
+* @param RCC_MCO: specifies the clock source to output.
+*   This parameter can be one of the following values:
+* @arg RCC_MCO_NoClock: No clock selected
+* @arg RCC_MCO_SYSCLK: System clock selected
+* @arg RCC_MCO_HSI: HSI oscillator clock selected
+* @arg RCC_MCO_HSE: HSE oscillator clock selected
+* @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
+* @retval : None
+*/
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_MCO(RCC_MCO));
+    /* Perform Byte access to MCO[2:0] bits to select the MCO source */
+    *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/**
+* @brief  Checks whether the specified RCC flag is set or not.
+* @param RCC_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+* @arg RCC_FLAG_PLLRDY: PLL clock ready
+* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+* @arg RCC_FLAG_PINRST: Pin reset
+* @arg RCC_FLAG_PORRST: POR/PDR reset
+* @arg RCC_FLAG_SFTRST: Software reset
+* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+* @arg RCC_FLAG_LPWRRST: Low Power reset
+* @retval : The new state of RCC_FLAG (SET or RESET).
+*/
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+    uint32_t tmp = 0;
+    uint32_t statusreg = 0;
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_RCC_FLAG(RCC_FLAG));
+    /* Get the RCC register index */
+    tmp = RCC_FLAG >> 5;
+    if (tmp == 1)               /* The flag to check is in CR register */
+    {
+        statusreg = RCC->CR;
+    }
+    else if (tmp == 2)          /* The flag to check is in BDCR register */
+    {
+        statusreg = RCC->BDCR;
+    }
+    else                       /* The flag to check is in CSR register */
+    {
+        statusreg = RCC->CSR;
+    }
+    /* Get the flag position */
+    tmp = RCC_FLAG & FLAG_Mask;
+    if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the flag status */
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the RCC reset flags.
+*   The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+*   RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
+*   RCC_FLAG_LPWRRST
+* @param  None
+* @retval : None
+*/
+void RCC_ClearFlag(void)
+{
+    /* Set RMVF bit to clear the reset flags */
+    RCC->CSR |= CSR_RMVF_Set;
+}
+
+/**
+* @brief  Checks whether the specified RCC interrupt has occurred or not.
+* @param RCC_IT: specifies the RCC interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg RCC_IT_LSIRDY: LSI ready interrupt
+* @arg RCC_IT_LSERDY: LSE ready interrupt
+* @arg RCC_IT_HSIRDY: HSI ready interrupt
+* @arg RCC_IT_HSERDY: HSE ready interrupt
+* @arg RCC_IT_PLLRDY: PLL ready interrupt
+* @arg RCC_IT_CSS: Clock Security System interrupt
+* @retval : The new state of RCC_IT (SET or RESET).
+*/
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+    ITStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_RCC_GET_IT(RCC_IT));
+    /* Check the status of the specified RCC interrupt */
+    if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    /* Return the RCC_IT status */
+    return  bitstatus;
+}
+
+/**
+* @brief  Clears the RCC’s interrupt pending bits.
+* @param RCC_IT: specifies the interrupt pending bit to clear.
+*   This parameter can be any combination of the following values:
+* @arg RCC_IT_LSIRDY: LSI ready interrupt
+* @arg RCC_IT_LSERDY: LSE ready interrupt
+* @arg RCC_IT_HSIRDY: HSI ready interrupt
+* @arg RCC_IT_HSERDY: HSE ready interrupt
+* @arg RCC_IT_PLLRDY: PLL ready interrupt
+* @arg RCC_IT_CSS: Clock Security System interrupt
+* @retval : None
+*/
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+    /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+    pending bits */
+
+    RCC->CIR |= (uint32_t)RCC_IT << 16;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_rtc.c

@@ -0,0 +1,339 @@
+/**
+******************************************************************************
+* @file    HAL_rtc.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the RTC firmware functions.
+******************************************************************************
+* @attention
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+******************************************************************************
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_rtc.h"
+
+/** @addtogroup
+* @{
+*/
+
+/** @defgroup RTC
+* @brief RTC driver modules
+* @{
+*/
+
+/** @defgroup RTC_Private_TypesDefinitions
+* @{
+*/
+/**
+* @}
+*/
+
+/** @defgroup RTC_Private_Defines
+* @{
+*/
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF)  /*!< RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000)  /*!< RTC Prescaler MSB Mask */
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup RTC_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Enables or disables the specified RTC interrupts.
+* @param  RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.
+*   This parameter can be any combination of the following values:
+*     @arg RTC_IT_OW: Overflow interrupt
+*     @arg RTC_IT_ALR: Alarm interrupt
+*     @arg RTC_IT_SEC: Second interrupt
+* @param  NewState: new state of the specified RTC interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval None
+*/
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_IT(RTC_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        RTC->CRH |= RTC_IT;
+    }
+    else
+    {
+        RTC->CRH &= (uint16_t)~RTC_IT;
+    }
+}
+
+/**
+* @brief  Enters the RTC configuration mode.
+* @param  None
+* @retval None
+*/
+void RTC_EnterConfigMode(void)
+{
+    /* Set the CNF flag to enter in the Configuration Mode */
+    RTC->CRL |= RTC_CRL_CNF;
+}
+
+/**
+* @brief  Exits from the RTC configuration mode.
+* @param  None
+* @retval None
+*/
+void RTC_ExitConfigMode(void)
+{
+    /* Reset the CNF flag to exit from the Configuration Mode */
+    RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF);
+}
+
+/**
+* @brief  Gets the RTC counter value.
+* @param  None
+* @retval RTC counter value.
+*/
+uint32_t RTC_GetCounter(void)
+{
+    uint16_t tmp = 0;
+    tmp = RTC->CNTL;
+    return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;
+}
+
+/**
+* @brief  Sets the RTC counter value.
+* @param  CounterValue: RTC counter new value.
+* @retval None
+*/
+void RTC_SetCounter(uint32_t CounterValue)
+{
+    RTC_EnterConfigMode();
+    /* Set RTC COUNTER MSB word */
+    RTC->CNTH = CounterValue >> 16;
+    /* Set RTC COUNTER LSB word */
+    RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/**
+* @brief  Sets the RTC prescaler value.
+* @param  PrescalerValue: RTC prescaler new value.
+* @retval None
+*/
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_PRESCALER(PrescalerValue));
+
+    RTC_EnterConfigMode();
+    /* Set RTC PRESCALER MSB word */
+    RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+    /* Set RTC PRESCALER LSB word */
+    RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/**
+* @brief  Sets the RTC alarm value.
+* @param  AlarmValue: RTC alarm new value.
+* @retval None
+*/
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+    RTC_EnterConfigMode();
+    /* Set the ALARM MSB word */
+    RTC->ALRH = AlarmValue >> 16;
+    /* Set the ALARM LSB word */
+    RTC->ALRL = (AlarmValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/**
+* @brief  Gets the RTC divider value.
+* @param  None
+* @retval RTC Divider value.
+*/
+uint32_t RTC_GetDivider(void)
+{
+    uint32_t tmp = 0x00;
+    tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+    tmp |= RTC->DIVL;
+    return tmp;
+}
+
+/**
+* @brief  Waits until last write operation on RTC registers has finished.
+* @note   This function must be called before any write to RTC registers.
+* @param  None
+* @retval None
+*/
+void RTC_WaitForLastTask(void)
+{
+    /* Loop until RTOFF flag is set */
+    while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/**
+* @brief  Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)
+*   are synchronized with RTC APB clock.
+* @note   This function must be called before any read operation after an APB reset
+*   or an APB clock stop.
+* @param  None
+* @retval None
+*/
+void RTC_WaitForSynchro(void)
+{
+    /* Clear RSF flag */
+    RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;
+    /* Loop until RSF flag is set */
+    while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/**
+* @brief  Checks whether the specified RTC flag is set or not.
+* @param  RTC_FLAG: specifies the flag to check.
+*   This parameter can be one the following values:
+*     @arg RTC_FLAG_RTOFF: RTC Operation OFF flag
+*     @arg RTC_FLAG_RSF: Registers Synchronized flag
+*     @arg RTC_FLAG_OW: Overflow flag
+*     @arg RTC_FLAG_ALR: Alarm flag
+*     @arg RTC_FLAG_SEC: Second flag
+* @retval The new state of RTC_FLAG (SET or RESET).
+*/
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+
+    if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the RTC's pending flags.
+* @param  RTC_FLAG: specifies the flag to clear.
+*   This parameter can be any combination of the following values:
+*     @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after
+*                        an APB reset or an APB Clock stop.
+*     @arg RTC_FLAG_OW: Overflow flag
+*     @arg RTC_FLAG_ALR: Alarm flag
+*     @arg RTC_FLAG_SEC: Second flag
+* @retval None
+*/
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+    /* Clear the corresponding RTC flag */
+    RTC->CRL &= (uint16_t)~RTC_FLAG;
+}
+
+/**
+* @brief  Checks whether the specified RTC interrupt has occurred or not.
+* @param  RTC_IT: specifies the RTC interrupts sources to check.
+*   This parameter can be one of the following values:
+*     @arg RTC_IT_OW: Overflow interrupt
+*     @arg RTC_IT_ALR: Alarm interrupt
+*     @arg RTC_IT_SEC: Second interrupt
+* @retval The new state of the RTC_IT (SET or RESET).
+*/
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+    ITStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_RTC_GET_IT(RTC_IT));
+
+    bitstatus = (ITStatus)(RTC->CRL & RTC_IT);
+    if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the RTC's interrupt pending bits.
+* @param  RTC_IT: specifies the interrupt pending bit to clear.
+*   This parameter can be any combination of the following values:
+*     @arg RTC_IT_OW: Overflow interrupt
+*     @arg RTC_IT_ALR: Alarm interrupt
+*     @arg RTC_IT_SEC: Second interrupt
+* @retval None
+*/
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_RTC_IT(RTC_IT));
+
+    /* Clear the corresponding RTC pending bit */
+    RTC->CRL &= (uint16_t)~RTC_IT;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_spi.c

@@ -0,0 +1,693 @@
+/**
+******************************************************************************
+* @file    HAL_spi.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the SPI firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_spi.h"
+
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup SPI
+* @brief SPI driver modules
+* @{
+*/
+
+/** @defgroup SPI_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+
+/** @defgroup SPI_Private_Defines
+* @{
+*/
+
+
+
+/* SPI SPIENE mask */
+#define GCTL_SPIEN_Set          ((uint16_t)0x0001)
+#define GCTL_SPIEN_Reset        ((uint16_t)0xFFFE)
+/* SPI registers Masks */
+#define GCTL_CLEAR_Mask       ((uint16_t)0xF000)
+#define CCTL_CLEAR_Mask       ((uint16_t)0xFFC0)
+#define SPBRG_CLEAR_Mask      ((uint16_t)0x0000)
+#define SPI_DataSize_Mask     ((uint16_t)0xFCFF)
+/**
+* @}
+*/
+
+/** @defgroup SPI_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup SPI_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the SPIx peripheral registers to their default
+*   reset values .
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @retval : None
+*/
+void SPI_DeInit(SPI_TypeDef* SPIx)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    switch (*(uint32_t*)&SPIx)
+    {
+        case SPI1_BASE:
+            /* Enable SPI1 reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+            /* Release SPI1 from reset state */
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+            break;
+        case SPI2_BASE:
+            /* Enable SPI2 reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+            /* Release SPI1 from reset state */
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+            break;
+
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the SPIx peripheral according to the specified
+*   parameters in the SPI_InitStruct.
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+*   contains the configuration information for the specified
+*   SPI peripheral.
+* @retval : None
+*/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    /* check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Check the SPI parameters */
+    assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+    assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+    assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+    assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+    assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+    assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+    assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+    assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+    assert_param(IS_SPI_DATAWIDRH(SPI_InitStruct->SPI_DataWidth));
+    assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+    /*---------------------------- SPIx GCTL Configuration ------------------------*/
+    /* Get the SPIx GCTL value */
+    tmpreg = SPIx->GCTL;
+    /* Clear csn_sel, dmamode, txtlf, rxtlf,data_sel, rxen, txen, mm, int_en, spien bits */
+    tmpreg &= GCTL_CLEAR_Mask;
+    /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+    master/salve mode, CPOL and CPHA */
+    /* Set dat_sel bits according to SPI_DataSize value */
+    /* Set csn and csn_sel bits according to SPI_NSS value */
+    /* Set mm bit according to SPI_Mode value */
+    tmpreg |= (uint32_t)((uint32_t) SPI_InitStruct->SPI_DataSize  |  SPI_InitStruct->SPI_NSS |
+                         SPI_InitStruct->SPI_Mode  );
+    /* Write to SPIx GCTL */
+    SPIx->GCTL = tmpreg;
+    /*---------------------------- SPIx CCTL Configuration ------------------------*/
+    tmpreg = SPIx->CCTL;
+    /* Clear spilen, lsbfe, CPOL, CPHA bits */
+    tmpreg &= CCTL_CLEAR_Mask;
+    /* Set Spilen bit according to SPI_DataWidth value */
+    /* Set LSBFirst bit according to SPI_FirstBit value */
+    /* Set CPOL bit according to SPI_CPOL value */
+    /* Set CPHA bit according to SPI_CPHA value */
+    tmpreg |= (uint16_t)( SPI_InitStruct->SPI_FirstBit   |  SPI_InitStruct->SPI_CPOL |
+                          SPI_InitStruct->SPI_CPHA) ;
+
+    /* Write to SPIx CCTL */
+    SPIx->CCTL = tmpreg | 0x18;
+    /*---------------------------- SPIx SPBRG Configuration ------------------------*/
+    tmpreg = SPIx->SPBRG;
+    /* Clear spbrg bits */
+    tmpreg &= (uint16_t)SPBRG_CLEAR_Mask;
+    /* Set BR bits according to SPI_BaudRatePrescaler value */
+    tmpreg |= (uint16_t) SPI_InitStruct->SPI_BaudRatePrescaler;
+    /* Write to SPIx SPBRG */
+    SPIx->SPBRG = tmpreg;
+
+    if((SPI_InitStruct->SPI_DataWidth) != SPI_DataWidth_8b)
+    {
+        SPIx->CCTL |= 1 << 2; //lsbfe
+        SPIx->CCTL |= 1 << 3; //spilen
+    }
+    SPIx->EXTCTL = SPI_InitStruct->SPI_DataWidth;
+}
+
+/**
+* @brief  Fills each SPI_InitStruct member with its default value.
+* @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+    /*--------------- Reset SPI init structure parameters values -----------------*/
+
+    /* initialize the SPI_Mode member */
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+    /* initialize the SPI_DataSize member */
+    SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+    /* Initialize the SPILEN member */
+    SPI_InitStruct->SPI_DataWidth = SPI_DataWidth_8b;
+    /* Initialize the SPI_CPOL member */
+    SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+    /* Initialize the SPI_CPHA member */
+    SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+    /* Initialize the SPI_NSS member */
+    SPI_InitStruct->SPI_NSS = SPI_NSS_Soft;
+    /* Initialize the SPI_BaudRatePrescaler member */
+    SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    /* Initialize the SPI_FirstBit member */
+    SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+
+}
+
+
+/**
+* @brief  Enables or disables the specified SPI peripheral.
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @param NewState: new state of the SPIx peripheral.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI peripheral */
+        SPIx->GCTL |= GCTL_SPIEN_Set;
+    }
+    else
+    {
+        /* Disable the selected SPI peripheral */
+        SPIx->GCTL &= GCTL_SPIEN_Reset;
+    }
+}
+
+
+/**
+* @brief  Enables or disables the specified SPIinterrupts.
+* @param SPIx: where x can be :
+*   0, 1  in SPI mode
+* @param SPI_IT: specifies the SPI interrupt source to be
+*   enabled or disabled.
+*   This parameter can be one of the following values:
+* @arg SPI_IT_TX: Tx buffer empty interrupt mask
+* @arg SPI_IT_RX: Rx buffer  interrupt mask
+* @arg SPI_IT_UNDERRUN: under Error interrupt mask in slave mode
+* @arg SPI_IT_RXOVER: RX OVER Error interrupt mask
+* @arg SPI_IT_RXMATCH: spectials rx data numbers  interrupt mask
+* @arg SPI_IT_RXFULL: Rx buffer full interrupt mask
+* @arg SPI_IT_TXEPT: Tx buffer empty interrupt mask
+* @param NewState: new state of the specified SPI interrupt.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_CONFIG_IT(SPI_IT));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI Global interrupt */
+        SPIx->GCTL |= SPI_INT_EN;
+        /* Enable the selected SPI interrupt */
+        SPIx->INTEN |= SPI_IT;
+    }
+    else
+    {
+        /* Disable the selected SPI interrupt */
+        SPIx->INTEN &= (uint16_t)~SPI_IT;
+        /* Disable the selected SPI Global interrupt */
+        SPIx->GCTL &= (uint16_t)~SPI_INT_EN;
+    }
+
+}
+
+/**
+* @brief  Enables or disables the SPIx DMA interface.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @param SPI_DMAReq: specifies the SPI DMA transfer request
+*   to be enabled or disabled.
+*   This parameter can be any combination of the following values:
+* @arg SPI_DMAReq_EN: DMA transfer request enable
+* @param NewState: new state of the selected SPI DMA transfer
+*   request.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_DMAREQ(SPI_DMAReq));
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI DMA requests */
+        SPIx->GCTL |= SPI_DMAReq;
+    }
+    else
+    {
+        /* Disable the selected SPI DMA requests */
+        SPIx->GCTL &= (uint32_t)~SPI_DMAReq;
+    }
+}
+
+/**
+* @brief  configure tn Fifo trigger level bit.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @param SPI_FifoTriggerValue: specifies the Fifo trigger level
+*   This parameter can be any combination of the following values:
+* SPI_TXTLF : SPI TX FIFO Trigger value set
+* SPI_RXTLF : SPI RX FIFO Trigger value set
+* @param NewState: new state of the selected SPI DMA transfer
+*   request.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void SPI_FifoTrigger(SPI_TypeDef* SPIx, uint16_t SPI_FifoTriggerValue, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_SPI_FIFOTRIGGER(SPI_FifoTriggerValue));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected SPI DMA requests */
+        SPIx->GCTL |= SPI_FifoTriggerValue;
+    }
+    else
+    {
+        /* Disable the selected SPI DMA requests */
+        SPIx->GCTL &= (uint32_t)~SPI_FifoTriggerValue;
+    }
+}
+
+/**
+* @brief  Transmits a Data through the SPIx peripheral.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @param Data : Data to be transmitted..
+* @retval : None
+*/
+void SPI_SendData(SPI_TypeDef* SPIx, uint32_t Data)
+{
+    uint8_t temp;
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+    /* Write in the TXREG register the data to be sent */
+    temp = SPIx->EXTCTL;
+    SPIx->TXREG = Data;
+    if(temp > 0x8 || temp == 0) SPIx->TXREG  = Data >> 8;
+    if(temp > 0x10 || temp == 0) SPIx->TXREG = Data >> 16;
+    if(temp > 0x18 || temp == 0) SPIx->TXREG = Data >> 24;
+}
+
+
+/**
+* @brief  Returns the most recent received data by the SPIx peripheral.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @retval : The value of the received data.
+*/
+uint32_t SPI_ReceiveData(SPI_TypeDef* SPIx)
+{
+
+    uint32_t temp = 0;
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    temp = temp;
+    temp |= (uint32_t)SPIx->RXREG;
+    if(SPIx->EXTCTL > 8 || SPIx->EXTCTL == 0)    temp |= (uint32_t) (SPIx->RXREG) << 8;
+    if(SPIx->EXTCTL > 16 || SPIx->EXTCTL == 0)  	temp |= (uint32_t)( SPIx->RXREG) << 16;
+    if(SPIx->EXTCTL > 24 || SPIx->EXTCTL == 0)	temp |= (uint32_t)( SPIx->RXREG) << 24;
+
+    return temp;
+}
+
+/**
+* @brief Slave chip csn single by selected
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @param SPI_CSInternalSelected: specifies the SPI CS internal selected.
+*   This parameter can be one of the following values:
+* @arg SPI_CS_BIT0: cs bit 0 selected
+* @arg SPI_CS_BIT1: cs bit 1 selected
+* @arg SPI_CS_BIT2: cs bit 2 selected
+* @arg SPI_CS_BIT3: cs bit 3 selected
+* @arg SPI_CS_BIT4: cs bit 4 selected
+* @arg SPI_CS_BIT5: cs bit 5 selected
+* @arg SPI_CS_BIT6: cs bit 6 selected
+* @arg SPI_CS_BIT7: cs bit 7 selected
+* @param NewState: new state of the selected SPI CS pin
+*   request.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void SPI_CSInternalSelected(SPI_TypeDef* SPIx, uint16_t SPI_CSInternalSelected, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CS(SPI_CSInternalSelected));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+
+    if (NewState != DISABLE)
+    {
+        /* selected cs pin according SCSR Value */
+        SPIx->SCSR &= SPI_CSInternalSelected;
+    }
+    else
+    {
+        /* release cs pin according SCSR Value*/
+        SPIx->SCSR |= ~SPI_CSInternalSelected;
+    }
+}
+
+
+/**
+* @brief  Configures internally by software the NSS pin for the selected
+*   SPI.
+* @param SPIx: where x can be 1, 2 to select the SPI peripheral.
+* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+*   This parameter can be one of the following values:
+* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+* @retval : None
+*/
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+    if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+    {
+        /* Set NSS pin internally by software */
+        SPIx->GCTL |= SPI_NSSInternalSoft_Set;
+    }
+    else
+    {
+        /* Reset NSS pin internally by software */
+        SPIx->GCTL &= SPI_NSSInternalSoft_Reset;
+    }
+}
+
+
+
+/**
+* @brief  Configures the data size for the selected SPI.
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @param SPI_DataSize: specifies the SPI data size.
+*   This parameter can be one of the following values:
+* @arg SPI_DataSize_32b: Set data frame format to 32bit
+* @arg SPI_DataSize_16b: Set data frame format to 16bit
+* @arg SPI_DataSize_8b: Set data frame format to 8bit
+* @retval : None
+*/
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+    /* Clear data_sel bit */
+    SPIx->GCTL &= SPI_DataSize_Mask;
+    /* Set new data_sel bit value */
+    SPIx->GCTL |= SPI_DataSize;
+}
+
+
+
+/**
+* @brief  Selects the data transfer direction in bi-directional mode
+*   for the specified SPI.
+* @param SPIx: where x can be 0, 1 to select the SPI peripheral.
+* @param SPI_Direction: specifies the data transfer direction in
+*   bi-directional mode.
+*   This parameter can be one of the following values:
+* @arg SPI_Direction_Tx: Selects Tx transmission direction
+* @arg SPI_Direction_Rx: Selects Rx receive direction
+@arg SPI_Disable_Tx: Selects Rx receive direction
+@arg SPI_Disable_Rx: Selects Rx receive direction
+* @retval : None
+*/
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_DIRECTION(SPI_Direction));
+
+    /* Set the Tx  only mode */
+    if(SPI_Direction == SPI_Direction_Tx)
+    {
+        SPIx->GCTL |= SPI_Direction_Tx;
+    }
+    /* Set the  Rx  only mode */
+    if(SPI_Direction == SPI_Direction_Rx)
+    {
+        SPIx->GCTL |= SPI_Direction_Rx;
+    }
+    /* Disable the  Tx  only mode */
+    if(SPI_Direction == SPI_Disable_Tx)
+    {
+        SPIx->GCTL &= SPI_Disable_Tx;
+    }
+    /* Disable the  Rx  only mode */
+    if(SPI_Direction == SPI_Disable_Rx)
+    {
+        SPIx->GCTL &= SPI_Disable_Rx;
+    }
+}
+
+/**
+* @brief  Checks whether the specified SPI flag is set or not.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @param SPI_FLAG: specifies the SPI flag to check.
+*   This parameter can be one of the following values:
+* @arg SPI_FLAG_RXAVL: Rx buffer has bytes flag
+* @arg SPI_FLAG_TXEPT:  Tx  buffer  and tx shifter empty flag
+* @retval : The new state of SPI_FLAG (SET or RESET).
+*/
+FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_GET_FLAG(SPI_FLAG));
+    if(SPIx->EXTCTL == 8)
+    {
+        /* Check the status of the specified SPI flag */
+        if ((SPIx->CSTAT & SPI_FLAG) != (uint16_t)RESET)
+        {
+            /* SPI_FLAG is set */
+            bitstatus = SET;
+        }
+        else
+        {
+            /* SPI_FLAG is reset */
+            bitstatus = RESET;
+        }
+        /* Return the SPI_FLAG status */
+        return  bitstatus;
+    }
+    else
+    {
+        uint8_t number;
+        if(SPIx->EXTCTL > 0 && SPIx->EXTCTL <= 8)
+            number = 1;
+        else if(SPIx->EXTCTL <= 16)
+            number = 2;
+        else if(SPIx->EXTCTL <= 24)
+            number = 3;
+        else if(SPIx->EXTCTL <= 31 || SPIx->EXTCTL == 0)
+            number = 4;
+        if(((SPIx->CSTAT & 0xf00) >> 8) >= number)
+        {
+            return SET;
+        }
+        else
+        {
+            return RESET;
+        }
+    }
+}
+
+/**
+* @brief  Checks whether the specified SPI interrupt has occurred or not.
+* @param SPIx: where x can be :
+*  0, 1 in SPI mode
+* @param SPI_IT: specifies the SPI interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg SPI_IT_TX: Tx buffer empty interrupt
+* @arg SPI_IT_RX: Rx buffer  interrupt
+* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
+* @arg SPI_IT_RXOVER: RX OVER Error interrupt
+* @arg SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+* @arg SPI_IT_RXFULL: Rx buffer full interrupt
+* @arg SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+* @retval : The new state of SPI_IT (SET or RESET).
+*/
+ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_GET_IT(SPI_IT));
+    /* Check the status of the specified SPI interrupt */
+    if ((SPIx->INTSTAT & SPI_IT) != (uint16_t)RESET)
+    {
+        /* SPI_IT is set */
+        bitstatus = SET;
+    }
+    else
+    {
+        /* SPI_IT is reset */
+        bitstatus = RESET;
+    }
+    /* Return the SPI_IT status */
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the SPIx  Error  interrupt pending bit.
+* @param SPIx: where x can be :
+*   0, 1 in SPI mode
+* @param SPI_IT: specifies the SPI interrupt pending bit to clear.
+* @arg SPI_IT_TX: Tx buffer empty interrupt
+* @arg SPI_IT_RX: Rx buffer  interrupt
+* @arg SPI_IT_UNDERRUN: under Error interrupt in slave mode
+* @arg SPI_IT_RXOVER: RX OVER Error interrupt
+* @arg SPI_IT_RXMATCH: spectials rx data numbers  interrupt
+* @arg SPI_IT_RXFULL: Rx buffer full interrupt
+* @arg SPI_IT_TXEPT: Tx buffer  and tx shifter empty interrupt
+*   This function clears only ERR intetrrupt pending bit.
+* @retval : None
+*/
+void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT)
+{
+
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_CLEAR_IT(SPI_IT));
+
+    /* Clear the selected SPI IT INTERRUPT */
+    SPIx->INTCLR |= (uint16_t)SPI_IT;
+}
+
+
+/**
+* @brief  SPI Hole a count Received bytes in next receive process.
+* @param SPIx: where x can be 0, 1 in SPI mode
+* @param Number: specifies the SPI receive Number.
+*   This parament can be 1-65535.
+*   This function can use only in SPI master single receive mode.
+* @retval : None
+*/
+void SPI_RxBytes(SPI_TypeDef* SPIx, uint16_t Number)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    /*set the received bytes in next receive process */
+    SPIx->RXDNR = Number;
+}
+
+/**
+* @brief  slave mode tx data transmit phase adjust set.
+* @param SPIx: where x can be 0, 1 in SPI mode
+* @param AdjustValue: specifies the SPI receive Number.
+*   This parament can be :
+*   SPI_SlaveAdjust_FAST:  fast speed use
+*   SPI_SlaveAdjust_LOW:   low speed use
+*   This function can use only in SPI master single receive mode.
+* @retval : None
+*/
+void SPI_SlaveAdjust(SPI_TypeDef* SPIx, uint16_t AdjustValue)
+{
+    /* Check the parameters */
+    assert_param(IS_SPI_ALL_PERIPH(SPIx));
+    assert_param(IS_SPI_SlaveAdjust(AdjustValue));
+    /*set the AdjustValue according to txedge bit of CCTL register*/
+    SPIx->CCTL |= AdjustValue;
+}
+
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_tim.c

@@ -0,0 +1,2838 @@
+/**
+******************************************************************************
+* @file    HAL_tim.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the TIM firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_tim.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup TIM
+* @brief TIM driver modules
+* @{
+*/
+
+/** @defgroup TIM_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Defines
+* @{
+*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define CR1_CEN_Set                 ((uint16_t)0x0001)
+#define CR1_CEN_Reset               ((uint16_t)0x03FE)
+#define CR1_UDIS_Set                ((uint16_t)0x0002)
+#define CR1_UDIS_Reset              ((uint16_t)0x03FD)
+#define CR1_URS_Set                 ((uint16_t)0x0004)
+#define CR1_URS_Reset               ((uint16_t)0x03FB)
+#define CR1_OPM_Reset               ((uint16_t)0x03F7)
+#define CR1_CounterMode_Mask        ((uint16_t)0x038F)
+#define CR1_ARPE_Set                ((uint16_t)0x0080)
+#define CR1_ARPE_Reset              ((uint16_t)0x037F)
+#define CR1_CKD_Mask                ((uint16_t)0x00FF)
+#define CR2_CCPC_Set                ((uint16_t)0x0001)
+#define CR2_CCPC_Reset              ((uint16_t)0xFFFE)
+#define CR2_CCUS_Set                ((uint16_t)0x0004)
+#define CR2_CCUS_Reset              ((uint16_t)0xFFFB)
+#define CR2_CCDS_Set                ((uint16_t)0x0008)
+#define CR2_CCDS_Reset              ((uint16_t)0xFFF7)
+#define CR2_MMS_Mask                ((uint16_t)0xFF8F)
+#define CR2_TI1S_Set                ((uint16_t)0x0080)
+#define CR2_TI1S_Reset              ((uint16_t)0xFF7F)
+#define CR2_OIS1_Reset              ((uint16_t)0x7EFF)
+#define CR2_OIS1N_Reset             ((uint16_t)0x7DFF)
+#define CR2_OIS2_Reset              ((uint16_t)0x7BFF)
+#define CR2_OIS2N_Reset             ((uint16_t)0x77FF)
+#define CR2_OIS3_Reset              ((uint16_t)0x6FFF)
+#define CR2_OIS3N_Reset             ((uint16_t)0x5FFF)
+#define CR2_OIS4_Reset              ((uint16_t)0x3FFF)
+#define SMCR_SMS_Mask               ((uint16_t)0xFFF8)
+#define SMCR_ETR_Mask               ((uint16_t)0x00FF)
+#define SMCR_TS_Mask                ((uint16_t)0xFF8F)
+#define SMCR_MSM_Reset              ((uint16_t)0xFF7F)
+#define SMCR_ECE_Set                ((uint16_t)0x4000)
+#define CCMR_CC13S_Mask             ((uint16_t)0xFFFC)
+#define CCMR_CC24S_Mask             ((uint16_t)0xFCFF)
+#define CCMR_TI13Direct_Set         ((uint16_t)0x0001)
+#define CCMR_TI24Direct_Set         ((uint16_t)0x0100)
+#define CCMR_OC13FE_Reset           ((uint16_t)0xFFFB)
+#define CCMR_OC24FE_Reset           ((uint16_t)0xFBFF)
+#define CCMR_OC13PE_Reset           ((uint16_t)0xFFF7)
+#define CCMR_OC24PE_Reset           ((uint16_t)0xF7FF)
+#define CCMR_OC13M_Mask             ((uint16_t)0xFF8F)
+#define CCMR_OC24M_Mask             ((uint16_t)0x8FFF)
+#define CCMR_OC13CE_Reset           ((uint16_t)0xFF7F)
+#define CCMR_OC24CE_Reset           ((uint16_t)0x7FFF)
+#define CCMR_IC13PSC_Mask           ((uint16_t)0xFFF3)
+#define CCMR_IC24PSC_Mask           ((uint16_t)0xF3FF)
+#define CCMR_IC13F_Mask             ((uint16_t)0xFF0F)
+#define CCMR_IC24F_Mask             ((uint16_t)0x0FFF)
+#define CCMR_Offset                 ((uint16_t)0x0018)
+#define CCER_CCE_Set                ((uint16_t)0x0001)
+#define	CCER_CCNE_Set               ((uint16_t)0x0004)
+#define CCER_CC1P_Reset             ((uint16_t)0xFFFD)
+#define CCER_CC2P_Reset             ((uint16_t)0xFFDF)
+#define CCER_CC3P_Reset             ((uint16_t)0xFDFF)
+#define CCER_CC4P_Reset             ((uint16_t)0xDFFF)
+#define CCER_CC1NP_Reset            ((uint16_t)0xFFF7)
+#define CCER_CC2NP_Reset            ((uint16_t)0xFF7F)
+#define CCER_CC3NP_Reset            ((uint16_t)0xF7FF)
+#define CCER_CC1E_Set               ((uint16_t)0x0001)
+#define CCER_CC1E_Reset             ((uint16_t)0xFFFE)
+#define CCER_CC1NE_Reset            ((uint16_t)0xFFFB)
+#define CCER_CC2E_Set               ((uint16_t)0x0010)
+#define CCER_CC2E_Reset             ((uint16_t)0xFFEF)
+#define CCER_CC2NE_Reset            ((uint16_t)0xFFBF)
+#define CCER_CC3E_Set               ((uint16_t)0x0100)
+#define CCER_CC3E_Reset             ((uint16_t)0xFEFF)
+#define CCER_CC3NE_Reset            ((uint16_t)0xFBFF)
+#define CCER_CC4E_Set               ((uint16_t)0x1000)
+#define CCER_CC4E_Reset             ((uint16_t)0xEFFF)
+#define BDTR_MOE_Set                ((uint16_t)0x8000)
+#define BDTR_MOE_Reset              ((uint16_t)0x7FFF)
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_FunctionPrototypes
+* @{
+*/
+
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup TIM_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the TIMx peripheral registers to their default
+*   reset values.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @retval : None
+*/
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+    switch (*(uint32_t*)&TIMx)
+    {
+        case TIM1_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+            break;
+
+        case TIM2_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+            break;
+
+        case TIM3_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+            break;
+
+        case TIM4_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+            break;
+
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the TIMx Time Base Unit peripheral according to
+*   the specified parameters in the TIM_TimeBaseInitStruct.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
+*   structure that contains the configuration information for
+*   the specified TIM peripheral.
+* @retval : None
+*/
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+    assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+    /* Select the Counter Mode and set the clock division */
+    TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask;
+    TIMx->CR1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision |
+                 TIM_TimeBaseInitStruct->TIM_CounterMode;
+
+    /* Set the Autoreload value */
+    TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+
+    /* Set the Prescaler value */
+    TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+    if(*(uint32_t*)&TIMx == TIM1_BASE)
+    {
+        /* Set the Repetition Counter value */
+        TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+    }
+
+    /* Generate an update event to reload the Prescaler value immediatly */
+    TIMx->EGR = TIM_PSCReloadMode_Immediate;
+}
+
+/**
+* @brief  Initializes the TIMx Channel1 according to the specified
+*   parameters in the TIM_OCInitStruct.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+    assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+    /* Disable the Channel 1: Reset the CC1E Bit */
+    TIMx->CCER &= CCER_CC1E_Reset;
+
+    /* Get the TIMx CCER register value */
+    tmpccer = TIMx->CCER;
+    /* Get the TIMx CR2 register value */
+    tmpcr2 =  TIMx->CR2;
+
+    /* Get the TIMx CCMR1 register value */
+    tmpccmrx = TIMx->CCMR1;
+
+    /* Reset the Output Compare Mode Bits */
+    tmpccmrx &= CCMR_OC13M_Mask;
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+    /* Reset the Output Polarity level */
+    tmpccer &= CCER_CC1P_Reset;
+    /* Set the Output Compare Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+
+    /* Set the Output State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+
+    if(*(uint32_t*)&TIMx == TIM1_BASE)
+    {
+        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= CCER_CC1NP_Reset;
+        /* Set the Output N Polarity */
+        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+        /* Reset the Output N State */
+        tmpccer &= CCER_CC1NE_Reset;
+
+        /* Set the Output N State */
+        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+        /* Reset the Ouput Compare and Output Compare N IDLE State */
+        tmpcr2 &= CR2_OIS1_Reset;
+        tmpcr2 &= CR2_OIS1N_Reset;
+        /* Set the Output Idle state */
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+        /* Set the Output N Idle state */
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+    }
+    /* Write to TIMx CR2 */
+    TIMx->CR2 = tmpcr2;
+
+    /* Write to TIMx CCMR1 */
+    TIMx->CCMR1 = tmpccmrx;
+
+    /* Write to TIMx CCER */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Initializes the TIMx Channel2 according to the specified
+*   parameters in the TIM_OCInitStruct.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+    assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCER &= CCER_CC2E_Reset;
+
+    /* Get the TIMx CCER register value */
+    tmpccer = TIMx->CCER;
+    /* Get the TIMx CR2 register value */
+    tmpcr2 =  TIMx->CR2;
+
+    /* Get the TIMx CCMR1 register value */
+    tmpccmrx = TIMx->CCMR1;
+
+    /* Reset the Output Compare Mode Bits */
+    tmpccmrx &= CCMR_OC24M_Mask;
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= CCER_CC2P_Reset;
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+
+    /* Set the Output State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+
+    if(*(uint32_t*)&TIMx == TIM1_BASE)
+    {
+        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= CCER_CC2NP_Reset;
+        /* Set the Output N Polarity */
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+        /* Reset the Output N State */
+        tmpccer &= CCER_CC2NE_Reset;
+
+        /* Set the Output N State */
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+        /* Reset the Ouput Compare and Output Compare N IDLE State */
+        tmpcr2 &= CR2_OIS2_Reset;
+        tmpcr2 &= CR2_OIS2N_Reset;
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+        /* Set the Output N Idle state */
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+    }
+    /* Write to TIMx CR2 */
+    TIMx->CR2 = tmpcr2;
+
+    /* Write to TIMx CCMR1 */
+    TIMx->CCMR1 = tmpccmrx;
+
+    /* Write to TIMx CCER */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Initializes the TIMx Channel3 according to the specified
+*   parameters in the TIM_OCInitStruct.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+    assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCER &= CCER_CC3E_Reset;
+
+    /* Get the TIMx CCER register value */
+    tmpccer = TIMx->CCER;
+    /* Get the TIMx CR2 register value */
+    tmpcr2 =  TIMx->CR2;
+
+    /* Get the TIMx CCMR2 register value */
+    tmpccmrx = TIMx->CCMR2;
+
+    /* Reset the Output Compare Mode Bits */
+    tmpccmrx &= CCMR_OC13M_Mask;
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+
+    /* Reset the Output Polarity level */
+    tmpccer &= CCER_CC3P_Reset;
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+
+    /* Set the Output State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+
+    if(*(uint32_t*)&TIMx == TIM1_BASE)
+    {
+        assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+        assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+        assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+
+        /* Reset the Output N Polarity level */
+        tmpccer &= CCER_CC3NP_Reset;
+        /* Set the Output N Polarity */
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+        /* Reset the Output N State */
+        tmpccer &= CCER_CC3NE_Reset;
+
+        /* Set the Output N State */
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+        /* Reset the Ouput Compare and Output Compare N IDLE State */
+        tmpcr2 &= CR2_OIS3_Reset;
+        tmpcr2 &= CR2_OIS3N_Reset;
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+        /* Set the Output N Idle state */
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+    }
+    /* Write to TIMx CR2 */
+    TIMx->CR2 = tmpcr2;
+
+    /* Write to TIMx CCMR2 */
+    TIMx->CCMR2 = tmpccmrx;
+
+    /* Write to TIMx CCER */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Initializes the TIMx Channel4 according to the specified
+*   parameters in the TIM_OCInitStruct.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+    assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
+    /* Disable the Channel 2: Reset the CC4E Bit */
+    TIMx->CCER &= CCER_CC4E_Reset;
+
+    /* Get the TIMx CCER register value */
+    tmpccer = TIMx->CCER;
+    /* Get the TIMx CR2 register value */
+    tmpcr2 =  TIMx->CR2;
+
+    /* Get the TIMx CCMR2 register value */
+    tmpccmrx = TIMx->CCMR2;
+
+    /* Reset the Output Compare Mode Bits */
+    tmpccmrx &= CCMR_OC24M_Mask;
+
+    /* Select the Output Compare Mode */
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+
+    /* Reset the Output Polarity level */
+    tmpccer &= CCER_CC4P_Reset;
+    /* Set the Output Compare Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+
+    /* Set the Output State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+    /* Set the Capture Compare Register value */
+    TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+
+    if(*(uint32_t*)&TIMx == TIM1_BASE)
+    {
+        assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+        /* Reset the Ouput Compare IDLE State */
+        tmpcr2 &= CR2_OIS4_Reset;
+        /* Set the Output Idle state */
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+    }
+    /* Write to TIMx CR2 */
+    TIMx->CR2 = tmpcr2;
+
+    /* Write to TIMx CCMR2 */
+    TIMx->CCMR2 = tmpccmrx;
+
+    /* Write to TIMx CCER */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Initializes the TIM peripheral according to the specified
+*   parameters in the TIM_ICInitStruct.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
+    assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+    assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+    assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+    assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+
+    if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        /* TI1 Configuration */
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+    {
+        /* TI2 Configuration */
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+    {
+        /* TI3 Configuration */
+        TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        /* TI4 Configuration */
+        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/**
+* @brief  Configures the TIM peripheral according to the specified
+*   parameters in the TIM_ICInitStruct to measure an external PWM
+*   signal.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
+*   that contains the configuration information for the specified
+*   TIM peripheral.
+* @retval : None
+*/
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+    uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+    uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Select the Opposite Input Polarity */
+    if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+    {
+        icoppositepolarity = TIM_ICPolarity_Falling;
+    }
+    else
+    {
+        icoppositepolarity = TIM_ICPolarity_Rising;
+    }
+    /* Select the Opposite Input */
+    if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+    {
+        icoppositeselection = TIM_ICSelection_IndirectTI;
+    }
+    else
+    {
+        icoppositeselection = TIM_ICSelection_DirectTI;
+    }
+    if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        /* TI1 Configuration */
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        /* TI2 Configuration */
+        TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        /* TI2 Configuration */
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        /* TI1 Configuration */
+        TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        /* Set the Input Capture Prescaler value */
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/**
+* @brief  Configures the: Break feature, dead time, Lock level, the OSSI,
+*   the OSSR State and the AOE(automatic output enable).
+* @param TIMx: where x can be  1  to select the TIM
+* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef
+*   structure that contains the BDTR Register configuration
+*   information for the TIM peripheral.
+* @retval : None
+*/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+    assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+    assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+    assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+    assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+    assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+    /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
+    the OSSI State, the dead time value and the Automatic Output Enable Bit */
+    TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+* @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+*   structure which will be initialized.
+* @retval : None
+*/
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+    /* Set the default configuration */
+    TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+    TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+    TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+    TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+    TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+* @brief  Fills each TIM_OCInitStruct member with its default value.
+* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+    /* Set the default configuration */
+    TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+    TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+    TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+    TIM_OCInitStruct->TIM_Pulse = 0x0000;
+    TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+    TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+* @brief  Fills each TIM_ICInitStruct member with its default value.
+* @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+    /* Set the default configuration */
+    TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+    TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+    TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+    TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+    TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+* @brief  Fills each TIM_BDTRInitStruct member with its default value.
+* @param TIM_BDTRInitStruct : pointer to a TIM_BDTRInitTypeDef
+*   structure which will be initialized.
+* @retval : None
+*/
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+    /* Set the default configuration */
+    TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+    TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+    TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+    TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+    TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+    TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+    TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+* @brief  Enables or disables the specified TIM peripheral.
+* @param TIMx: where x can be 1 to 4 to select the TIMx peripheral.
+* @param NewState: new state of the TIMx peripheral.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+
+    if (NewState != DISABLE)
+    {
+
+        /* Enable the TIM Counter */
+        TIMx->CR1 |= CR1_CEN_Set;
+
+    }
+    else
+    {
+        /* Disable the TIM Counter */
+        TIMx->CR1 &= CR1_CEN_Reset;
+    }
+
+}
+
+/**
+* @brief  Enables or disables the TIM peripheral Main Outputs.
+* @param TIMx: where x can be 1  to select the TIMx peripheral.
+* @param NewState: new state of the TIM peripheral Main Outputs.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the TIM Main Output */
+        TIMx->BDTR |= BDTR_MOE_Set;
+    }
+    else
+    {
+        /* Disable the TIM Main Output */
+        TIMx->BDTR &= BDTR_MOE_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified TIM interrupts.
+* @param TIMx: where x can be 1 to 4 to select the TIMx peripheral.
+* @param TIM_IT: specifies the TIM interrupts sources to be enabled
+*   or disabled.
+*   This parameter can be any combination of the following values:
+* @arg TIM_IT_Update: TIM update Interrupt source
+* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+* @arg TIM_IT_COM: TIM Commutation Interrupt source
+* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+* @arg TIM_IT_Break: TIM Break Interrupt source
+* @param NewState: new state of the TIM interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+    unsigned int temp = 0;
+    temp = temp;
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_IT(TIM_IT));
+    assert_param(IS_TIM_PERIPH_IT((TIMx), (TIM_IT)));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the Interrupt sources */
+        TIMx->DIER |= TIM_IT;
+        temp = TIMx->DIER;
+    }
+    else
+    {
+        /* Disable the Interrupt sources */
+        TIMx->DIER &= (uint16_t)~TIM_IT;
+    }
+
+}
+
+/**
+* @brief  Configures the TIMx event to be generate by software.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_EventSource: specifies the event source.
+*   This parameter can be one or more of the following values:
+* @arg TIM_EventSource_Update: Timer update Event source
+* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+* @arg TIM_EventSource_Trigger: Timer Trigger Event source
+* @retval : None
+*/
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+    assert_param(IS_TIM_PERIPH_EVENT((TIMx), (TIM_EventSource)));
+    /* Set the event sources */
+    TIMx->EGR = TIM_EventSource;
+}
+
+/**
+* @brief  Configures the TIMx’s DMA interface.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_DMABase: DMA Base address.
+*   This parameter can be one of the following values:
+* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
+*   TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
+*   TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
+*   TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
+*   TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
+*   TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
+*   TIM_DMABase_DCR.
+* @param TIM_DMABurstLength: DMA Burst length.
+*   This parameter can be one value between:
+*   TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.
+* @retval : None
+*/
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
+    assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+    /* Set the DMA Base and the DMA Burst Length */
+    TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+* @brief  Enables or disables the TIMx’s DMA Requests.
+* @param TIMx: where x can be  1 to 4 to select the TIM peripheral.
+* @param TIM_DMASource: specifies the DMA Request sources.
+*   This parameter can be any combination of the following values:
+* @arg TIM_DMA_Update: TIM update Interrupt source
+* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+* @arg TIM_DMA_COM: TIM Commutation DMA source
+* @arg TIM_DMA_Trigger: TIM Trigger DMA source
+* @param NewState: new state of the DMA Request sources.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+    assert_param(IS_TIM_PERIPH_DMA(TIMx, TIM_DMASource));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the DMA sources */
+        TIMx->DIER |= TIM_DMASource;
+    }
+    else
+    {
+        /* Disable the DMA sources */
+        TIMx->DIER &= (uint16_t)~TIM_DMASource;
+    }
+}
+
+/**
+* @brief  Configures the TIMx interrnal Clock
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @retval : None
+*/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Disable slave mode to clock the prescaler directly with the internal clock */
+    TIMx->SMCR &=  SMCR_SMS_Mask;
+}
+
+/**
+* @brief  Configures the TIMx Internal Trigger as External Clock
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ITRSource: Trigger source.
+*   This parameter can be one of the following values:
+* @param TIM_TS_ITR0: Internal Trigger 0
+* @param TIM_TS_ITR1: Internal Trigger 1
+* @param TIM_TS_ITR2: Internal Trigger 2
+* @param TIM_TS_ITR3: Internal Trigger 3
+* @retval : None
+*/
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+    /* Select the Internal Trigger */
+    TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+    /* Select the External clock mode1 */
+    TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+* @brief  Configures the TIMx Trigger as External Clock
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_TIxExternalCLKSource: Trigger source.
+*   This parameter can be one of the following values:
+* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+* @param TIM_ICPolarity: specifies the TIx Polarity.
+*   This parameter can be:
+* @arg TIM_ICPolarity_Rising
+* @arg TIM_ICPolarity_Falling
+* @param ICFilter : specifies the filter value.
+*   This parameter must be a value between 0x0 and 0xF.
+* @retval : None
+*/
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
+    assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+    assert_param(IS_TIM_IC_FILTER(ICFilter));
+    /* Configure the Timer Input Clock Source */
+    if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+    {
+        TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+    else
+    {
+        TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+    /* Select the Trigger source */
+    TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+    /* Select the External clock mode1 */
+    TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+* @brief  Configures the External clock Mode1
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*   It can be one of the following values:
+* @arg TIM_ExtTRGPSC_OFF
+* @arg TIM_ExtTRGPSC_DIV2
+* @arg TIM_ExtTRGPSC_DIV4
+* @arg TIM_ExtTRGPSC_DIV8.
+* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+*   It can be one of the following values:
+* @arg TIM_ExtTRGPolarity_Inverted
+* @arg TIM_ExtTRGPolarity_NonInverted
+* @param ExtTRGFilter: External Trigger Filter.
+*   This parameter must be a value between 0x00 and 0x0F
+* @retval : None
+*/
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+    assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+    assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+    /* Configure the ETR Clock source */
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+    /* Get the TIMx SMCR register value */
+    tmpsmcr = TIMx->SMCR;
+    /* Reset the SMS Bits */
+    tmpsmcr &= SMCR_SMS_Mask;
+    /* Select the External clock mode1 */
+    tmpsmcr |= TIM_SlaveMode_External1;
+    /* Select the Trigger selection : ETRF */
+    tmpsmcr &= SMCR_TS_Mask;
+    tmpsmcr |= TIM_TS_ETRF;
+    /* Write to TIMx SMCR */
+    TIMx->SMCR = tmpsmcr;
+}
+
+/**
+* @brief  Configures the External clock Mode2
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*   It can be one of the following values:
+* @arg TIM_ExtTRGPSC_OFF
+* @arg TIM_ExtTRGPSC_DIV2
+* @arg TIM_ExtTRGPSC_DIV4
+* @arg TIM_ExtTRGPSC_DIV8
+* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+*   It can be one of the following values:
+* @arg TIM_ExtTRGPolarity_Inverted
+* @arg TIM_ExtTRGPolarity_NonInverted
+* @param ExtTRGFilter: External Trigger Filter.
+*   This parameter must be a value between 0x00 and 0x0F
+* @retval : None
+*/
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+    assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+    assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+    /* Configure the ETR Clock source */
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    /* Enable the External clock mode2 */
+    TIMx->SMCR |= SMCR_ECE_Set;
+}
+
+/**
+* @brief  Configures the TIMx External Trigger (ETR).
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+*   This parameter can be one of the following values:
+* @arg TIM_ExtTRGPSC_OFF
+* @arg TIM_ExtTRGPSC_DIV2
+* @arg TIM_ExtTRGPSC_DIV4
+* @arg TIM_ExtTRGPSC_DIV8
+* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+*   This parameter can be one of the following values:
+* @arg TIM_ExtTRGPolarity_Inverted
+* @arg TIM_ExtTRGPolarity_NonInverted
+* @param ExtTRGFilter: External Trigger Filter.
+*   This parameter must be a value between 0x00 and 0x0F.
+* @retval : None
+*/
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+    assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+    assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+    tmpsmcr = TIMx->SMCR;
+    /* Reset the ETR Bits */
+    tmpsmcr &= SMCR_ETR_Mask;
+    /* Set the Prescaler, the Filter value and the Polarity */
+    tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << 8);
+    /* Write to TIMx SMCR */
+    TIMx->SMCR = tmpsmcr;
+}
+
+/**
+* @brief  Configures the TIMx Prescaler.
+* @param TIMx: where x can be  1 to 4 to select the TIM peripheral.
+* @param Prescaler: specifies the Prescaler Register value
+* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+*   This parameter can be one of the following values:
+* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at
+*   the update event.
+* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded
+*   immediatly.
+* @retval : None
+*/
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+    /* Set the Prescaler value */
+    TIMx->PSC = Prescaler;
+    /* Set or reset the UG Bit */
+    TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+* @brief  Specifies the TIMx Counter Mode to be used.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_CounterMode: specifies the Counter Mode to be used
+*   This parameter can be one of the following values:
+* @arg TIM_CounterMode_Up: TIM Up Counting Mode
+* @arg TIM_CounterMode_Down: TIM Down Counting Mode
+* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+* @retval : None
+*/
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+    uint16_t tmpcr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+    tmpcr1 = TIMx->CR1;
+    /* Reset the CMS and DIR Bits */
+    tmpcr1 &= CR1_CounterMode_Mask;
+    /* Set the Counter Mode */
+    tmpcr1 |= TIM_CounterMode;
+    /* Write to TIMx CR1 register */
+    TIMx->CR1 = tmpcr1;
+
+}
+
+/**
+* @brief  Selects the Input Trigger source
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_InputTriggerSource: The Input Trigger source.
+*   This parameter can be one of the following values:
+* @arg TIM_TS_ITR0: Internal Trigger 0
+* @arg TIM_TS_ITR1: Internal Trigger 1
+* @arg TIM_TS_ITR2: Internal Trigger 2
+* @arg TIM_TS_ITR3: Internal Trigger 3
+* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+* @arg TIM_TS_ETRF: External Trigger input
+* @retval : None
+*/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+    uint16_t tmpsmcr = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+    /* Get the TIMx SMCR register value */
+    tmpsmcr = TIMx->SMCR;
+    /* Reset the TS Bits */
+    tmpsmcr &= SMCR_TS_Mask;
+    /* Set the Input Trigger source */
+    tmpsmcr |= TIM_InputTriggerSource;
+    /* Write to TIMx SMCR */
+    TIMx->SMCR = tmpsmcr;
+}
+
+/**
+* @brief  Configures the TIMx Encoder Interface.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
+*   This parameter can be one of the following values:
+* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge
+*   depending on TI2FP2 level.
+* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge
+*   depending on TI1FP1 level.
+* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and
+*   TI2FP2 edges depending on the level of the other input.
+* @param TIM_IC1Polarity: specifies the IC1 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_ICPolarity_Falling: IC Falling edge.
+* @arg TIM_ICPolarity_Rising: IC Rising edge.
+* @param TIM_IC2Polarity: specifies the IC2 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_ICPolarity_Falling: IC Falling edge.
+* @arg TIM_ICPolarity_Rising: IC Rising edge.
+* @retval : None
+*/
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+    uint16_t tmpsmcr = 0;
+    uint16_t tmpccmr1 = 0;
+    uint16_t tmpccer = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+    assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+    assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+    /* Get the TIMx SMCR register value */
+    tmpsmcr = TIMx->SMCR;
+    /* Get the TIMx CCMR1 register value */
+    tmpccmr1 = TIMx->CCMR1;
+    /* Get the TIMx CCER register value */
+    tmpccer = TIMx->CCER;
+    /* Set the encoder Mode */
+    tmpsmcr &= SMCR_SMS_Mask;
+    tmpsmcr |= TIM_EncoderMode;
+    /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+    tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
+    tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
+    /* Set the TI1 and the TI2 Polarities */
+    tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
+    tmpccer |= (TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << 4));
+    /* Write to TIMx SMCR */
+    TIMx->SMCR = tmpsmcr;
+    /* Write to TIMx CCMR1 */
+    TIMx->CCMR1 = tmpccmr1;
+    /* Write to TIMx CCER */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Forces the TIMx output 1 waveform to active or inactive level.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ForcedAction: specifies the forced Action to be set to
+*   the output waveform.
+*   This parameter can be one of the following values:
+* @arg TIM_ForcedAction_Active: Force active level on OC1REF
+* @arg TIM_ForcedAction_InActive: Force inactive level on
+*   OC1REF.
+* @retval : None
+*/
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC1M Bits */
+    tmpccmr1 &= CCMR_OC13M_Mask;
+    /* Configure The Forced output Mode */
+    tmpccmr1 |= TIM_ForcedAction;
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Forces the TIMx output 2 waveform to active or inactive level.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ForcedAction: specifies the forced Action to be set to
+*   the output waveform.
+*   This parameter can be one of the following values:
+* @arg TIM_ForcedAction_Active: Force active level on OC2REF
+* @arg TIM_ForcedAction_InActive: Force inactive level on
+*   OC2REF.
+* @retval : None
+*/
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC2M Bits */
+    tmpccmr1 &= CCMR_OC24M_Mask;
+    /* Configure The Forced output Mode */
+    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Forces the TIMx output 3 waveform to active or inactive level.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ForcedAction: specifies the forced Action to be set to
+*   the output waveform.
+*   This parameter can be one of the following values:
+* @arg TIM_ForcedAction_Active: Force active level on OC3REF
+* @arg TIM_ForcedAction_InActive: Force inactive level on
+*   OC3REF.
+* @retval : None
+*/
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC1M Bits */
+    tmpccmr2 &= CCMR_OC13M_Mask;
+    /* Configure The Forced output Mode */
+    tmpccmr2 |= TIM_ForcedAction;
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Forces the TIMx output 4 waveform to active or inactive level.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ForcedAction: specifies the forced Action to be set to
+*   the output waveform.
+*   This parameter can be one of the following values:
+* @arg TIM_ForcedAction_Active: Force active level on OC4REF
+* @arg TIM_ForcedAction_InActive: Force inactive level on
+*   OC4REF.
+* @retval : None
+*/
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC2M Bits */
+    tmpccmr2 &= CCMR_OC24M_Mask;
+    /* Configure The Forced output Mode */
+    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Enables or disables TIMx peripheral Preload register on ARR.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param NewState: new state of the TIMx peripheral Preload register
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the ARR Preload Bit */
+        TIMx->CR1 |= CR1_ARPE_Set;
+    }
+    else
+    {
+        /* Reset the ARR Preload Bit */
+        TIMx->CR1 &= CR1_ARPE_Reset;
+    }
+
+}
+
+/**
+* @brief  Selects the TIM peripheral Commutation event.
+* @param TIMx: where x can be  1  to select the TIMx peripheral
+* @param NewState: new state of the Commutation event.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the COM Bit */
+        TIMx->CR2 |= CR2_CCUS_Set;
+    }
+    else
+    {
+        /* Reset the COM Bit */
+        TIMx->CR2 &= CR2_CCUS_Reset;
+    }
+}
+
+/**
+* @brief  Selects the TIMx peripheral Capture Compare DMA source.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param NewState: new state of the Capture Compare DMA source
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the CCDS Bit */
+        TIMx->CR2 |= CR2_CCDS_Set;
+    }
+    else
+    {
+        /* Reset the CCDS Bit */
+        TIMx->CR2 &= CR2_CCDS_Reset;
+    }
+}
+
+/**
+* @brief  Sets or Resets the TIM peripheral Capture Compare Preload
+*   Control bit.
+* @param TIMx: where x can be  1  to select the TIMx peripheral
+* @param NewState: new state of the Capture Compare Preload Control bit
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the CCPC Bit */
+        TIMx->CR2 |= CR2_CCPC_Set;
+    }
+    else
+    {
+        /* Reset the CCPC Bit */
+        TIMx->CR2 &= CR2_CCPC_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPreload: new state of the TIMx peripheral Preload
+*   register
+*   This parameter can be one of the following values:
+* @arg TIM_OCPreload_Enable
+* @arg TIM_OCPreload_Disable
+* @retval : None
+*/
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC1PE Bit */
+    tmpccmr1 &= CCMR_OC13PE_Reset;
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr1 |= TIM_OCPreload;
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPreload: new state of the TIMx peripheral Preload
+*   register
+*   This parameter can be one of the following values:
+* @arg TIM_OCPreload_Enable
+* @arg TIM_OCPreload_Disable
+* @retval : None
+*/
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC2PE Bit */
+    tmpccmr1 &= CCMR_OC24PE_Reset;
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPreload: new state of the TIMx peripheral Preload
+*   register
+*   This parameter can be one of the following values:
+* @arg TIM_OCPreload_Enable
+* @arg TIM_OCPreload_Disable
+* @retval : None
+*/
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC3PE Bit */
+    tmpccmr2 &= CCMR_OC13PE_Reset;
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr2 |= TIM_OCPreload;
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPreload: new state of the TIMx peripheral Preload
+*   register
+*   This parameter can be one of the following values:
+* @arg TIM_OCPreload_Enable
+* @arg TIM_OCPreload_Disable
+* @retval : None
+*/
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC4PE Bit */
+    tmpccmr2 &= CCMR_OC24PE_Reset;
+    /* Enable or Disable the Output Compare Preload feature */
+    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Configures the TIMx Output Compare 1 Fast feature.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCFast_Enable: TIM output compare fast enable
+* @arg TIM_OCFast_Disable: TIM output compare fast disable
+* @retval : None
+*/
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+    /* Get the TIMx CCMR1 register value */
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC1FE Bit */
+    tmpccmr1 &= CCMR_OC13FE_Reset;
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr1 |= TIM_OCFast;
+    /* Write to TIMx CCMR1 */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Configures the TIMx Output Compare 2 Fast feature.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCFast_Enable: TIM output compare fast enable
+* @arg TIM_OCFast_Disable: TIM output compare fast disable
+* @retval : None
+*/
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+    /* Get the TIMx CCMR1 register value */
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC2FE Bit */
+    tmpccmr1 &= CCMR_OC24FE_Reset;
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+    /* Write to TIMx CCMR1 */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Configures the TIMx Output Compare 3 Fast feature.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCFast_Enable: TIM output compare fast enable
+* @arg TIM_OCFast_Disable: TIM output compare fast disable
+* @retval : None
+*/
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+    /* Get the TIMx CCMR2 register value */
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC3FE Bit */
+    tmpccmr2 &= CCMR_OC13FE_Reset;
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr2 |= TIM_OCFast;
+    /* Write to TIMx CCMR2 */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Configures the TIMx Output Compare 4 Fast feature.
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCFast_Enable: TIM output compare fast enable
+* @arg TIM_OCFast_Disable: TIM output compare fast disable
+* @retval : None
+*/
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+    /* Get the TIMx CCMR2 register value */
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC4FE Bit */
+    tmpccmr2 &= CCMR_OC24FE_Reset;
+    /* Enable or Disable the Output Compare Fast Bit */
+    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+    /* Write to TIMx CCMR2 */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Clears or safeguards the OCREF1 signal on an external event
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCClear_Enable: TIM Output clear enable
+* @arg TIM_OCClear_Disable: TIM Output clear disable
+* @retval : None
+*/
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC1CE Bit */
+    tmpccmr1 &= CCMR_OC13CE_Reset;
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr1 |= TIM_OCClear;
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Clears or safeguards the OCREF2 signal on an external event
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCClear_Enable: TIM Output clear enable
+* @arg TIM_OCClear_Disable: TIM Output clear disable
+* @retval : None
+*/
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+    tmpccmr1 = TIMx->CCMR1;
+    /* Reset the OC2CE Bit */
+    tmpccmr1 &= CCMR_OC24CE_Reset;
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+    /* Write to TIMx CCMR1 register */
+    TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+* @brief  Clears or safeguards the OCREF3 signal on an external event
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCClear_Enable: TIM Output clear enable
+* @arg TIM_OCClear_Disable: TIM Output clear disable
+* @retval : None
+*/
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC3CE Bit */
+    tmpccmr2 &= CCMR_OC13CE_Reset;
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr2 |= TIM_OCClear;
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Clears or safeguards the OCREF4 signal on an external event
+* @param TIMx: where x can be  1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+*   This parameter can be one of the following values:
+* @arg TIM_OCClear_Enable: TIM Output clear enable
+* @arg TIM_OCClear_Disable: TIM Output clear disable
+* @retval : None
+*/
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+    tmpccmr2 = TIMx->CCMR2;
+    /* Reset the OC4CE Bit */
+    tmpccmr2 &= CCMR_OC24CE_Reset;
+    /* Enable or Disable the Output Compare Clear Bit */
+    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+    /* Write to TIMx CCMR2 register */
+    TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+* @brief  Configures the TIMx channel 1 polarity.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPolarity: specifies the OC1 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCPolarity_High: Output Compare active high
+* @arg TIM_OCPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC1P Bit */
+    tmpccer &= CCER_CC1P_Reset;
+    tmpccer |= TIM_OCPolarity;
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx Channel 1N polarity.
+* @param TIMx: where x can be 1  to select the TIM peripheral.
+* @param TIM_OCNPolarity: specifies the OC1N Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCNPolarity_High: Output Compare active high
+* @arg TIM_OCNPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC1NP Bit */
+    tmpccer &= CCER_CC1NP_Reset;
+    tmpccer |= TIM_OCNPolarity;
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx channel 2 polarity.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPolarity: specifies the OC2 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCPolarity_High: Output Compare active high
+* @arg TIM_OCPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC2P Bit */
+    tmpccer &= CCER_CC2P_Reset;
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx Channel 2N polarity.
+* @param TIMx: where x can be 1  to select the TIM peripheral.
+* @param TIM_OCNPolarity: specifies the OC2N Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCNPolarity_High: Output Compare active high
+* @arg TIM_OCNPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC2NP Bit */
+    tmpccer &= CCER_CC2NP_Reset;
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx channel 3 polarity.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPolarity: specifies the OC3 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCPolarity_High: Output Compare active high
+* @arg TIM_OCPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC3P Bit */
+    tmpccer &= CCER_CC3P_Reset;
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx Channel 3N polarity.
+* @param TIMx: where x can be 1  to select the TIM peripheral.
+* @param TIM_OCNPolarity: specifies the OC3N Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCNPolarity_High: Output Compare active high
+* @arg TIM_OCNPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC3NP Bit */
+    tmpccer &= CCER_CC3NP_Reset;
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configures the TIMx channel 4 polarity.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_OCPolarity: specifies the OC4 Polarity
+*   This parmeter can be one of the following values:
+* @arg TIM_OCPolarity_High: Output Compare active high
+* @arg TIM_OCPolarity_Low: Output Compare active low
+* @retval : None
+*/
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+    tmpccer = TIMx->CCER;
+    /* Set or Reset the CC4P Bit */
+    tmpccer &= CCER_CC4P_Reset;
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+    /* Write to TIMx CCER register */
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Enables or disables the TIM Capture Compare Channel x.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_Channel: specifies the TIM Channel
+*   This parmeter can be one of the following values:
+* @arg TIM_Channel_1: TIM Channel 1
+* @arg TIM_Channel_2: TIM Channel 2
+* @arg TIM_Channel_3: TIM Channel 3
+* @arg TIM_Channel_4: TIM Channel 4
+* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
+*   This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
+* @retval : None
+*/
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_CHANNEL(TIM_Channel));
+    assert_param(IS_TIM_CCX(TIM_CCx));
+    /* Reset the CCxE Bit */
+    TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCE_Set << TIM_Channel)));
+    /* Set or reset the CCxE Bit */
+    TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+* @brief  Enables or disables the TIM Capture Compare Channel xN.
+* @param TIMx: where x can be 1  to select the TIM peripheral.
+* @param TIM_Channel: specifies the TIM Channel
+*   This parmeter can be one of the following values:
+* @arg TIM_Channel_1: TIM Channel 1
+* @arg TIM_Channel_2: TIM Channel 2
+* @arg TIM_Channel_3: TIM Channel 3
+* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+*   This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
+* @retval : None
+*/
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_18_PERIPH(TIMx));
+    assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+    assert_param(IS_TIM_CCXN(TIM_CCxN));
+    /* Reset the CCxNE Bit */
+    TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCNE_Set << TIM_Channel)));
+    /* Set or reset the CCxNE Bit */
+    TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/**
+* @brief  Selects the TIM Ouput Compare Mode.
+*   This function disables the selected channel before changing
+*   the Ouput Compare Mode. User has to enable this channel using
+*   TIM_CCxCmd and TIM_CCxNCmd functions.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_Channel: specifies the TIM Channel
+*   This parmeter can be one of the following values:
+* @arg TIM_Channel_1: TIM Channel 1
+* @arg TIM_Channel_2: TIM Channel 2
+* @arg TIM_Channel_3: TIM Channel 3
+* @arg TIM_Channel_4: TIM Channel 4
+* @param TIM_OCMode: specifies the TIM Output Compare Mode.
+*   This paramter can be one of the following values:
+* @arg TIM_OCMode_Timing
+* @arg TIM_OCMode_Active
+* @arg TIM_OCMode_Toggle
+* @arg TIM_OCMode_PWM1
+* @arg TIM_OCMode_PWM2
+* @arg TIM_ForcedAction_Active
+* @arg TIM_ForcedAction_InActive
+* @retval : None
+*/
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_CHANNEL(TIM_Channel));
+    assert_param(IS_TIM_OCM(TIM_OCMode));
+
+    /* Disable the Channel: Reset the CCxE Bit */
+    TIMx->CCER &= (uint16_t)(~((uint16_t)(CCER_CCE_Set << TIM_Channel)));
+    if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3))
+    {
+        /* Reset the OCxM bits in the CCMRx register */
+        *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + (TIM_Channel >> 1))) &= CCMR_OC13M_Mask;
+
+        /* Configure the OCxM bits in the CCMRx register */
+        *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + (TIM_Channel >> 1))) |= TIM_OCMode;
+    }
+    else
+    {
+        /* Reset the OCxM bits in the CCMRx register */
+        *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + ((uint16_t)(TIM_Channel - 4) >> 1))) &= CCMR_OC24M_Mask;
+
+        /* Configure the OCxM bits in the CCMRx register */
+        *((__IO uint32_t *)((*(uint32_t*)&TIMx) + CCMR_Offset + ((uint16_t)(TIM_Channel - 4) >> 1))) |= (uint16_t)(TIM_OCMode << 8);
+    }
+}
+
+/**
+* @brief  Enables or Disables the TIMx Update event.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param NewState: new state of the TIMx UDIS bit
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the Update Disable Bit */
+        TIMx->CR1 |= CR1_UDIS_Set;
+    }
+    else
+    {
+        /* Reset the Update Disable Bit */
+        TIMx->CR1 &= CR1_UDIS_Reset;
+    }
+}
+
+/**
+* @brief  Configures the TIMx Update Request Interrupt source.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_UpdateSource: specifies the Update source.
+*   This parameter can be one of the following values:
+* @arg TIM_UpdateSource_Regular
+* @arg TIM_UpdateSource_Global
+* @retval : None
+*/
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+    if (TIM_UpdateSource != TIM_UpdateSource_Global)
+    {
+        /* Set the URS Bit */
+        TIMx->CR1 |= CR1_URS_Set;
+    }
+    else
+    {
+        /* Reset the URS Bit */
+        TIMx->CR1 &= CR1_URS_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the TIMx’s Hall sensor interface.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM peripheral.
+* @param NewState: new state of the TIMx Hall sensor interface.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Set the TI1S Bit */
+        TIMx->CR2 |= CR2_TI1S_Set;
+    }
+    else
+    {
+        /* Reset the TI1S Bit */
+        TIMx->CR2 &= CR2_TI1S_Reset;
+    }
+}
+
+/**
+* @brief  Selects the TIMx’s One Pulse Mode.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_OPMode: specifies the OPM Mode to be used.
+*   This parameter can be one of the following values:
+* @arg TIM_OPMode_Single
+* @arg TIM_OPMode_Repetitive
+* @retval : None
+*/
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+    /* Reset the OPM Bit */
+    TIMx->CR1 &= CR1_OPM_Reset;
+    /* Configure the OPM Mode */
+    TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+* @brief  Selects the TIMx Trigger Output Mode.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_TRGOSource: specifies the Trigger Output source.
+*   This paramter can be as follow:
+*   1/ For TIM1 to TIM8:
+* @arg TIM_TRGOSource_Reset
+* @arg TIM_TRGOSource_Enable
+* @arg TIM_TRGOSource_Update
+*   2/ These parameters are available for all TIMx
+* @arg TIM_TRGOSource_OC1
+* @arg TIM_TRGOSource_OC1Ref
+* @arg TIM_TRGOSource_OC2Ref
+* @arg TIM_TRGOSource_OC3Ref
+* @arg TIM_TRGOSource_OC4Ref
+* @retval : None
+*/
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+    assert_param(IS_TIM_PERIPH_TRGO(TIMx, TIM_TRGOSource));
+    /* Reset the MMS Bits */
+    TIMx->CR2 &= CR2_MMS_Mask;
+    /* Select the TRGO source */
+    TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+* @brief  Selects the TIMx Slave Mode.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_SlaveMode: specifies the Timer Slave Mode.
+*   This paramter can be one of the following values:
+* @arg TIM_SlaveMode_Reset
+* @arg TIM_SlaveMode_Gated
+* @arg TIM_SlaveMode_Trigger
+* @arg TIM_SlaveMode_External1
+* @retval : None
+*/
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+    /* Reset the SMS Bits */
+    TIMx->SMCR &= SMCR_SMS_Mask;
+    /* Select the Slave Mode */
+    TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+* @brief  Sets or Resets the TIMx Master/Slave Mode.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+*   This paramter can be one of the following values:
+* @arg TIM_MasterSlaveMode_Enable: synchronization between the
+*   current timer and its slaves (through TRGO).
+* @arg TIM_MasterSlaveMode_Disable: No action
+* @retval : None
+*/
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+    /* Reset the MSM Bit */
+    TIMx->SMCR &= SMCR_MSM_Reset;
+
+    /* Set or Reset the MSM Bit */
+    TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+* @brief  Sets the TIMx Counter Register value
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param Counter: specifies the Counter register new value.
+* @retval : None
+*/
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    /* Set the Counter Register value */
+    TIMx->CNT = Counter;
+}
+
+/**
+* @brief  Sets the TIMx Autoreload Register value
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param Autoreload: specifies the Autoreload register new value.
+* @retval : None
+*/
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    /* Set the Autoreload Register value */
+    TIMx->ARR = Autoreload;
+}
+
+/**
+* @brief  Sets the TIMx Capture Compare1 Register value
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param Compare1: specifies the Capture Compare1 register new value.
+* @retval : None
+*/
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Set the Capture Compare1 Register value */
+    TIMx->CCR1 = Compare1;
+}
+
+/**
+* @brief  Sets the TIMx Capture Compare2 Register value
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param Compare2: specifies the Capture Compare2 register new value.
+* @retval : None
+*/
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Set the Capture Compare2 Register value */
+    TIMx->CCR2 = Compare2;
+}
+
+/**
+* @brief  Sets the TIMx Capture Compare3 Register value
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param Compare3: specifies the Capture Compare3 register new value.
+* @retval : None
+*/
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Set the Capture Compare3 Register value */
+    TIMx->CCR3 = Compare3;
+}
+
+/**
+* @brief  Sets the TIMx Capture Compare4 Register value
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param Compare4: specifies the Capture Compare4 register new value.
+* @retval : None
+*/
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Set the Capture Compare4 Register value */
+    TIMx->CCR4 = Compare4;
+}
+
+/**
+* @brief  Sets the TIMx Input Capture 1 prescaler.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPSC: specifies the Input Capture1 prescaler
+*   new value.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPSC_DIV1: no prescaler
+* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+* @retval : None
+*/
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+    /* Reset the IC1PSC Bits */
+    TIMx->CCMR1 &= CCMR_IC13PSC_Mask;
+    /* Set the IC1PSC value */
+    TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+* @brief  Sets the TIMx Input Capture 2 prescaler.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPSC: specifies the Input Capture2 prescaler
+*   new value.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPSC_DIV1: no prescaler
+* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+* @retval : None
+*/
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+    /* Reset the IC2PSC Bits */
+    TIMx->CCMR1 &= CCMR_IC24PSC_Mask;
+    /* Set the IC2PSC value */
+    TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+* @brief  Sets the TIMx Input Capture 3 prescaler.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPSC: specifies the Input Capture3 prescaler
+*   new value.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPSC_DIV1: no prescaler
+* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+* @retval : None
+*/
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+    /* Reset the IC3PSC Bits */
+    TIMx->CCMR2 &= CCMR_IC13PSC_Mask;
+    /* Set the IC3PSC value */
+    TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+* @brief  Sets the TIMx Input Capture 4 prescaler.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPSC: specifies the Input Capture4 prescaler
+*   new value.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPSC_DIV1: no prescaler
+* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+* @retval : None
+*/
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+    /* Reset the IC4PSC Bits */
+    TIMx->CCMR2 &= CCMR_IC24PSC_Mask;
+    /* Set the IC4PSC value */
+    TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+* @brief  Sets the TIMx Clock Division value.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_CKD: specifies the clock division value.
+*   This parameter can be one of the following value:
+* @arg TIM_CKD_DIV1: TDTS = Tck_tim
+* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+* @retval : None
+*/
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+    /* Reset the CKD Bits */
+    TIMx->CR1 &= CR1_CKD_Mask;
+    /* Set the CKD value */
+    TIMx->CR1 |= TIM_CKD;
+
+}
+
+/**
+* @brief  Gets the TIMx Input Capture 1 value.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @retval : Capture Compare 1 Register value.
+*/
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Get the Capture 1 Register value */
+    return TIMx->CCR1;
+}
+
+/**
+* @brief  Gets the TIMx Input Capture 2 value.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @retval : Capture Compare 2 Register value.
+*/
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Get the Capture 2 Register value */
+    return TIMx->CCR2;
+}
+
+/**
+* @brief  Gets the TIMx Input Capture 3 value.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @retval : Capture Compare 3 Register value.
+*/
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Get the Capture 3 Register value */
+    return TIMx->CCR3;
+}
+
+/**
+* @brief  Gets the TIMx Input Capture 4 value.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @retval : Capture Compare 4 Register value.
+*/
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_123458_PERIPH(TIMx));
+    /* Get the Capture 4 Register value */
+    return TIMx->CCR4;
+}
+
+/**
+* @brief  Gets the TIMx Counter value.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @retval : Counter Register value.
+*/
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    /* Get the Counter Register value */
+    return TIMx->CNT;
+}
+
+/**
+* @brief  Gets the TIMx Prescaler value.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @retval : Prescaler Register value.
+*/
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    /* Get the Prescaler Register value */
+    return TIMx->PSC;
+}
+
+/**
+* @brief  Checks whether the specified TIM flag is set or not.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg TIM_FLAG_Update: TIM update Flag
+* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+* @arg TIM_FLAG_COM: TIM Commutation Flag
+* @arg TIM_FLAG_Trigger: TIM Trigger Flag
+* @arg TIM_FLAG_Break: TIM Break Flag
+* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+* @retval : The new state of TIM_FLAG (SET or RESET).
+*/
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+    ITStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+    assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG));
+
+    if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the TIMx's pending flags.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_FLAG: specifies the flag bit to clear.
+*   This parameter can be any combination of the following values:
+* @arg TIM_FLAG_Update: TIM update Flag
+* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+* @arg TIM_FLAG_COM: TIM Commutation Flag
+* @arg TIM_FLAG_Trigger: TIM Trigger Flag
+* @arg TIM_FLAG_Break: TIM Break Flag
+* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
+* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
+* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
+* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
+* @retval : None
+*/
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_CLEAR_FLAG(TIMx, TIM_FLAG));
+
+    /* Clear the flags */
+    TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+* @brief  Checks whether the TIM interrupt has occurred or not.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_IT: specifies the TIM interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg TIM_IT_Update: TIM update Interrupt source
+* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+* @arg TIM_IT_COM: TIM Commutation Interrupt
+*   source
+* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+* @arg TIM_IT_Break: TIM Break Interrupt source
+* @retval : The new state of the TIM_IT(SET or RESET).
+*/
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itstatus = 0x0, itenable = 0x0;
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_GET_IT(TIM_IT));
+    assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT));
+
+    itstatus = TIMx->SR & TIM_IT;
+
+    itenable = TIMx->DIER & TIM_IT;
+    if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the TIMx's interrupt pending bits.
+* @param TIMx: where x can be 1 to 4 to select the TIM peripheral.
+* @param TIM_IT: specifies the pending bit to clear.
+*   This parameter can be any combination of the following values:
+* @arg TIM_IT_Update: TIM1 update Interrupt source
+* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+* @arg TIM_IT_COM: TIM Commutation Interrupt
+*   source
+* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+* @arg TIM_IT_Break: TIM Break Interrupt source
+* @retval : None
+*/
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+    /* Check the parameters */
+    assert_param(IS_TIM_ALL_PERIPH(TIMx));
+    assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT));
+    /* Clear the IT pending Bit */
+    TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+* @brief  Configure the TI1 as Input.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPolarity : The Input Polarity.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPolarity_Rising
+* @arg TIM_ICPolarity_Falling
+* @param TIM_ICSelection: specifies the input to be used.
+*   This parameter can be one of the following values:
+* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to
+*   be connected to IC1.
+* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to
+*   be connected to IC2.
+* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be
+*   connected to TRC.
+* @param TIM_ICFilter: Specifies the Input Capture Filter.
+*   This parameter must be a value between 0x00 and 0x0F.
+* @retval : None
+*/
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0;
+    /* Disable the Channel 1: Reset the CC1E Bit */
+    TIMx->CCER &= CCER_CC1E_Reset;
+    tmpccmr1 = TIMx->CCMR1;
+    tmpccer = TIMx->CCER;
+    /* Select the Input and set the filter */
+    tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+    tmpccmr1 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4);
+    /* Select the Polarity and set the CC1E Bit */
+    tmpccer &= CCER_CC1P_Reset;
+    tmpccer |= TIM_ICPolarity | CCER_CC1E_Set;
+    /* Write to TIMx CCMR1 and CCER registers */
+    TIMx->CCMR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configure the TI2 as Input.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPolarity : The Input Polarity.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPolarity_Rising
+* @arg TIM_ICPolarity_Falling
+* @param TIM_ICSelection: specifies the input to be used.
+*   This parameter can be one of the following values:
+* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to
+*   be connected to IC2.
+* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to
+*   be connected to IC1.
+* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be
+*   connected to TRC.
+* @param TIM_ICFilter: Specifies the Input Capture Filter.
+*   This parameter must be a value between 0x00 and 0x0F.
+* @retval : None
+*/
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+    /* Disable the Channel 2: Reset the CC2E Bit */
+    TIMx->CCER &= CCER_CC2E_Reset;
+    tmpccmr1 = TIMx->CCMR1;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 4);
+    /* Select the Input and set the filter */
+    tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+    tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+    /* Select the Polarity and set the CC2E Bit */
+    tmpccer &= CCER_CC2P_Reset;
+    tmpccer |=  tmp | CCER_CC2E_Set;
+    /* Write to TIMx CCMR1 and CCER registers */
+    TIMx->CCMR1 = tmpccmr1 ;
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configure the TI3 as Input.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPolarity : The Input Polarity.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPolarity_Rising
+* @arg TIM_ICPolarity_Falling
+* @param TIM_ICSelection: specifies the input to be used.
+*   This parameter can be one of the following values:
+* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to
+*   be connected to IC3.
+* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to
+*   be connected to IC4.
+* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be
+*   connected to TRC.
+* @param TIM_ICFilter: Specifies the Input Capture Filter.
+*   This parameter must be a value between 0x00 and 0x0F.
+* @retval : None
+*/
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+    /* Disable the Channel 3: Reset the CC3E Bit */
+    TIMx->CCER &= CCER_CC3E_Reset;
+    tmpccmr2 = TIMx->CCMR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 8);
+    /* Select the Input and set the filter */
+    tmpccmr2 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
+    tmpccmr2 |= TIM_ICSelection | (uint16_t)(TIM_ICFilter << 4);
+    /* Select the Polarity and set the CC3E Bit */
+    tmpccer &= CCER_CC3P_Reset;
+    tmpccer |= tmp | CCER_CC3E_Set;
+    /* Write to TIMx CCMR2 and CCER registers */
+    TIMx->CCMR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}
+
+/**
+* @brief  Configure the TI1 as Input.
+* @param TIMx: where x can be 1, 2, 3, 4 to select the TIM
+*   peripheral.
+* @param TIM_ICPolarity : The Input Polarity.
+*   This parameter can be one of the following values:
+* @arg TIM_ICPolarity_Rising
+* @arg TIM_ICPolarity_Falling
+* @param TIM_ICSelection: specifies the input to be used.
+*   This parameter can be one of the following values:
+* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to
+*   be connected to IC4.
+* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to
+*   be connected to IC3.
+* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be
+*   connected to TRC.
+* @param TIM_ICFilter: Specifies the Input Capture Filter.
+*   This parameter must be a value between 0x00 and 0x0F.
+* @retval : None
+*/
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+    /* Disable the Channel 4: Reset the CC4E Bit */
+    TIMx->CCER &= CCER_CC4E_Reset;
+    tmpccmr2 = TIMx->CCMR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 12);
+    /* Select the Input and set the filter */
+    tmpccmr2 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12);
+    /* Select the Polarity and set the CC4E Bit */
+    tmpccer &= CCER_CC4P_Reset;
+    tmpccer |= tmp | CCER_CC4E_Set;
+    /* Write to TIMx CCMR2 and CCER registers */
+    TIMx->CCMR2 = tmpccmr2;
+    TIMx->CCER = tmpccer ;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_uart.c

@@ -0,0 +1,463 @@
+/**
+******************************************************************************
+* @file    HAL_UART.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the UART firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_uart.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup UART
+* @brief UART driver modules
+* @{
+*/
+
+/** @defgroup UART_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Private_Defines
+* @{
+*/
+
+
+
+/* UART UE Mask */
+#define GCR_UE_Set                ((uint16_t)0x0001)  /* UART Enable Mask */
+#define GCR_UE_Reset              ((uint16_t)0xFFFE)  /* UART Disable Mask */
+
+//#define CCR_CLEAR_Mask       			((uint32_t)0xFFFFFF30)  /* UART CCR Mask */
+#define CCR_CLEAR_Mask       			((uint32_t)0xFFFFFFC9)  /* UART CCR Mask */
+#define GCR_CLEAR_Mask       			((uint32_t)0xFFFFFFE0)  /* UART GCR Mask */
+/**
+* @}
+*/
+
+/** @defgroup UART_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup UART_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the UARTx peripheral registers to their
+*   default reset values.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @retval : None
+*/
+void UART_DeInit(UART_TypeDef* UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    switch (*(uint32_t*)&UARTx)
+    {
+        case UART1_BASE:
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART1, DISABLE);
+            break;
+        case UART2_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, DISABLE);
+            break;
+        case UART3_BASE:
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, DISABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+/**
+* @brief  Initializes the UARTx peripheral according to the specified
+*   parameters in the UART_InitStruct .
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param UART_InitStruct: pointer to a UART_InitTypeDef structure
+*   that contains the configuration information for the
+*   specified UART peripheral.
+* @retval : None
+*/
+void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
+{
+    uint32_t tmpreg = 0x00, apbclock = 0x00;
+    uint32_t tmpreg1 = 0x00;
+    uint32_t UARTxbase = 0;
+    RCC_ClocksTypeDef RCC_ClocksStatus;
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate));
+    assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
+    assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
+    assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
+    assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
+    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
+
+    UARTxbase = (*(uint32_t*)&UARTx);
+    /*---------------------------- UART CCR Configuration -----------------------*/
+    /* get UART CCR values */
+    tmpreg = UARTx->CCR;
+    /* Clear spb,psel,pen bits */
+    tmpreg &= CCR_CLEAR_Mask;
+    /* Configure the UART Word Length,the UART Stop Bits,Parity ------------*/
+    /* Set the char bits according to UART_WordLength value */
+    /* Set spb bit according to UART_StopBits value */
+    /* Set PEN bit according to UART_Parity value */
+    tmpreg |= (uint32_t)UART_InitStruct->UART_WordLength | (uint32_t)UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity;
+
+    /* Write to UART CCR */
+    UARTx->CCR = tmpreg;
+
+    /*---------------------------- UART GCR Configuration -----------------------*/
+    /* get UART GCR values */
+    tmpreg = UARTx->GCR;
+    /* Clear TXEN and RXEN ,autoflowen, mode ,uarten bits */
+    tmpreg &= GCR_CLEAR_Mask;
+    /* Set autorlowen bit according to UART_HardwareFlowControl value */
+    /* Set rxen,txen bits according to UART_Mode value */
+    tmpreg |= UART_InitStruct->UART_HardwareFlowControl | UART_InitStruct->UART_Mode ;
+    /* Write to UART GCR */
+    UARTx->GCR = tmpreg;
+    /*---------------------------- UART BRR Configuration -----------------------*/
+    /* Configure the UART Baud Rate -------------------------------------------*/
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+    if (UARTxbase == UART1_BASE)
+    {
+
+        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+
+    }
+    else
+    {
+
+        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+    }
+    /* Determine the UART_baud*/
+
+    tmpreg = (apbclock / UART_InitStruct->UART_BaudRate) / 16;
+    tmpreg1 = (apbclock / UART_InitStruct->UART_BaudRate) % 16;
+    UARTx->BRR = tmpreg;
+    UARTx->FRA = tmpreg1;
+}
+
+/**
+* @brief  Fills each UART_InitStruct member with its default value.
+* @param UART_InitStruct: pointer to a UART_InitTypeDef structure
+*   which will be initialized.
+* @retval : None
+*/
+void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
+{
+    /* UART_InitStruct members default value */
+    UART_InitStruct->UART_BaudRate = 9600;
+    UART_InitStruct->UART_WordLength = UART_WordLength_8b;
+    UART_InitStruct->UART_StopBits = UART_StopBits_1;
+    UART_InitStruct->UART_Parity = UART_Parity_No ;
+    UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
+    UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None;
+}
+
+
+/**
+* @brief  Enables or disables the specified UART peripheral.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param NewState: new state of the UARTx peripheral.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the selected UART by setting the uarten bit in the GCR register */
+        UARTx->GCR |= GCR_UE_Set;
+    }
+    else
+    {
+        /* Disable the selected UART by clearing the uarten bit in the GCR register */
+        UARTx->GCR &= GCR_UE_Reset;
+    }
+}
+
+/**
+* @brief  Enables or disables the specified UART interrupts.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param UART_IT: specifies the UART interrupt sources to be
+*   enabled or disabled.
+*   This parameter can be one of the following values:
+*
+* @arg UART_IT_ERR:  Error interrupt(Frame error,)
+* @arg UART_IT_PE:   Parity Error interrupt
+* @arg UART_OVER_ERR:  overrun Error interrupt
+* @arg UART_TIMEOUT_ERR:  timeout Error interrupt
+* @arg UART_IT_RXIEN: Receive Data register interrupt
+* @arg UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+* @param NewState: new state of the specified UARTx interrupts.
+*   This parameter can be: ENABLE or DISABLE.
+* @retval : None
+*/
+void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_CONFIG_IT(UART_IT));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState != DISABLE)
+    {
+        /* Enable the UART_IT interrupt */
+        UARTx->IER  |= UART_IT;
+    }
+    else
+    {
+        /* Disable the UART_IT interrupt */
+        UARTx->IER  &= ~ UART_IT;
+    }
+}
+
+/**
+* @brief  Enables or disables the UART’s DMA interface.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3 .
+* @param UART_DMAReq: specifies the DMA request.
+*   This parameter can be any combination of the following values:
+* @arg UART_DMAReq_EN: UART DMA transmit request
+*
+* @param NewState: new state of the DMA Request sources.
+*   This parameter can be: ENABLE or DISABLE.
+* @note The DMA mode is not available for UART5.
+* @retval : None
+*/
+void UART_DMACmd(UART_TypeDef* UARTx, uint16_t UART_DMAReq, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_1234_PERIPH(UARTx));
+    assert_param(IS_UART_DMAREQ(UART_DMAReq));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    if (NewState != DISABLE)
+    {
+        /* Enable the DMA transfer */
+        UARTx->GCR |= UART_DMAReq;
+    }
+    else
+    {
+        /* Disable the DMA transfer */
+        UARTx->GCR &= ~UART_DMAReq;
+    }
+}
+
+
+/**
+* @brief  Transmits single data through the UARTx peripheral.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param Data: the data to transmit.
+* @retval : None
+*/
+void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_DATA(Data));
+
+    /* Transmit Data */
+    UARTx->TDR = (Data & (uint16_t)0x00FF);
+}
+
+/**
+* @brief  Returns the most recent received data by the UARTx peripheral.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @retval : The received data.
+*/
+uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+
+    /* Receive Data */
+    return (uint16_t)(UARTx->RDR & (uint16_t)0x00FF);
+}
+
+
+/**
+* @brief  Checks whether the specified UART flag is set or not.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param UART_FLAG: specifies the flag to check.
+*   This parameter can be one of the following values:
+* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag
+* @arg UART_FLAG_TXFULL:Transmit data buffer full
+* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag
+* @arg UART_FLAG_OVER:OverRun Error flag
+* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
+* @retval : The new state of UART_FLAG (SET or RESET).
+*/
+FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_FLAG(UART_FLAG));
+    if ((UARTx->CSR & UART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the UARTx's pending flags.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3, UART4 or UART5.
+* @param UART_FLAG: specifies the flag to clear.
+*   This parameter can be any combination of the following values:
+* @arg UART_FLAG_TXEMPTY:Transmit data register empty flag
+* @arg UART_FLAG_TXFULL:Transmit data buffer full
+* @arg UART_FLAG_RXAVL:RX Buffer has a byte flag
+* @arg UART_FLAG_OVER:OverRun Error flag
+* @arg UART_FLAG_TXEPT: tx and shifter are emptys flag
+* @retval : None
+*/
+void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
+{
+
+}
+
+/**
+* @brief  Checks whether the specified UART interrupt has occurred or not.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3.
+* @param UART_IT: specifies the UART interrupt source to check.
+*   This parameter can be one of the following values:
+* @arg UART_IT_ERR:  Error interrupt(Frame error,)
+* @arg UART_IT_PE:   Parity Error interrupt
+* @arg UART_OVER_ERR:  overrun Error interrupt
+* @arg UART_TIMEOUT_ERR:  timeout Error interrupt
+* @arg UART_IT_RXIEN: Receive Data register interrupt
+* @arg UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+* @retval : The new state of UART_IT (SET or RESET).
+*/
+ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
+{
+    FlagStatus bitstatus = RESET;
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_FLAG(UART_FLAG));
+    assert_param(IS_UART_PERIPH_FLAG(UARTx, UART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */
+    if ((UARTx->ISR & UART_IT) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/**
+* @brief  Clears the UARTx’s interrupt pending bits.
+* @param UARTx: Select the UART or the UART peripheral.
+*   This parameter can be one of the following values:
+*   UART1, UART2, UART3, UART4 or UART5.
+* @param UART_IT: specifies the interrupt pending bit to clear.
+*   This parameter can be one of the following values:
+* @arg UART_IT_ERR:  Error interrupt(Frame error,)
+* @arg UART_IT_PE:   Parity Error interrupt
+* @arg UART_OVER_ERR:  overrun Error interrupt
+* @arg UART_TIMEOUT_ERR:  timeout Error interrupt
+* @arg UART_IT_RXIEN: Receive Data register interrupt
+* @arg UART_IT_TXIEN:  Tansmit Data Register empty interrupt
+
+* @retval : None
+*/
+void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
+{
+
+    /* Check the parameters */
+    assert_param(IS_UART_ALL_PERIPH(UARTx));
+    assert_param(IS_UART_CLEAR_IT(UART_IT));
+    assert_param(IS_UART_PERIPH_IT(UARTx, UART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */
+    /*clear UART_IT pendings bit*/
+    UARTx->ICR = UART_IT;
+}
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/HAL_lib/src/HAL_wwdg.c

@@ -0,0 +1,221 @@
+/**
+******************************************************************************
+* @file    HAL_wwdg.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file provides all the WWDG firmware functions.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT,MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "HAL_wwdg.h"
+#include "HAL_rcc.h"
+
+/** @addtogroup StdPeriph_Driver
+* @{
+*/
+
+/** @defgroup WWDG
+* @brief WWDG driver modules
+* @{
+*/
+
+/** @defgroup WWDG_Private_TypesDefinitions
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Private_Defines
+* @{
+*/
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_WDGA_Set       ((uint32_t)0x00000080)
+
+/* CFR register bit mask */
+#define CFR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask          ((uint8_t)0x7F)
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Private_Macros
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Private_Variables
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Private_FunctionPrototypes
+* @{
+*/
+
+/**
+* @}
+*/
+
+/** @defgroup WWDG_Private_Functions
+* @{
+*/
+
+/**
+* @brief  Deinitializes the WWDG  peripheral registers to their default
+*   reset values.
+* @param  None
+* @retval : None
+*/
+void WWDG_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+* @brief  Sets the WWDG Prescaler.
+* @param WWDG_Prescaler: specifies the WWDG Prescaler.
+*   This parameter can be one of the following values:
+* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+* @retval : None
+*/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+    /* Clear WDGTB[1:0] bits */
+    tmpreg = WWDG->CFR & CFR_WDGTB_Mask;
+    /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+    tmpreg |= WWDG_Prescaler;
+    /* Store the new value */
+    WWDG->CFR = tmpreg;
+}
+
+/**
+* @brief  Sets the WWDG window value.
+* @param WindowValue: specifies the window value to be compared to
+*   the downcounter.
+*   This parameter value must be lower than 0x80.
+* @retval : None
+*/
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+    uint32_t tmpreg = 0;
+    /* Check the parameters */
+    assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+    /* Clear W[6:0] bits */
+    tmpreg = WWDG->CFR & CFR_W_Mask;
+    /* Set W[6:0] bits according to WindowValue value */
+    tmpreg |= WindowValue & BIT_Mask;
+    /* Store the new value */
+    WWDG->CFR = tmpreg;
+}
+
+/**
+* @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+* @param  None
+* @retval : None
+*/
+void WWDG_EnableIT(void)
+{
+    WWDG->CFR |= (uint32_t)0x200;
+}
+
+/**
+* @brief  Sets the WWDG counter value.
+* @param Counter: specifies the watchdog counter value.
+*   This parameter must be a number between 0x40 and 0x7F.
+* @retval : None
+*/
+void WWDG_SetCounter(uint8_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IS_WWDG_COUNTER(Counter));
+    /* Write to T[6:0] bits to configure the counter value, no need to do
+    a read-modify-write; writing a 0 to WDGA bit does nothing */
+    WWDG->CR = Counter & BIT_Mask;
+}
+
+/**
+* @brief  Enables WWDG and load the counter value.
+* @param Counter: specifies the watchdog counter value.
+*   This parameter must be a number between 0x40 and 0x7F.
+* @retval : None
+*/
+void WWDG_Enable(uint8_t Counter)
+{
+    /* Check the parameters */
+    assert_param(IS_WWDG_COUNTER(Counter));
+    WWDG->CR = CR_WDGA_Set | Counter;
+}
+
+/**
+* @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+* @param  None
+* @retval : The new state of the Early Wakeup interrupt flag (SET or RESET)
+*/
+FlagStatus WWDG_GetFlagStatus(void)
+{
+    return (FlagStatus)(WWDG->SR);
+}
+
+/**
+* @brief  Clears Early Wakeup interrupt flag.
+* @param  None
+* @retval : None
+*/
+void WWDG_ClearFlag(void)
+{
+    WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/Include/HAL_device.h

@@ -0,0 +1,37 @@
+/**
+******************************************************************************
+* @file    HAL_device.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   This file contains all the Device inc file for the library.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+
+#ifndef __HAL_device_H
+#define __HAL_device_H
+
+
+#define MM32F103
+
+#if defined(MM32F103)
+#include "MM32F103.h"
+#include "SYSTEM_MM32F103.h"
+#else
+#error "HAL_device.h: PART NUMBER undefined"
+#endif
+#endif /* __HAL_device_H */
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/
+

bsp/mm32f103x/Libraries/MM32F103/Include/MM32F103.h

@@ -0,0 +1,4404 @@
+/**
+******************************************************************************
+* @file    MM32F103.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+*          This file contains all the peripheral register's definitions, bits
+*          definitions and memory mapping for MM32F103 High Density, Medium
+*          Density and Low Density devices.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+/** @addtogroup CMSIS
+* @{
+*/
+
+/** @addtogroup MM32F103
+* @{
+*/
+
+#ifndef __MM32F103_H
+#define __MM32F103_H
+
+/** @addtogroup Library_configuration_section
+* @{
+*/
+
+
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+* @brief Comment the line below if you will not use the peripherals drivers.
+In this case, these drivers will not be included and the application code will
+be based on direct access to peripherals registers
+*/
+/*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+* @brief In the following line adjust the value of External High Speed oscillator (HSE)
+used in your application
+*/
+#define HSE_Value    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#define HSE_VALUE    HSE_Value
+/**
+* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+Timeout value
+*/
+#define HSEStartUp_TimeOut   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#define HSE_STARTUP_TIMEOUT   HSEStartUp_TimeOut
+
+#define HSI_Value_Pll_ON    ((uint32_t)48000000/4) /*!< Value of the Internal oscillator in Hz*/
+#define HSI_VALUE_PLL_ON   HSI_Value_Pll_ON
+
+#define HSI_Value_Pll_OFF    ((uint32_t)48000000/6) /*!< Value of the Internal oscillator in Hz*/
+#define HSI_VALUE_PLL_OFF   HSI_Value_Pll_OFF
+
+/*!< [31:16] MM32F103 Standard Peripheral Library main version */
+#define __MM32F103_STDPERIPH_VERSION_MAIN   (0x01)
+/*!< [15:8]  MM32F103 Standard Peripheral Library sub1 version */
+#define __MM32F103_STDPERIPH_VERSION_SUB1   (0x00)
+/*!< [7:0]  MM32F103 Standard Peripheral Library sub2 version */
+#define __MM32F103_STDPERIPH_VERSION_SUB2   (0x00)
+/*!< MM32F103 Standard Peripheral Library version number */
+#define __MM32F103_STDPERIPH_VERSION       ((__MM32F103_STDPERIPH_VERSION_MAIN << 16)\
+        | (__MM32F103_STDPERIPH_VERSION_SUB1 << 8)\
+        | __MM32F103_STDPERIPH_VERSION_SUB2)
+
+/**
+* @}
+*/
+
+/** @addtogroup Configuration_section_for_CMSIS
+* @{
+*/
+
+/**
+* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+*/
+#define __MPU_PRESENT             0 /*!< MM32F103 does not provide a MPU present or not  */
+#define __NVIC_PRIO_BITS          4 /*!< MM32F103 uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+    /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
+    MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
+    BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
+    UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
+    SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
+    DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+    PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+    SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+    /******  MM32F103 CM3 specific Interrupt Numbers *********************************************************/
+
+    WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
+    PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
+    TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
+    RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
+    FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
+    RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
+    EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
+    DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
+    DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
+    DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
+    DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
+    DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
+    DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
+    DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
+    ADC1_2_IRQn                 = 18,     /*!< ADC1 et ADC2 global Interrupt                        */
+    USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB High Priority or CAN1 TX Interrupts              */
+
+    CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
+
+    EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
+    TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
+    TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
+    TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
+    TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
+    TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
+    TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
+    TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
+    I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
+
+    I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
+
+    SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
+    SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
+    UART1_IRQn                 = 37,     /*!< UART1 global Interrupt                              */
+    UART2_IRQn                 = 38,     /*!< UART2 global Interrupt                              */
+    UART3_IRQn                 = 39,     /*!< UART3 global Interrupt                              */
+    EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn               = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn              = 42,     /*!< USB WakeUp from suspend through EXTI Line Interrupt  */
+
+
+} IRQn_Type;
+
+
+
+
+/**
+* @}
+*/
+
+#include <core_cm3.h>
+
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+* @{
+*/
+
+/*!< MM32F103 Standard Peripheral Library old types (maintained for legacy prupose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {FALSE = 0, TRUE = !FALSE} bool;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+* @}
+*/
+
+typedef struct
+{
+    __IO uint32_t     SHCSR;  //0XE000DE24
+    __IO uint8_t      MFSR;   //0XE000DE28
+    __IO uint8_t      BFSR;   //0XE000DE29
+    __IO uint16_t     UFSR;   //0XE000DE2A
+    __IO uint32_t     HFSR;   //0XE000DE2C
+    __IO uint32_t     DFSR;   //0XE000DE30
+    __IO uint32_t     MMAR;   //0XE000DE34
+    __IO uint32_t     BFAR;   //0XE000DE38
+} HARD_FAULT_TypeDef;
+
+
+/** @addtogroup Peripheral_registers_structures
+* @{
+*/
+
+/**
+* @brief Analog to Digital Converter
+*/
+
+typedef struct
+{
+    __IO uint32_t ADDATA;
+    __IO uint32_t ADCFG;
+    __IO uint32_t ADCR;
+    __IO uint32_t ADCHS;
+    __IO uint32_t ADCMPR;
+    __IO uint32_t ADSTA;
+    __IO uint32_t ADDR0;
+    __IO uint32_t ADDR1;
+    __IO uint32_t ADDR2;
+    __IO uint32_t ADDR3;
+    __IO uint32_t ADDR4;
+    __IO uint32_t ADDR5;
+    __IO uint32_t ADDR6;
+    __IO uint32_t ADDR7;
+    __IO uint32_t ADDR8;
+} ADC_TypeDef;
+
+/**
+* @brief Backup Registers
+*/
+
+typedef struct
+{
+    uint32_t  RESERVED0;
+    __IO uint16_t DR1;
+    uint16_t  RESERVED1;
+    __IO uint16_t DR2;
+    uint16_t  RESERVED2;
+    __IO uint16_t DR3;
+    uint16_t  RESERVED3;
+    __IO uint16_t DR4;
+    uint16_t  RESERVED4;
+    __IO uint16_t DR5;
+    uint16_t  RESERVED5;
+    __IO uint16_t DR6;
+    uint16_t  RESERVED6;
+    __IO uint16_t DR7;
+    uint16_t  RESERVED7;
+    __IO uint16_t DR8;
+    uint16_t  RESERVED8;
+    __IO uint16_t DR9;
+    uint16_t  RESERVED9;
+    __IO uint16_t DR10;
+    uint16_t  RESERVED10;
+    __IO uint16_t RTCCR;
+    uint16_t  RESERVED11;
+    __IO uint16_t CR;
+    uint16_t  RESERVED12;
+    __IO uint16_t CSR;
+} BKP_TypeDef;
+
+/**
+* @brief CAN basic
+*/
+typedef struct
+{
+    __IO uint32_t CR;			//0x00
+    __IO uint32_t CMR;			//0x04
+    __IO uint32_t SR;			//0x08
+    __IO uint32_t IR;			//0x0c
+    __IO uint32_t ACR;			//0x10
+    __IO uint32_t AMR;			//0x14
+    __IO uint32_t BTR0;		//0x18
+    __IO uint32_t BTR1;		//0x1C
+    __IO uint32_t  RESERVED0;	//0x20
+    uint32_t RESERVED1; 		//0x24
+    __IO uint32_t TXID0;		//0x28
+    __IO uint32_t TXID1;		//0x2c
+    __IO uint32_t TXDR0;		//0x30
+    __IO uint32_t TXDR1;		//0x34
+    __IO uint32_t TXDR2;		//0x38
+    __IO uint32_t TXDR3;		//0x3c
+    __IO uint32_t TXDR4;		//0x40
+    __IO uint32_t TXDR5;		//0x44
+    __IO uint32_t TXDR6;		//0x48
+    __IO uint32_t TXDR7;		//0x4c
+    __IO uint32_t RXID0;		//0x50
+    __IO uint32_t RXID1;		//0x54
+    __IO uint32_t RXDR0;		//0x58
+    __IO uint32_t RXDR1;		//0x5C
+    __IO uint32_t RXDR2;		//0x60
+    __IO uint32_t RXDR3;
+    __IO uint32_t RXDR4;
+    __IO uint32_t RXDR5;		//0x6c
+    __IO uint32_t RXDR6;		//0x70
+    __IO uint32_t RXDR7;		//0x74
+    uint32_t RESERVED2;
+    __IO uint32_t CDR;			//0x7c
+} CAN_TypeDef;
+
+/**
+* @brief CAN Peli
+*/
+typedef struct
+{
+    __IO uint32_t MOD;
+    __IO uint32_t CMR;
+    __IO uint32_t SR;
+    __IO uint32_t IR;
+    __IO uint32_t IER;		//0x10h
+    uint32_t RESERVED0;
+    __IO uint32_t BTR0;
+    __IO uint32_t BTR1;
+    uint32_t RESERVED1;	//0x20h
+    uint32_t RESERVED2;
+    uint32_t RESERVED3;
+    __IO uint32_t ALC;
+    __IO uint32_t ECC;		//0x30h
+    __IO uint32_t EWLR;
+    __IO uint32_t RXERR;
+    __IO uint32_t TXERR;
+    __IO uint32_t FF;		//0x40
+    __IO uint32_t ID0;
+    __IO uint32_t ID1;
+    __IO uint32_t DATA0;
+    __IO uint32_t DATA1;	//0x50
+    __IO uint32_t DATA2;
+    __IO uint32_t DATA3;
+    __IO uint32_t DATA4;
+    __IO uint32_t DATA5;	//0x60
+    __IO uint32_t DATA6;
+    __IO uint32_t DATA7;
+    __IO uint32_t DATA8;
+    __IO uint32_t DATA9;	//0x70
+    __IO uint32_t RMC;
+    __IO uint32_t RBSA;
+    __IO uint32_t CDR;
+} CAN_Peli_TypeDef;
+
+
+/**
+* @brief CRC calculation unit
+*/
+
+typedef struct
+{
+    __IO uint32_t DR;
+    __IO uint8_t  IDR;
+    uint8_t   RESERVED0;
+    uint16_t  RESERVED1;
+    __IO uint32_t CR;
+} CRC_TypeDef;
+
+/**
+* @brief Digital to Analog Converter
+*/
+
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t SWTRIGR;
+    __IO uint32_t DHR12R1;
+    __IO uint32_t DHR12L1;
+    __IO uint32_t DHR8R1;
+    __IO uint32_t DHR12R2;
+    __IO uint32_t DHR12L2;
+    __IO uint32_t DHR8R2;
+    __IO uint32_t DHR12RD;
+    __IO uint32_t DHR12LD;
+    __IO uint32_t DHR8RD;
+    __IO uint32_t DOR1;
+    __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+
+/**
+* @brief Debug MCU
+*/
+
+typedef struct
+{
+    __IO uint32_t IDCODE;
+    __IO uint32_t CR;
+} DBGMCU_TypeDef;
+
+/**
+* @brief DMA Controller
+*/
+
+typedef struct
+{
+    __IO uint32_t CCR;
+    __IO uint32_t CNDTR;
+    __IO uint32_t CPAR;
+    __IO uint32_t CMAR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t ISR;
+    __IO uint32_t IFCR;
+} DMA_TypeDef;
+
+/**
+* @brief External Interrupt/Event Controller
+*/
+
+typedef struct
+{
+    __IO uint32_t IMR;
+    __IO uint32_t EMR;
+    __IO uint32_t RTSR;
+    __IO uint32_t FTSR;
+    __IO uint32_t SWIER;
+    __IO uint32_t PR;
+} EXTI_TypeDef;
+
+/**
+* @brief FLASH Registers
+*/
+
+typedef struct
+{
+    __IO uint32_t ACR;
+    __IO uint32_t KEYR;
+    __IO uint32_t OPTKEYR;
+    __IO uint32_t SR;
+    __IO uint32_t CR;
+    __IO uint32_t AR;
+    __IO uint32_t RESERVED;
+    __IO uint32_t OBR;
+    __IO uint32_t WRPR;
+} FLASH_TypeDef;
+
+/**
+* @brief Option Bytes Registers
+*/
+
+typedef struct
+{
+    __IO uint16_t RDP;
+    __IO uint16_t USER;
+    __IO uint16_t Data0;
+    __IO uint16_t Data1;
+    __IO uint16_t WRP0;
+    __IO uint16_t WRP1;
+    __IO uint16_t WRP2;
+    __IO uint16_t WRP3;
+} OB_TypeDef;
+
+
+
+/**
+* @brief General Purpose IO
+*/
+
+typedef struct
+{
+    __IO uint32_t CRL;
+    __IO uint32_t CRH;
+    __IO uint32_t IDR;
+    __IO uint32_t ODR;
+    __IO uint32_t BSRR;
+    __IO uint32_t BRR;
+    __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/**
+* @brief Alternate Function IO
+*/
+
+typedef struct
+{
+    __IO uint32_t EVCR;
+    __IO uint32_t MAPR;
+    __IO uint32_t EXTICR[4];
+} AFIO_TypeDef;
+/**
+* @brief Inter-integrated Circuit Interface
+*/
+
+typedef struct
+{
+    __IO uint16_t IC_CON;
+    uint16_t  RESERVED0;
+    __IO uint16_t IC_TAR;
+    uint16_t  RESERVED1;
+    __IO uint16_t IC_SAR;
+    uint16_t  RESERVED2;
+    __IO uint16_t IC_HS_MADDR;
+    uint16_t  RESERVED3;
+    __IO uint16_t IC_DATA_CMD;
+    uint16_t  RESERVED4;
+    __IO uint16_t IC_SS_SCL_HCNT;
+    uint16_t  RESERVED5;
+    __IO uint16_t IC_SS_SCL_LCNT;
+    uint16_t  RESERVED6;
+    __IO uint16_t IC_FS_SCL_HCNT;
+    uint16_t  RESERVED7;
+    __IO uint16_t IC_FS_SCL_LCNT;
+    uint16_t  RESERVED8;
+    __IO uint16_t IC_HS_SCL_HCNT;
+    uint16_t  RESERVED9;
+    __IO uint16_t IC_HS_SCL_LCNT;
+    uint16_t  RESERVED10;
+    __IO uint16_t IC_INTR_STAT;
+    uint16_t  RESERVED11;
+    __IO uint16_t IC_INTR_MASK;
+    uint16_t  RESERVED12;
+    __IO uint16_t IC_RAW_INTR_STAT;
+    uint16_t  RESERVED13;
+    __IO uint16_t IC_RX_TL;
+    uint16_t  RESERVED14;
+    __IO uint16_t IC_TX_TL;
+    uint16_t  RESERVED15;
+    __IO uint16_t IC_CLR_INTR;
+    uint16_t  RESERVED16;
+    __IO uint16_t IC_CLR_RX_UNDER;
+    uint16_t  RESERVED17;
+    __IO uint16_t IC_CLR_RX_OVER;
+    uint16_t  RESERVED18;
+    __IO uint16_t IC_CLR_TX_OVER;
+    uint16_t  RESERVED19;
+    __IO uint16_t IC_CLR_RD_REQ;
+    uint16_t  RESERVED20;
+    __IO uint16_t IC_CLR_TX_ABRT;
+    uint16_t  RESERVED21;
+    __IO uint16_t IC_CLR_RX_DONE;
+    uint16_t  RESERVED22;
+    __IO uint16_t IC_CLR_ACTIVITY;
+    uint16_t  RESERVED23;
+    __IO uint16_t IC_CLR_STOP_DET;
+    uint16_t  RESERVED24;
+    __IO uint16_t IC_CLR_START_DET;
+    uint16_t  RESERVED25;
+    __IO uint16_t IC_CLR_GEN_CALL;
+    uint16_t  RESERVED26;
+    __IO uint16_t IC_ENABLE;               //RESERVED
+    uint16_t  RESERVED27;
+
+    __IO uint32_t IC_STATUS;
+    __IO uint32_t IC_TXFLR;                //RESERVED
+    __IO uint32_t IC_RXFLR;                //RESERVED
+    __IO uint32_t IC_SDA_HOLD;             //RESERVED
+    __IO uint32_t IC_TX_ABRT_SOURCE;       //RESERVED
+    __IO uint32_t IC_SLV_DATA_NACK_ONLY;   //RESERVED
+    __IO uint32_t IC_DMA_CR;               //RESERVED
+    __IO uint32_t IC_DMA_TDLR;             //RESERVED
+    __IO uint32_t IC_DMA_RDLR;             //RESERVED
+    __IO uint32_t IC_SDA_SETUP;            //RESERVED
+    __IO uint32_t IC_ACK_GENERAL_CALL;     //RESERVED
+
+    __IO uint32_t IC_FS_SPKLEN;
+    __IO uint32_t IC_HS_SPKLEN;
+
+    __IO uint16_t IC_CLR_RESTART_DET;
+    uint16_t  RESERVED28;
+    __IO uint32_t IC_COMP_PARAM_1;
+    __IO uint32_t IC_COMP_VERSION;
+    __IO uint32_t IC_COMP_TYPE;
+
+} I2C_TypeDef;
+
+/**
+* @brief Independent WATCHDOG
+*/
+
+typedef struct
+{
+    __IO uint32_t KR;
+    __IO uint32_t PR;
+    __IO uint32_t RLR;
+    __IO uint32_t SR;
+} IWDG_TypeDef;
+
+/**
+* @brief Power Control
+*/
+
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/**
+* @brief Reset and Clock Control
+*/
+
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t CFGR;
+    __IO uint32_t CIR;
+    __IO uint32_t APB2RSTR;
+    __IO uint32_t APB1RSTR;
+    __IO uint32_t AHBENR;
+    __IO uint32_t APB2ENR;
+    __IO uint32_t APB1ENR;
+    __IO uint32_t BDCR;
+    __IO uint32_t CSR;
+} RCC_TypeDef;
+
+/**
+* @brief Real-Time Clock
+*/
+
+typedef struct
+{
+    __IO uint16_t CRH;
+    uint16_t  RESERVED0;
+    __IO uint16_t CRL;
+    uint16_t  RESERVED1;
+    __IO uint16_t PRLH;
+    uint16_t  RESERVED2;
+    __IO uint16_t PRLL;
+    uint16_t  RESERVED3;
+    __IO uint16_t DIVH;
+    uint16_t  RESERVED4;
+    __IO uint16_t DIVL;
+    uint16_t  RESERVED5;
+    __IO uint16_t CNTH;
+    uint16_t  RESERVED6;
+    __IO uint16_t CNTL;
+    uint16_t  RESERVED7;
+    __IO uint16_t ALRH;
+    uint16_t  RESERVED8;
+    __IO uint16_t ALRL;
+    uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+
+/**
+* @brief Serial Peripheral Interface
+*/
+
+
+typedef struct
+{
+    __IO uint32_t TXREG;
+    __IO uint32_t RXREG;
+    __IO uint16_t CSTAT;
+    uint16_t  RESERVED0;
+    __IO uint16_t INTSTAT;
+    uint16_t  RESERVED1;
+    __IO uint16_t INTEN;
+    uint16_t  RESERVED2;
+    __IO uint16_t INTCLR;
+    uint16_t  RESERVED3;
+    __IO uint16_t GCTL;
+    uint16_t  RESERVED4;
+    __IO uint16_t CCTL;
+    uint16_t  RESERVED5;
+    __IO uint16_t SPBRG;
+    uint16_t  RESERVED6;
+    __IO uint16_t RXDNR;
+    uint16_t  RESERVED7;
+    __IO uint16_t SCSR;
+    uint16_t  RESERVED8;
+    __IO uint16_t EXTCTL;
+    uint16_t  RESERVED9;
+} SPI_TypeDef;
+
+
+
+
+/**
+* @brief TIM
+*/
+
+typedef struct
+{
+    __IO uint16_t CR1;
+    uint16_t  RESERVED0;
+    __IO uint16_t CR2;
+    uint16_t  RESERVED1;
+    __IO uint16_t SMCR;
+    uint16_t  RESERVED2;
+    __IO uint16_t DIER;
+    uint16_t  RESERVED3;
+    __IO uint16_t SR;
+    uint16_t  RESERVED4;
+    __IO uint16_t EGR;
+    uint16_t  RESERVED5;
+    __IO uint16_t CCMR1;
+    uint16_t  RESERVED6;
+    __IO uint16_t CCMR2;
+    uint16_t  RESERVED7;
+    __IO uint16_t CCER;
+    uint16_t  RESERVED8;
+    __IO uint16_t CNT;
+    uint16_t  RESERVED9;
+    __IO uint16_t PSC;
+    uint16_t  RESERVED10;
+    __IO uint16_t ARR;
+    uint16_t  RESERVED11;
+    __IO uint16_t RCR;
+    uint16_t  RESERVED12;
+    __IO uint16_t CCR1;
+    uint16_t  RESERVED13;
+    __IO uint16_t CCR2;
+    uint16_t  RESERVED14;
+    __IO uint16_t CCR3;
+    uint16_t  RESERVED15;
+    __IO uint16_t CCR4;
+    uint16_t  RESERVED16;
+    __IO uint16_t BDTR;
+    uint16_t  RESERVED17;
+    __IO uint16_t DCR;
+    uint16_t  RESERVED18;
+    __IO uint16_t DMAR;
+    uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/**
+* @brief Universal Synchronous Asynchronous Receiver Transmitter
+*/
+
+typedef struct
+{
+    __IO uint32_t TDR;
+    __IO uint32_t RDR;
+    __IO uint32_t CSR;
+    __IO uint32_t ISR;
+    __IO uint32_t IER;
+    __IO uint32_t ICR;
+    __IO uint32_t GCR;
+    __IO uint32_t CCR;
+    __IO uint32_t BRR;
+    __IO uint32_t FRA;
+
+} UART_TypeDef;
+
+/**
+* @brief Window WATCHDOG
+*/
+
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t CFR;
+    __IO uint32_t SR;
+} WWDG_TypeDef;
+
+
+/**
+* @brief USB
+*/
+typedef struct
+{
+    __IO uint32_t  rTOP;        		/*!           Address offset: 0x00 */
+    __IO uint32_t  rINT_STATE;        	/*!           Address offset: 0x04 */
+    __IO uint32_t  rEP_INT_STATE;  		/*!           Address offset: 0x08 */
+    __IO uint32_t  rEP0_INT_STATE; 		/*!           Address offset: 0x0C */
+    __IO uint32_t  rINT_EN;        		/*!           Address offset: 0x10 */
+    __IO uint32_t  rEP_INT_EN;        	/*!           Address offset: 0x14 */
+    __IO uint32_t  rEP0_INT_EN;      	/*!           Address offset: 0x18 */
+
+    __IO uint32_t  RESERVED0;
+
+    //__IO uint32_t  rEP1_4_INT_STATE[4];      /*!           Address offset: 0x20 */
+
+    __IO uint32_t  rEP1_INT_STATE;      /*!           Address offset: 0x20 */
+    __IO uint32_t  rEP2_INT_STATE;      /*!           Address offset: 0x24 */
+    __IO uint32_t  rEP3_INT_STATE;      /*!           Address offset: 0x28 */
+    __IO uint32_t  rEP4_INT_STATE;      /*!           Address offset: 0x2C */
+
+    __IO uint32_t  RESERVED1; 			/*!           Address offset: 0x30 */
+    __IO uint32_t  RESERVED2; 			/*!           Address offset: 0x34 */
+    __IO uint32_t  RESERVED3; 			/*!           Address offset: 0x38 */
+    __IO uint32_t  RESERVED4; 			/*!           Address offset: 0x3C */
+
+    __IO uint32_t  rEP1_INT_EN;        	/*!           Address offset: 0x40 */
+    __IO uint32_t  rEP2_INT_EN;        	/*!           Address offset: 0x44 */
+    __IO uint32_t  rEP3_INT_EN;        	/*!           Address offset: 0x48 */
+    __IO uint32_t  rEP4_INT_EN;        	/*!           Address offset: 0x4C */
+
+    __IO uint32_t  RESERVED5; 			/*!           Address offset: 0x50 */
+    __IO uint32_t  RESERVED6; 			/*!           Address offset: 0x54 */
+    __IO uint32_t  RESERVED7; 			/*!           Address offset: 0x58 */
+    __IO uint32_t  RESERVED8; 			/*!           Address offset: 0x5C */
+
+    __IO uint32_t  rADDR;        		/*!           Address offset: 0x60 */
+    __IO uint32_t  rEP_EN;        		/*!           Address offset: 0x64 */
+
+    __IO uint32_t  RESERVED9; 			/*!           Address offset: 0x68 */
+    __IO uint32_t  RESERVED10; 			/*!           Address offset: 0x6C */
+    __IO uint32_t  RESERVED11; 			/*!           Address offset: 0x70 */
+    __IO uint32_t  RESERVED12; 			/*!           Address offset: 0x74 */
+
+    __IO uint32_t  rTOG_CTRL1_4;        /*!           Address offset: 0x78 */
+
+    __IO uint32_t  RESERVED13; 			/*!           Address offset: 0x7C */
+
+    __IO uint32_t  rSETUP[8];        		/*!           Address offset: 0x80 */
+    //__IO uint32_t  rSETUP0;        		/*!           Address offset: 0x80 */
+    //__IO uint32_t  rSETUP1;        		/*!           Address offset: 0x84 */
+    //__IO uint32_t  rSETUP2;        		/*!           Address offset: 0x88 */
+    //__IO uint32_t  rSETUP3;        		/*!           Address offset: 0x8C */
+    //__IO uint32_t  rSETUP4;        		/*!           Address offset: 0x90 */
+    //__IO uint32_t  rSETUP5;        		/*!           Address offset: 0x94 */
+    //__IO uint32_t  rSETUP6;        		/*!           Address offset: 0x98 */
+    //__IO uint32_t  rSETUP7;        		/*!           Address offset: 0x9C */
+    __IO uint32_t  rPAKET_SIZE0;    	/*!           Address offset: 0xA0 */
+    __IO uint32_t  rPAKET_SIZE1;    	/*!           Address offset: 0xA4 */
+
+    __IO uint32_t  RESERVED14; 			/*!           Address offset: 0xA8 */
+    __IO uint32_t  RESERVED15; 			/*!           Address offset: 0xAC */
+
+    __IO uint32_t  RESERVED16; 			/*!           Address offset: 0xB0 */
+    __IO uint32_t  RESERVED17; 			/*!           Address offset: 0xB4 */
+    __IO uint32_t  RESERVED18; 			/*!           Address offset: 0xB8 */
+    __IO uint32_t  RESERVED19; 			/*!           Address offset: 0xBC */
+
+    __IO uint32_t  RESERVED20; 			/*!           Address offset: 0xC0 */
+    __IO uint32_t  RESERVED21; 			/*!           Address offset: 0xC4 */
+    __IO uint32_t  RESERVED22; 			/*!           Address offset: 0xC8 */
+    __IO uint32_t  RESERVED23; 			/*!           Address offset: 0xCC */
+
+    __IO uint32_t  RESERVED24; 			/*!           Address offset: 0xD0 */
+    __IO uint32_t  RESERVED25; 			/*!           Address offset: 0xD4 */
+    __IO uint32_t  RESERVED26; 			/*!           Address offset: 0xD8 */
+    __IO uint32_t  RESERVED27; 			/*!           Address offset: 0xDC */
+
+    __IO uint32_t  RESERVED28; 			/*!           Address offset: 0xE0 */
+    __IO uint32_t  RESERVED29; 			/*!           Address offset: 0xE4 */
+    __IO uint32_t  RESERVED30; 			/*!           Address offset: 0xE8 */
+    __IO uint32_t  RESERVED31; 			/*!           Address offset: 0xEC */
+
+    __IO uint32_t  RESERVED32; 			/*!           Address offset: 0xF0 */
+    __IO uint32_t  RESERVED33; 			/*!           Address offset: 0xF4 */
+    __IO uint32_t  RESERVED34; 			/*!           Address offset: 0xF8 */
+    __IO uint32_t  RESERVED35; 			/*!           Address offset: 0xFC */
+
+    __IO uint32_t  rEP0_AVIL;		 	/*!           Address offset: 0x100 */
+    __IO uint32_t  rEP1_AVIL;			/*!           Address offset: 0x104 */
+    __IO uint32_t  rEP2_AVIL;			/*!           Address offset: 0x108 */
+    __IO uint32_t  rEP3_AVIL;			/*!           Address offset: 0x10C */
+    __IO uint32_t  rEP4_AVIL;			/*!           Address offset: 0x110 */
+
+    __IO uint32_t  RESERVED36; 			/*!           Address offset: 0x114 */
+    __IO uint32_t  RESERVED37; 			/*!           Address offset: 0x118 */
+    __IO uint32_t  RESERVED38; 			/*!           Address offset: 0x11C */
+    __IO uint32_t  RESERVED39; 			/*!           Address offset: 0x120 */
+
+    __IO uint32_t  RESERVED40; 			/*!           Address offset: 0x124 */
+    __IO uint32_t  RESERVED41; 			/*!           Address offset: 0x128 */
+    __IO uint32_t  RESERVED42; 			/*!           Address offset: 0x12C */
+    __IO uint32_t  RESERVED43; 			/*!           Address offset: 0x130 */
+
+    __IO uint32_t  RESERVED44; 			/*!           Address offset: 0x134 */
+    __IO uint32_t  RESERVED45; 			/*!           Address offset: 0x138 */
+    __IO uint32_t  RESERVED46; 			/*!           Address offset: 0x13C */
+
+    __IO uint32_t  rEP0_CTRL;			/*!           Address offset: 0x140 */
+    __IO uint32_t  rEP1_CTRL;			/*!           Address offset: 0x144 */
+    __IO uint32_t  rEP2_CTRL;			/*!           Address offset: 0x148 */
+    __IO uint32_t  rEP3_CTRL;			/*!           Address offset: 0x14C */
+    __IO uint32_t  rEP4_CTRL;			/*!           Address offset: 0x150 */
+
+    __IO uint32_t  RESERVED47; 			/*!           Address offset: 0x154 */
+    __IO uint32_t  RESERVED48; 			/*!           Address offset: 0x158 */
+    __IO uint32_t  RESERVED49; 			/*!           Address offset: 0x15C */
+    //__IO uint32_t  RESERVED50; 			/*!           Address offset: 0x15C */
+
+    //__IO uint32_t  rEPn_FIFO[5];			/*!           Address offset: 0x160 */
+
+    __IO uint32_t  rEP0_FIFO;			/*!           Address offset: 0x160 */
+    __IO uint32_t  rEP1_FIFO;			/*!           Address offset: 0x164 */
+    __IO uint32_t  rEP2_FIFO;			/*!           Address offset: 0x168 */
+    __IO uint32_t  rEP3_FIFO;			/*!           Address offset: 0x16C */
+    __IO uint32_t  rEP4_FIFO;			/*!           Address offset: 0x170 */
+
+    __IO uint32_t  RESERVED51; 			/*!           Address offset: 0x174 */
+    __IO uint32_t  RESERVED52; 			/*!           Address offset: 0x178 */
+    __IO uint32_t  RESERVED53; 			/*!           Address offset: 0x17C */
+
+    __IO uint32_t  RESERVED54; 			/*!           Address offset: 0x180 */
+
+    __IO uint32_t  rEP_DMA;				/*!           Address offset: 0x184 */
+    __IO uint32_t  rEP_HALT;			/*!           Address offset: 0x188 */
+    __IO uint32_t  RESERVED55; 			/*!           Address offset: 0x18C */
+
+    __IO uint32_t  RESERVED56; 			/*!           Address offset: 0x190 */
+    __IO uint32_t  RESERVED57; 			/*!           Address offset: 0x194 */
+    __IO uint32_t  RESERVED58; 			/*!           Address offset: 0x198 */
+    __IO uint32_t  RESERVED59; 			/*!           Address offset: 0x19C */
+
+    __IO uint32_t  RESERVED60; 			/*!           Address offset: 0x1A0 */
+    __IO uint32_t  RESERVED61; 			/*!           Address offset: 0x1A4 */
+    __IO uint32_t  RESERVED62; 			/*!           Address offset: 0x1A8 */
+    __IO uint32_t  RESERVED63; 			/*!           Address offset: 0x1AC */
+
+    __IO uint32_t  RESERVED64; 			/*!           Address offset: 0x1B0 */
+    __IO uint32_t  RESERVED65; 			/*!           Address offset: 0x1B4 */
+    __IO uint32_t  RESERVED66; 			/*!           Address offset: 0x1B8 */
+    __IO uint32_t  RESERVED67; 			/*!           Address offset: 0x1BC */
+    __IO uint32_t  rPOWER;				/*!           Address offset: 0x1C0 */
+} USB_TypeDef;
+
+/**
+* @}
+*/
+
+#define HARD_FAULT_MM         ((HARD_FAULT_TypeDef*)0xE000DE24)
+
+/** @addtogroup Peripheral_memory_map
+* @{
+*/
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
+
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
+
+
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+
+#define UART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define UART3_BASE           (APB1PERIPH_BASE + 0x4800)
+
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800) //RESERVED
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00) //RESERVED
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000) //RESERVED
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+
+#define UART1_BASE           (APB2PERIPH_BASE + 0x3800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+
+
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
+
+
+#define DBGMCU_BASE           ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+#define USB_BASE          	  ((uint32_t)0x40005C00)
+
+/**
+* @}
+*/
+
+/** @addtogroup Peripheral_declaration
+* @{
+*/
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define UART2              ((UART_TypeDef *) UART2_BASE)
+#define UART3              ((UART_TypeDef *) UART3_BASE)
+
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1_PELI           ((CAN_Peli_TypeDef *) CAN1_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)//RESERVED
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)//RESERVED
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)//RESERVED
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define UART1              ((UART_TypeDef *) UART1_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+
+
+#define USB				    ((USB_TypeDef*) USB_BASE )//usb_base
+
+/**
+* @}
+*/
+
+/** @addtogroup Exported_constants
+* @{
+*/
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+* @{
+*/
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x1E00)     /*!< PLS[3:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0200)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0400)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0800)     /*!< Bit 2 */
+#define  PWR_CR_PLS_3                        ((uint16_t)0x1000)     /*!< Bit 3 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_2V6                      ((uint16_t)0x0000)     /*!< PVD level 2.6V */
+#define  PWR_CR_PLS_2V8                      ((uint16_t)0x0200)     /*!< PVD level 2.8V */
+#define  PWR_CR_PLS_3V0                      ((uint16_t)0x0400)     /*!< PVD level 3.0V */
+#define  PWR_CR_PLS_3V2                      ((uint16_t)0x0600)     /*!< PVD level 3.2V */
+#define  PWR_CR_PLS_3V4                      ((uint16_t)0x0800)     /*!< PVD level 3.4V */
+#define  PWR_CR_PLS_3V6                      ((uint16_t)0x0A00)     /*!< PVD level 3.6V */
+#define  PWR_CR_PLS_3V8                      ((uint16_t)0x0C00)     /*!< PVD level 3.8V */
+#define  PWR_CR_PLS_4V0                      ((uint16_t)0x0E00)     /*!< PVD level 4.0V */
+#define  PWR_CR_PLS_4V2                      ((uint16_t)0x1000)     /*!< PVD level 4.2V */
+#define  PWR_CR_PLS_4V4                      ((uint16_t)0x1200)     /*!< PVD level 4.4V */
+#define  PWR_CR_PLS_4V6                      ((uint16_t)0x1400)     /*!< PVD level 4.6V */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_EWUP                        ((uint16_t)0x0100)     /*!< Enable WKUP pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Backup registers                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DR1 register  ********************/
+#define  BKP_DR1_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR2 register  ********************/
+#define  BKP_DR2_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR3 register  ********************/
+#define  BKP_DR3_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR4 register  ********************/
+#define  BKP_DR4_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR5 register  ********************/
+#define  BKP_DR5_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR6 register  ********************/
+#define  BKP_DR6_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR7 register  ********************/
+#define  BKP_DR7_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR8 register  ********************/
+#define  BKP_DR8_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR9 register  ********************/
+#define  BKP_DR9_D                           ((uint16_t)0xFFFF)     /*!< Backup data */
+
+/*******************  Bit definition for BKP_DR10 register  *******************/
+#define  BKP_DR10_D                          ((uint16_t)0xFFFF)     /*!< Backup data */
+
+
+/******************  Bit definition for BKP_RTCCR register  *******************/
+#define  BKP_RTCCR_CAL                       ((uint16_t)0x007F)     /*!< Calibration value */
+#define  BKP_RTCCR_CCO                       ((uint16_t)0x0080)     /*!< Calibration Clock Output */
+#define  BKP_RTCCR_ASOE                      ((uint16_t)0x0100)     /*!< Alarm or Second Output Enable */
+#define  BKP_RTCCR_ASOS                      ((uint16_t)0x0200)     /*!< Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_CR register  ********************/
+#define  BKP_CR_TPE                          ((uint8_t)0x01)        /*!< TAMPER pin enable */
+#define  BKP_CR_TPAL                         ((uint8_t)0x02)        /*!< TAMPER pin active level */
+
+/*******************  Bit definition for BKP_CSR register  ********************/
+#define  BKP_CSR_CTE                         ((uint16_t)0x0001)     /*!< Clear Tamper event */
+#define  BKP_CSR_CTI                         ((uint16_t)0x0002)     /*!< Clear Tamper Interrupt */
+#define  BKP_CSR_TPIE                        ((uint16_t)0x0004)     /*!< TAMPER Pin interrupt enable */
+#define  BKP_CSR_TEF                         ((uint16_t)0x0100)     /*!< Tamper Event Flag */
+#define  BKP_CSR_TIF                         ((uint16_t)0x0200)     /*!< Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+#define  RCC_CR_PLLDN                   	((uint32_t)0xFC000000)        /*!< PLLDN[5:0] bits */
+#define  RCC_CR_PLLDN_0                  	((uint32_t)0x04000000)         /*!< Bit 0 */
+#define  RCC_CR_PLLDN_1                  	((uint32_t)0x08000000)         /*!< Bit 1 */
+#define  RCC_CR_PLLDN_2                  	((uint32_t)0x10000000)         /*!< Bit 2 */
+#define  RCC_CR_PLLDN_3                  	((uint32_t)0x20000000)         /*!< Bit 3 */
+#define  RCC_CR_PLLDN_4                  	((uint32_t)0x40000000)         /*!< Bit 4 */
+#define  RCC_CR_PLLDN_5                  	((uint32_t)0x80000000)         /*!< Bit 5 */
+
+#define  RCC_CR_PLLDM                   	((uint32_t)0x00700000)        /*!< PLLDM[2:0] bits */
+#define  RCC_CR_PLLDM_0                  	((uint32_t)0x00100000)         /*!< Bit 0 */
+#define  RCC_CR_PLLDM_1                  	((uint32_t)0x00200000)         /*!< Bit 1 */
+#define  RCC_CR_PLLDM_2                  	((uint32_t)0x00400000)         /*!< Bit 2 */
+/*******************  Bit definition for RCC_CFGR register  *******************/
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+/*!< SW configuration */
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+/*!< PPRE1 configuration */
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
+
+/*!< PPRE2 configuration */
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+#define  RCC_CFGR_USBPRE                     ((uint32_t)0x00C00000)        /*!< USB prescaler BIT[1:0] */
+#define  RCC_CFGR_USBPRE_0                   ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  RCC_CFGR_USBPRE_1                   ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)  	   //
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< Internal 48 MHz RC oscillator clock selected */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< External 1-25 MHz oscillator clock selected */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected*/
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)            /*!< Alternate Function I/O reset */
+#define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)            /*!< I/O port A reset */
+#define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)            /*!< IO port B reset */
+#define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)            /*!< IO port C reset */
+#define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)            /*!< IO port D reset */
+#define  RCC_APB2RSTR_IOPERST                ((uint32_t)0x00000040)            /*!< IO port E reset *///RESERVED
+#define  RCC_APB2RSTR_IOPFRST                ((uint32_t)0x00000080)            /*!< IO port F reset *///RESERVED
+#define  RCC_APB2RSTR_IOPGRST                ((uint32_t)0x00000100)            /*!< IO port G reset *///RESERVED
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)            /*!< ADC 1 interface reset */
+#define  RCC_APB2RSTR_ADC2RST                ((uint32_t)0x00000400)            /*!< ADC 2 interface reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)            /*!< TIM1 Timer reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)            /*!< SPI 1 reset */
+#define  RCC_APB2RSTR_UART1RST              ((uint32_t)0x00004000)            /*!< UART1 reset */
+#define  RCC_APB2RSTR_CPTRST                 ((uint32_t)0x0008000)             /*!< CPT interface reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
+#define  RCC_APB1RSTR_UART2RST              ((uint32_t)0x00020000)        /*!< UART 2 reset */
+#define  RCC_APB1RSTR_UART3RST              ((uint32_t)0x00040000)        /*!< UART 3 reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
+#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
+#define  RCC_APB1RSTR_CANRST                 ((uint32_t)0x02000000)        /*!< CAN reset */
+#define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMAEN                    ((uint16_t)0x0001)            /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint16_t)0x0004)            /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint16_t)0x0010)            /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint16_t)0x0040)            /*!< CRC clock enable */
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)            /*!< Alternate Function I/O clock enable */
+#define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)            /*!< I/O port A clock enable */
+#define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)            /*!< I/O port B clock enable */
+#define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)            /*!< I/O port C clock enable */
+#define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)            /*!< I/O port D clock enable */
+#define  RCC_APB2ENR_IOPEEN                  ((uint32_t)0x00000040)            /*!< I/O port E clock enable *///RESERVED
+#define  RCC_APB2ENR_IOPFEN                  ((uint32_t)0x00000080)            /*!< I/O port F clock enable *///RESERVED
+#define  RCC_APB2ENR_IOPGEN                  ((uint32_t)0x00000100)            /*!< I/O port G clock enable *///RESERVED
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)            /*!< ADC 1 interface clock enable */
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000400)            /*!< ADC 2 interface clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)            /*!< TIM1 Timer clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)            /*!< SPI 1 clock enable */
+#define  RCC_APB2ENR_UART1EN                ((uint32_t)0x00004000)            /*!< UART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
+#define  RCC_APB1ENR_UART2EN                ((uint32_t)0x00020000)        /*!< UART 2 clock enable */
+#define  RCC_APB1ENR_UART3EN                ((uint32_t)0x00040000)        /*!< UART 3 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
+#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
+#define  RCC_APB1ENR_CANEN                   ((uint32_t)0x02000000)        /*!< CAN clock enable */
+#define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                General Purpose and Alternate Function IO                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CRL register  *******************/
+#define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*******************  Bit definition for GPIO_CRH register  *******************/
+#define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
+
+#define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
+#define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
+
+#define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
+
+#define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
+#define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
+
+/*!<******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR0                        ((uint16_t)0x0001)            /*!< Port input data, bit 0 */
+#define GPIO_IDR_IDR1                        ((uint16_t)0x0002)            /*!< Port input data, bit 1 */
+#define GPIO_IDR_IDR2                        ((uint16_t)0x0004)            /*!< Port input data, bit 2 */
+#define GPIO_IDR_IDR3                        ((uint16_t)0x0008)            /*!< Port input data, bit 3 */
+#define GPIO_IDR_IDR4                        ((uint16_t)0x0010)            /*!< Port input data, bit 4 */
+#define GPIO_IDR_IDR5                        ((uint16_t)0x0020)            /*!< Port input data, bit 5 */
+#define GPIO_IDR_IDR6                        ((uint16_t)0x0040)            /*!< Port input data, bit 6 */
+#define GPIO_IDR_IDR7                        ((uint16_t)0x0080)            /*!< Port input data, bit 7 */
+#define GPIO_IDR_IDR8                        ((uint16_t)0x0100)            /*!< Port input data, bit 8 */
+#define GPIO_IDR_IDR9                        ((uint16_t)0x0200)            /*!< Port input data, bit 9 */
+#define GPIO_IDR_IDR10                       ((uint16_t)0x0400)            /*!< Port input data, bit 10 */
+#define GPIO_IDR_IDR11                       ((uint16_t)0x0800)            /*!< Port input data, bit 11 */
+#define GPIO_IDR_IDR12                       ((uint16_t)0x1000)            /*!< Port input data, bit 12 */
+#define GPIO_IDR_IDR13                       ((uint16_t)0x2000)            /*!< Port input data, bit 13 */
+#define GPIO_IDR_IDR14                       ((uint16_t)0x4000)            /*!< Port input data, bit 14 */
+#define GPIO_IDR_IDR15                       ((uint16_t)0x8000)            /*!< Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR0                        ((uint16_t)0x0001)            /*!< Port output data, bit 0 */
+#define GPIO_ODR_ODR1                        ((uint16_t)0x0002)            /*!< Port output data, bit 1 */
+#define GPIO_ODR_ODR2                        ((uint16_t)0x0004)            /*!< Port output data, bit 2 */
+#define GPIO_ODR_ODR3                        ((uint16_t)0x0008)            /*!< Port output data, bit 3 */
+#define GPIO_ODR_ODR4                        ((uint16_t)0x0010)            /*!< Port output data, bit 4 */
+#define GPIO_ODR_ODR5                        ((uint16_t)0x0020)            /*!< Port output data, bit 5 */
+#define GPIO_ODR_ODR6                        ((uint16_t)0x0040)            /*!< Port output data, bit 6 */
+#define GPIO_ODR_ODR7                        ((uint16_t)0x0080)            /*!< Port output data, bit 7 */
+#define GPIO_ODR_ODR8                        ((uint16_t)0x0100)            /*!< Port output data, bit 8 */
+#define GPIO_ODR_ODR9                        ((uint16_t)0x0200)            /*!< Port output data, bit 9 */
+#define GPIO_ODR_ODR10                       ((uint16_t)0x0400)            /*!< Port output data, bit 10 */
+#define GPIO_ODR_ODR11                       ((uint16_t)0x0800)            /*!< Port output data, bit 11 */
+#define GPIO_ODR_ODR12                       ((uint16_t)0x1000)            /*!< Port output data, bit 12 */
+#define GPIO_ODR_ODR13                       ((uint16_t)0x2000)            /*!< Port output data, bit 13 */
+#define GPIO_ODR_ODR14                       ((uint16_t)0x4000)            /*!< Port output data, bit 14 */
+#define GPIO_ODR_ODR15                       ((uint16_t)0x8000)            /*!< Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSRR register  *******************/
+#define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
+#define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
+#define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
+#define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
+#define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
+#define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
+#define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
+#define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
+#define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
+#define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
+#define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
+#define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
+#define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
+#define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
+#define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
+#define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
+
+#define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
+#define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
+#define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
+#define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
+#define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
+#define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
+#define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
+#define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
+#define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
+#define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
+#define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
+#define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
+#define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
+#define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
+#define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
+#define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BRR register  *******************/
+#define GPIO_BRR_BR0                         ((uint16_t)0x0001)            /*!< Port x Reset bit 0 */
+#define GPIO_BRR_BR1                         ((uint16_t)0x0002)            /*!< Port x Reset bit 1 */
+#define GPIO_BRR_BR2                         ((uint16_t)0x0004)            /*!< Port x Reset bit 2 */
+#define GPIO_BRR_BR3                         ((uint16_t)0x0008)            /*!< Port x Reset bit 3 */
+#define GPIO_BRR_BR4                         ((uint16_t)0x0010)            /*!< Port x Reset bit 4 */
+#define GPIO_BRR_BR5                         ((uint16_t)0x0020)            /*!< Port x Reset bit 5 */
+#define GPIO_BRR_BR6                         ((uint16_t)0x0040)            /*!< Port x Reset bit 6 */
+#define GPIO_BRR_BR7                         ((uint16_t)0x0080)            /*!< Port x Reset bit 7 */
+#define GPIO_BRR_BR8                         ((uint16_t)0x0100)            /*!< Port x Reset bit 8 */
+#define GPIO_BRR_BR9                         ((uint16_t)0x0200)            /*!< Port x Reset bit 9 */
+#define GPIO_BRR_BR10                        ((uint16_t)0x0400)            /*!< Port x Reset bit 10 */
+#define GPIO_BRR_BR11                        ((uint16_t)0x0800)            /*!< Port x Reset bit 11 */
+#define GPIO_BRR_BR12                        ((uint16_t)0x1000)            /*!< Port x Reset bit 12 */
+#define GPIO_BRR_BR13                        ((uint16_t)0x2000)            /*!< Port x Reset bit 13 */
+#define GPIO_BRR_BR14                        ((uint16_t)0x4000)            /*!< Port x Reset bit 14 */
+#define GPIO_BRR_BR15                        ((uint16_t)0x8000)            /*!< Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
+#define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
+#define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
+#define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
+#define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
+#define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
+#define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
+#define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
+#define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
+#define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
+#define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
+#define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
+#define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
+#define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
+#define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
+#define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
+#define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
+
+/*----------------------------------------------------------------------------*/
+
+
+
+/******************  Bit definition for AFIO_MAPR register  *******************/
+#define AFIO_MAPR_SPI1 _REMAP                ((uint32_t)0x00000001)        /*!< SPI1 remapping */
+#define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
+#define AFIO_MAPR_UART1_REMAP               ((uint32_t)0x00000004)        /*!< UART1 remapping */
+
+#define AFIO_MAPR_UART3_REMAP               ((uint32_t)0x00000030)        /*!< UART3_REMAP[1:0] bits (UART3 remapping) */
+#define AFIO_MAPR_UART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
+
+/* UART3_REMAP configuration */
+#define AFIO_MAPR_UART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_UART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+
+#define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
+
+/*!< TIM1_REMAP configuration */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+
+#define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< TIM2_REMAP configuration */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+
+#define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
+#define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
+
+/*!< TIM3_REMAP configuration */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+
+#define AFIO_MAPR_CAN_REMAP                  ((uint32_t)0x00006000)        /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_MAPR_CAN_REMAP_0                ((uint32_t)0x00002000)        /*!< Bit 0 */
+#define AFIO_MAPR_CAN_REMAP_1                ((uint32_t)0x00004000)        /*!< Bit 1 */
+
+/*!< CAN_REMAP configuration */
+#define AFIO_MAPR_CAN_REMAP_REMAP1           ((uint32_t)0x00000000)        /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP2           ((uint32_t)0x00004000)        /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_MAPR_CAN_REMAP_REMAP3           ((uint32_t)0x00006000)        /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+
+#define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+/*!< SWJ_CFG configuration */
+#define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                   ((uint16_t)0x000F)            /*!< EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                   ((uint16_t)0x00F0)            /*!< EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                   ((uint16_t)0x0F00)            /*!< EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                   ((uint16_t)0xF000)            /*!< EXTI 3 configuration */
+
+/*!< EXTI0 configuration */
+#define AFIO_EXTICR1_EXTI0_PA                ((uint16_t)0x0000)            /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                ((uint16_t)0x0001)            /*!< PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                ((uint16_t)0x0002)            /*!< PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                ((uint16_t)0x0003)            /*!< PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                ((uint16_t)0x0004)            /*!< PE[0] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI0_PF                ((uint16_t)0x0005)            /*!< PF[0] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI0_PG                ((uint16_t)0x0006)            /*!< PG[0] pin *///RESERVED
+
+/*!< EXTI1 configuration */
+#define AFIO_EXTICR1_EXTI1_PA                ((uint16_t)0x0000)            /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                ((uint16_t)0x0010)            /*!< PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                ((uint16_t)0x0020)            /*!< PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                ((uint16_t)0x0030)            /*!< PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                ((uint16_t)0x0040)            /*!< PE[1] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI1_PF                ((uint16_t)0x0050)            /*!< PF[1] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI1_PG                ((uint16_t)0x0060)            /*!< PG[1] pin *///RESERVED
+
+/*!< EXTI2 configuration */
+#define AFIO_EXTICR1_EXTI2_PA                ((uint16_t)0x0000)            /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                ((uint16_t)0x0100)            /*!< PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                ((uint16_t)0x0200)            /*!< PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                ((uint16_t)0x0300)            /*!< PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                ((uint16_t)0x0400)            /*!< PE[2] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI2_PF                ((uint16_t)0x0500)            /*!< PF[2] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI2_PG                ((uint16_t)0x0600)            /*!< PG[2] pin *///RESERVED
+
+/*!< EXTI3 configuration */
+#define AFIO_EXTICR1_EXTI3_PA                ((uint16_t)0x0000)            /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                ((uint16_t)0x1000)            /*!< PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                ((uint16_t)0x2000)            /*!< PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                ((uint16_t)0x3000)            /*!< PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                ((uint16_t)0x4000)            /*!< PE[3] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI3_PF                ((uint16_t)0x5000)            /*!< PF[3] pin *///RESERVED
+#define AFIO_EXTICR1_EXTI3_PG                ((uint16_t)0x6000)            /*!< PG[3] pin *///RESERVED
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                   ((uint16_t)0x000F)            /*!< EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                   ((uint16_t)0x00F0)            /*!< EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                   ((uint16_t)0x0F00)            /*!< EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                   ((uint16_t)0xF000)            /*!< EXTI 7 configuration */
+
+/*!< EXTI4 configuration */
+#define AFIO_EXTICR2_EXTI4_PA                ((uint16_t)0x0000)            /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                ((uint16_t)0x0001)            /*!< PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                ((uint16_t)0x0002)            /*!< PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                ((uint16_t)0x0003)            /*!< PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                ((uint16_t)0x0004)            /*!< PE[4] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI4_PF                ((uint16_t)0x0005)            /*!< PF[4] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI4_PG                ((uint16_t)0x0006)            /*!< PG[4] pin *///RESERVED
+
+/* EXTI5 configuration */
+#define AFIO_EXTICR2_EXTI5_PA                ((uint16_t)0x0000)            /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                ((uint16_t)0x0010)            /*!< PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                ((uint16_t)0x0020)            /*!< PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                ((uint16_t)0x0030)            /*!< PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                ((uint16_t)0x0040)            /*!< PE[5] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI5_PF                ((uint16_t)0x0050)            /*!< PF[5] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI5_PG                ((uint16_t)0x0060)            /*!< PG[5] pin *///RESERVED
+
+/*!< EXTI6 configuration */
+#define AFIO_EXTICR2_EXTI6_PA                ((uint16_t)0x0000)            /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                ((uint16_t)0x0100)            /*!< PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                ((uint16_t)0x0200)            /*!< PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                ((uint16_t)0x0300)            /*!< PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                ((uint16_t)0x0400)            /*!< PE[6] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI6_PF                ((uint16_t)0x0500)            /*!< PF[6] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI6_PG                ((uint16_t)0x0600)            /*!< PG[6] pin *///RESERVED
+
+/*!< EXTI7 configuration */
+#define AFIO_EXTICR2_EXTI7_PA                ((uint16_t)0x0000)            /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                ((uint16_t)0x1000)            /*!< PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                ((uint16_t)0x2000)            /*!< PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                ((uint16_t)0x3000)            /*!< PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                ((uint16_t)0x4000)            /*!< PE[7] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI7_PF                ((uint16_t)0x5000)            /*!< PF[7] pin *///RESERVED
+#define AFIO_EXTICR2_EXTI7_PG                ((uint16_t)0x6000)            /*!< PG[7] pin *///RESERVED
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                   ((uint16_t)0x000F)            /*!< EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                   ((uint16_t)0x00F0)            /*!< EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                  ((uint16_t)0x0F00)            /*!< EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                  ((uint16_t)0xF000)            /*!< EXTI 11 configuration */
+
+/*!< EXTI8 configuration */
+#define AFIO_EXTICR3_EXTI8_PA                ((uint16_t)0x0000)            /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                ((uint16_t)0x0001)            /*!< PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                ((uint16_t)0x0002)            /*!< PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                ((uint16_t)0x0003)            /*!< PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                ((uint16_t)0x0004)            /*!< PE[8] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI8_PF                ((uint16_t)0x0005)            /*!< PF[8] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI8_PG                ((uint16_t)0x0006)            /*!< PG[8] pin *///RESERVED
+
+/*!< EXTI9 configuration */
+#define AFIO_EXTICR3_EXTI9_PA                ((uint16_t)0x0000)            /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                ((uint16_t)0x0010)            /*!< PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                ((uint16_t)0x0020)            /*!< PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                ((uint16_t)0x0030)            /*!< PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                ((uint16_t)0x0040)            /*!< PE[9] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI9_PF                ((uint16_t)0x0050)            /*!< PF[9] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI9_PG                ((uint16_t)0x0060)            /*!< PG[9] pin *///RESERVED
+
+/*!< EXTI10 configuration */
+#define AFIO_EXTICR3_EXTI10_PA               ((uint16_t)0x0000)            /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB               ((uint16_t)0x0100)            /*!< PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC               ((uint16_t)0x0200)            /*!< PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD               ((uint16_t)0x0300)            /*!< PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE               ((uint16_t)0x0400)            /*!< PE[10] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI10_PF               ((uint16_t)0x0500)            /*!< PF[10] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI10_PG               ((uint16_t)0x0600)            /*!< PG[10] pin *///RESERVED
+
+/*!< EXTI11 configuration */
+#define AFIO_EXTICR3_EXTI11_PA               ((uint16_t)0x0000)            /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB               ((uint16_t)0x1000)            /*!< PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC               ((uint16_t)0x2000)            /*!< PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD               ((uint16_t)0x3000)            /*!< PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE               ((uint16_t)0x4000)            /*!< PE[11] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI11_PF               ((uint16_t)0x5000)            /*!< PF[11] pin *///RESERVED
+#define AFIO_EXTICR3_EXTI11_PG               ((uint16_t)0x6000)            /*!< PG[11] pin *///RESERVED
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                  ((uint16_t)0x000F)            /*!< EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                  ((uint16_t)0x00F0)            /*!< EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                  ((uint16_t)0x0F00)            /*!< EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                  ((uint16_t)0xF000)            /*!< EXTI 15 configuration */
+
+/* EXTI12 configuration */
+#define AFIO_EXTICR4_EXTI12_PA               ((uint16_t)0x0000)            /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB               ((uint16_t)0x0001)            /*!< PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC               ((uint16_t)0x0002)            /*!< PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD               ((uint16_t)0x0003)            /*!< PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE               ((uint16_t)0x0004)            /*!< PE[12] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI12_PF               ((uint16_t)0x0005)            /*!< PF[12] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI12_PG               ((uint16_t)0x0006)            /*!< PG[12] pin *///RESERVED
+
+/* EXTI13 configuration */
+#define AFIO_EXTICR4_EXTI13_PA               ((uint16_t)0x0000)            /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB               ((uint16_t)0x0010)            /*!< PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC               ((uint16_t)0x0020)            /*!< PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD               ((uint16_t)0x0030)            /*!< PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE               ((uint16_t)0x0040)            /*!< PE[13] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI13_PF               ((uint16_t)0x0050)            /*!< PF[13] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI13_PG               ((uint16_t)0x0060)            /*!< PG[13] pin *///RESERVED
+
+/*!< EXTI14 configuration */
+#define AFIO_EXTICR4_EXTI14_PA               ((uint16_t)0x0000)            /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB               ((uint16_t)0x0100)            /*!< PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC               ((uint16_t)0x0200)            /*!< PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD               ((uint16_t)0x0300)            /*!< PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE               ((uint16_t)0x0400)            /*!< PE[14] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI14_PF               ((uint16_t)0x0500)            /*!< PF[14] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI14_PG               ((uint16_t)0x0600)            /*!< PG[14] pin *///RESERVED
+
+/*!< EXTI15 configuration */
+#define AFIO_EXTICR4_EXTI15_PA               ((uint16_t)0x0000)            /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB               ((uint16_t)0x1000)            /*!< PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC               ((uint16_t)0x2000)            /*!< PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD               ((uint16_t)0x3000)            /*!< PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE               ((uint16_t)0x4000)            /*!< PE[15] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI15_PF               ((uint16_t)0x5000)            /*!< PF[15] pin *///RESERVED
+#define AFIO_EXTICR4_EXTI15_PG               ((uint16_t)0x6000)            /*!< PG[15] pin *///RESERVED
+
+/******************************************************************************/
+/*                                                                            */
+/*                               SystemTick                                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
+#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
+#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
+#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
+#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
+#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  Nested Vectored Interrupt Controller                      */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
+#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
+#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
+#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
+#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
+#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
+#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
+#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
+#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
+#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
+#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
+#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
+#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
+#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
+#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
+#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
+#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
+#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
+#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
+#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
+#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
+#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
+#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
+#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
+#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
+#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
+#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
+#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
+#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
+#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
+#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
+#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
+#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
+#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
+#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
+#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
+#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
+#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
+#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
+#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
+#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
+#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
+#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
+#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
+#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
+#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
+#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
+#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
+#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
+#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
+#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
+#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
+#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
+#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
+#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
+#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
+#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
+#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
+#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
+#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
+#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for NVIC_PRI8 register  *******************/
+#define  NVIC_IPR7_PRI_32                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 32 */
+#define  NVIC_IPR7_PRI_33                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 33 */
+#define  NVIC_IPR7_PRI_34                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 34 */
+#define  NVIC_IPR7_PRI_35                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 35 */
+
+/******************  Bit definition for NVIC_PRI9 register  *******************/
+#define  NVIC_IPR7_PRI_36                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 36 */
+#define  NVIC_IPR7_PRI_37                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 37 */
+#define  NVIC_IPR7_PRI_38                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 38 */
+#define  NVIC_IPR7_PRI_39                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 39 */
+
+/******************  Bit definition for NVIC_PRI10 register  *******************/
+#define  NVIC_IPR7_PRI_40                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 40 */
+#define  NVIC_IPR7_PRI_41                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 41 */
+#define  NVIC_IPR7_PRI_42                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 42 */
+#define  NVIC_IPR7_PRI_43                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 43 */
+
+/******************  Bit definition for NVIC_PRI11 register  *******************/
+#define  NVIC_IPR7_PRI_44                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 44 */
+#define  NVIC_IPR7_PRI_45                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 45 */
+#define  NVIC_IPR7_PRI_46                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 46 */
+#define  NVIC_IPR7_PRI_47                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 47 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
+#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
+#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
+#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
+#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
+#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
+#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
+#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
+#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
+#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
+#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
+#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
+#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
+#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
+#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
+
+#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
+#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
+
+/* prority group configuration */
+#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
+#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define  SCB_SCR_SLEEPONEXIT                 ((uint8_t)0x02)               /*!< Sleep on exit bit */
+#define  SCB_SCR_SLEEPDEEP                   ((uint8_t)0x04)               /*!< Sleep deep bit */
+#define  SCB_SCR_SEVONPEND                   ((uint8_t)0x10)               /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define  SCB_CCR_NONBASETHRDENA              ((uint16_t)0x0001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define  SCB_CCR_USERSETMPEND                ((uint16_t)0x0002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define  SCB_CCR_UNALIGN_TRP                 ((uint16_t)0x0008)            /*!< Trap for unaligned access */
+#define  SCB_CCR_DIV_0_TRP                   ((uint16_t)0x0010)            /*!< Trap on Divide by 0 */
+#define  SCB_CCR_BFHFNMIGN                   ((uint16_t)0x0100)            /*!< Handlers running at priority -1 and -2 */
+#define  SCB_CCR_STKALIGN                    ((uint16_t)0x0200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
+#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
+#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
+#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
+#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
+#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
+#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
+#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
+#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
+#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
+#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
+#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
+#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
+#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
+#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
+#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
+#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
+#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
+#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
+#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
+#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
+#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
+#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
+#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
+#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
+#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
+#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
+#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define  SCB_DFSR_HALTED                     ((uint8_t)0x01)               /*!< Halt request flag */
+#define  SCB_DFSR_BKPT                       ((uint8_t)0x02)               /*!< BKPT flag */
+#define  SCB_DFSR_DWTTRAP                    ((uint8_t)0x04)               /*!< Data Watchpoint and Trace (DWT) flag */
+#define  SCB_DFSR_VCATCH                     ((uint8_t)0x08)               /*!< Vector catch flag */
+#define  SCB_DFSR_EXTERNAL                   ((uint8_t)0x10)               /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Trigger request occurred on the external interrupt line 18 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)
+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
+#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
+#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
+#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
+#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
+#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
+#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
+#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
+#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clearr */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
+#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
+#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
+#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
+#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
+#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
+#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
+#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR1 register  *******************/
+#define  DMA_CCR1_EN                         ((uint16_t)0x0001)            /*!< Channel enable*/
+#define  DMA_CCR1_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR1_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR1_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR1_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR1_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR1_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR1_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR1_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR1_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR1_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR1_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR1_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR1_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits(Channel Priority level) */
+#define  DMA_CCR1_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR1_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR1_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR2 register  *******************/
+#define  DMA_CCR2_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR2_TCIE                       ((uint16_t)0x0002)            /*!< ransfer complete interrupt enable */
+#define  DMA_CCR2_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR2_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR2_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR2_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR2_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR2_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR2_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR2_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR2_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR2_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR2_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR2_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR2_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR2_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR2_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR3 register  *******************/
+#define  DMA_CCR3_EN                         ((uint16_t)0x0001)            /*!< Channel enable */
+#define  DMA_CCR3_TCIE                       ((uint16_t)0x0002)            /*!< Transfer complete interrupt enable */
+#define  DMA_CCR3_HTIE                       ((uint16_t)0x0004)            /*!< Half Transfer interrupt enable */
+#define  DMA_CCR3_TEIE                       ((uint16_t)0x0008)            /*!< Transfer error interrupt enable */
+#define  DMA_CCR3_DIR                        ((uint16_t)0x0010)            /*!< Data transfer direction */
+#define  DMA_CCR3_CIRC                       ((uint16_t)0x0020)            /*!< Circular mode */
+#define  DMA_CCR3_PINC                       ((uint16_t)0x0040)            /*!< Peripheral increment mode */
+#define  DMA_CCR3_MINC                       ((uint16_t)0x0080)            /*!< Memory increment mode */
+
+#define  DMA_CCR3_PSIZE                      ((uint16_t)0x0300)            /*!< PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR3_PSIZE_0                    ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  DMA_CCR3_PSIZE_1                    ((uint16_t)0x0200)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MSIZE                      ((uint16_t)0x0C00)            /*!< MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR3_MSIZE_0                    ((uint16_t)0x0400)            /*!< Bit 0 */
+#define  DMA_CCR3_MSIZE_1                    ((uint16_t)0x0800)            /*!< Bit 1 */
+
+#define  DMA_CCR3_PL                         ((uint16_t)0x3000)            /*!< PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR3_PL_0                       ((uint16_t)0x1000)            /*!< Bit 0 */
+#define  DMA_CCR3_PL_1                       ((uint16_t)0x2000)            /*!< Bit 1 */
+
+#define  DMA_CCR3_MEM2MEM                    ((uint16_t)0x4000)            /*!< Memory to memory mode */
+
+/*!<******************  Bit definition for DMA_CCR4 register  *******************/
+#define  DMA_CCR4_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
+#define  DMA_CCR4_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
+#define  DMA_CCR4_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
+#define  DMA_CCR4_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
+#define  DMA_CCR4_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
+#define  DMA_CCR4_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
+#define  DMA_CCR4_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
+#define  DMA_CCR4_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
+
+#define  DMA_CCR4_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR4_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  DMA_CCR4_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  DMA_CCR4_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR4_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  DMA_CCR4_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  DMA_CCR4_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR4_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  DMA_CCR4_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  DMA_CCR4_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode */
+
+/******************  Bit definition for DMA_CCR5 register  *******************/
+#define  DMA_CCR5_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
+#define  DMA_CCR5_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
+#define  DMA_CCR5_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
+#define  DMA_CCR5_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
+#define  DMA_CCR5_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
+#define  DMA_CCR5_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
+#define  DMA_CCR5_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
+#define  DMA_CCR5_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
+
+#define  DMA_CCR5_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR5_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  DMA_CCR5_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  DMA_CCR5_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR5_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  DMA_CCR5_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  DMA_CCR5_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR5_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  DMA_CCR5_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  DMA_CCR5_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CCR6 register  *******************/
+#define  DMA_CCR6_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
+#define  DMA_CCR6_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
+#define  DMA_CCR6_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
+#define  DMA_CCR6_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
+#define  DMA_CCR6_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
+#define  DMA_CCR6_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
+#define  DMA_CCR6_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
+#define  DMA_CCR6_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
+
+#define  DMA_CCR6_PSIZE                      ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR6_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  DMA_CCR6_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  DMA_CCR6_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR6_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  DMA_CCR6_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  DMA_CCR6_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR6_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  DMA_CCR6_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  DMA_CCR6_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode */
+
+/*******************  Bit definition for DMA_CCR7 register  *******************/
+#define  DMA_CCR7_EN                         ((uint16_t)0x0001)            /*!<Channel enable */
+#define  DMA_CCR7_TCIE                       ((uint16_t)0x0002)            /*!<Transfer complete interrupt enable */
+#define  DMA_CCR7_HTIE                       ((uint16_t)0x0004)            /*!<Half Transfer interrupt enable */
+#define  DMA_CCR7_TEIE                       ((uint16_t)0x0008)            /*!<Transfer error interrupt enable */
+#define  DMA_CCR7_DIR                        ((uint16_t)0x0010)            /*!<Data transfer direction */
+#define  DMA_CCR7_CIRC                       ((uint16_t)0x0020)            /*!<Circular mode */
+#define  DMA_CCR7_PINC                       ((uint16_t)0x0040)            /*!<Peripheral increment mode */
+#define  DMA_CCR7_MINC                       ((uint16_t)0x0080)            /*!<Memory increment mode */
+
+#define  DMA_CCR7_PSIZE            ,         ((uint16_t)0x0300)            /*!<PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CCR7_PSIZE_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  DMA_CCR7_PSIZE_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  DMA_CCR7_MSIZE                      ((uint16_t)0x0C00)            /*!<MSIZE[1:0] bits (Memory size) */
+#define  DMA_CCR7_MSIZE_0                    ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  DMA_CCR7_MSIZE_1                    ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  DMA_CCR7_PL                         ((uint16_t)0x3000)            /*!<PL[1:0] bits (Channel Priority level) */
+#define  DMA_CCR7_PL_0                       ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  DMA_CCR7_PL_1                       ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  DMA_CCR7_MEM2MEM                    ((uint16_t)0x4000)            /*!<Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define  DMA_CNDTR1_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define  DMA_CNDTR2_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define  DMA_CNDTR3_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define  DMA_CNDTR4_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define  DMA_CNDTR5_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define  DMA_CNDTR6_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define  DMA_CNDTR7_NDT                      ((uint16_t)0xFFFF)            /*!<Number of data to Transfer */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!<Peripheral Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!<Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADDATA register  ********************/
+#define  ADDATA_DATA                        ((uint32_t)0x00000FFF)               /*!<ADC 12bit convert data */
+#define  ADDATA_CHANNELSEL                  ((uint32_t)0x00070000)               /*!<CHANNELSEL[19:16] (ADC current channel convert data) */
+#define  ADDATA_CHANNELSEL_0                 ((uint32_t)0x00010000)               /*!<Bit 0 */
+#define  ADDATA_CHANNELSEL_1                 ((uint32_t)0x00020000)               /*!<Bit 1*/
+#define  ADDATA_CHANNELSEL_2                 ((uint32_t)0x00040000)               /*!<Bit 2 */
+#define  ADDATA_CHANNELSEL_3                 ((uint32_t)0x00080000)               /*!<Bit 3 */
+#define  ADDATA_OVERRUN                     ((uint32_t)0x00100000)               /*!<ADC data will be cover */
+#define  ADDATA_VALID                       ((uint32_t)0x00200000)               /*!<ADC data[11:0] is valid*/
+
+
+/********************  Bit definition for ADCFG register  ********************/
+#define  ADCFG_ADEN                        ((uint32_t)0x00000001)               /*!<ADC convert enable */
+#define  ADCFG_ADWEN                       ((uint32_t)0x00000002)               /*!<ADC window compare enable */
+#define  ADCFG_TVSEN                       ((uint32_t)0x00000004)               /*!<ADC sensor enable */
+#define  ADCFG_ADCPRE_2                    ((uint32_t)0x00000000)               /*!<ADC preclk 2 */
+#define  ADCFG_ADCPRE_4                    ((uint32_t)0x00000010)               /*!<ADC preclk 4 */
+#define  ADCFG_ADCPRE_6                    ((uint32_t)0x00000020)               /*!<ADC preclk 6 */
+#define  ADCFG_ADCPRE_8                    ((uint32_t)0x00000030)               /*!<ADC preclk 8 */
+#define  ADCFG_ADCPRE_10                   ((uint32_t)0x00000040)               /*!<ADC preclk 10 */
+#define  ADCFG_ADCPRE_12                   ((uint32_t)0x00000050)               /*!<ADC preclk 12 */
+#define  ADCFG_ADCPRE_14                   ((uint32_t)0x00000060)               /*!<ADC preclk 14 */
+#define  ADCFG_ADCPRE_16                   ((uint32_t)0x00000070)               /*!<ADC preclk 16 */
+
+/********************  Bit definition for ADCR register  ********************/
+#define  ADCR_ADIE                         ((uint32_t)0x00000001)               /*!<ADC interrupt enable */
+#define  ADCR_ADWIE                        ((uint32_t)0x00000002)               /*!<ADC window compare interrupt enable */
+#define  ADCR_TRGEN                        ((uint32_t)0x00000004)               /*!<extranal trigger single start AD convert */
+#define  ADCR_DMAEN                        ((uint32_t)0x00000008)               /*!<ADC DMA enable */
+#define  ADCR_TRGSEL                       ((uint32_t)0x00000070)               /*!<TRGSEL[6:4] ADC1 external trigger source select */
+#define  ADCR_TRGSEL_0                     ((uint32_t)0x00000010)               /*!<Bit 0 */
+#define  ADCR_TRGSEL_1                     ((uint32_t)0x00000020)               /*!<Bit 1 */
+#define  ADCR_TRGSEL_2                     ((uint32_t)0x00000040)               /*!<Bit 2 */
+
+#define  ADCR_ADST                         ((uint32_t)0x00000100)               /*!<ADC start convert data */
+#define  ADCR_ADMD_SINGLE                  ((uint32_t)0x00000000)               /*!<ADC single convert mode */
+#define  ADCR_ADMD_PERIOD                  ((uint32_t)0x00000200)               /*!<ADC single period convert mode */
+#define  ADCR_ADMD_CONTINUE                ((uint32_t)0x00000400)               /*!<ADC continue scan convert mode */
+#define  ADCR_ALIGN_LEFT                   ((uint32_t)0x00000800)               /*!<ADC data left align */
+#define  ADCR_ALIGN_RIGHT                  ((uint32_t)0x00000000)               /*!<ADC data right align */
+#define  ADCR_CMPCH                        ((uint32_t)0x0000F000)               /*!<CMPCH[15:12] ADC window compare channel0 convert data */
+#define  ADCR_CMPCH_0                      ((uint32_t)0x00001000)               /*!<Bit 0 */
+#define  ADCR_CMPCH_1                      ((uint32_t)0x00002000)               /*!<Bit 1 */
+#define  ADCR_CMPCH_2                      ((uint32_t)0x00004000)               /*!<Bit 2 */
+#define  ADCR_CMPCH_3                      ((uint32_t)0x00008000)               /*!<Bit 3 */
+
+
+/********************  Bit definition for ADCHS register  ********************/
+#define  ADCHS_CHEN0                       ((uint32_t)0x00000001)              /*!<ADC channel0 enable */
+#define  ADCHS_CHEN1                       ((uint32_t)0x00000002)              /*!<ADC channel1 enable */
+#define  ADCHS_CHEN2                       ((uint32_t)0x00000004)              /*!<ADC channel2 enable */
+#define  ADCHS_CHEN3                       ((uint32_t)0x00000008)              /*!<ADC channel3 enable */
+#define  ADCHS_CHEN4                       ((uint32_t)0x00000010)              /*!<ADC channel4 enable */
+#define  ADCHS_CHEN5                       ((uint32_t)0x00000020)              /*!<ADC channel5 enable */
+#define  ADCHS_CHEN6                       ((uint32_t)0x00000040)              /*!<ADC channel6 enable */
+#define  ADCHS_CHEN7                       ((uint32_t)0x00000080)              /*!<ADC channel7 enable */
+#define  ADCHS_SENSOREN                    ((uint32_t)0x00000100)              /*!<ADC sensor enable */
+
+
+/********************  Bit definition for ADCMPR register  ********************/
+#define  ADCMPR_CMPLDATA                   ((uint32_t)0x00000FFF)              /*!<ADC 12bit window compare DOWN LEVEL DATA*/
+#define  ADCMPR_CMPHDATA                   ((uint32_t)0x0FFF0000)              /*!<ADC 12bit window compare UP LEVEL DATA*/
+
+/********************  Bit definition for ADSTA register  ********************/
+#define  ADSTA_ADIF                        ((uint32_t)0x00000001)               /*!<ADC convert complete flag*/
+#define  ADSTA_ADWIF                       ((uint32_t)0x00000002)               /*!<ADC compare flag*/
+#define  ADSTA_BUSY                        ((uint32_t)0x00000004)               /*!<ADC busy flag*/
+#define  ADSTA_CHANNEL                     ((uint32_t)0x000001F0)               /*!<CHANNEL[8:4] ADC current channel*/
+#define  ADSTA_CHANNEL_0                   ((uint32_t)0x00000010)               /*!<Bit 0 */
+#define  ADSTA_CHANNEL_1                   ((uint32_t)0x00000020)               /*!<Bit 1*/
+#define  ADSTA_CHANNEL_2                   ((uint32_t)0x00000040)               /*!<Bit 2*/
+#define  ADSTA_CHANNEL_3                   ((uint32_t)0x00000080)               /*!<Bit 3*/
+#define  ADSTA_CHANNEL_4                   ((uint32_t)0x00000100)               /*!<Bit 4*/
+
+#define  ADSTA_VALID                       ((uint32_t)0x0001FE00)               /*!<VALID[16:9] ADC channel0 valid flag*/
+#define  ADSTA_VALID_0                     ((uint32_t)0x00000200)               /*!<Bit 0*/
+#define  ADSTA_VALID_1                     ((uint32_t)0x00000400)               /*!<Bit 1*/
+#define  ADSTA_VALID_2                     ((uint32_t)0x00000800)               /*!<Bit 2*/
+#define  ADSTA_VALID_3                     ((uint32_t)0x00001000)               /*!<Bit 3*/
+#define  ADSTA_VALID_4                     ((uint32_t)0x00002000)               /*!<Bit 4*/
+#define  ADSTA_VALID_5                     ((uint32_t)0x00004000)               /*!<Bit 5*/
+#define  ADSTA_VALID_6                     ((uint32_t)0x00008000)               /*!<Bit 6*/
+#define  ADSTA_VALID_7                     ((uint32_t)0x00010000)               /*!<Bit 7*/
+#define  ADSTA_OVERRUN                     ((uint32_t)0x1FF00000)               /*!<OVERRUN[28:20] ADC channel0 data covered flag*/
+#define  ADSTA_OVERRUN_0                   ((uint32_t)0x00100000)               /*!<Bit 0*/
+#define  ADSTA_OVERRUN_1                   ((uint32_t)0x00200000)               /*!<Bit 1*/
+#define  ADSTA_OVERRUN_2                   ((uint32_t)0x00400000)               /*!<Bit 2*/
+#define  ADSTA_OVERRUN_3                   ((uint32_t)0x00800000)               /*!<Bit 3*/
+#define  ADSTA_OVERRUN_4                   ((uint32_t)0x01000000)               /*!<Bit 4*/
+#define  ADSTA_OVERRUN_5                   ((uint32_t)0x02000000)               /*!<Bit 5*/
+#define  ADSTA_OVERRUN_6                   ((uint32_t)0x04000000)               /*!<Bit 6*/
+#define  ADSTA_OVERRUN_7                   ((uint32_t)0x08000000)               /*!<Bit 7*/
+#define  ADSTA_OVERRUN_8                   ((uint32_t)0x10000000)               /*!<Bit 8*/
+
+
+/********************  Bit definition for ADDR0~ADDR8 register  ********************/
+#define  ADDR_DATA                         ((uint32_t)0x00000FFF)                   /*!<ADC channel convert data */
+#define  ADDR_OVERRUN                      ((uint32_t)0x00100000)               /*!<ADC data covered flag */
+#define  ADDR_VALID                        ((uint32_t)0x00200000)               /*!<ADC data valid flag*/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
+
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
+
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
+
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
+
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */
+
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Real-Time Clock                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CRH register  ********************/
+#define  RTC_CRH_SECIE                       ((uint8_t)0x01)               /*!<Second Interrupt Enable */
+#define  RTC_CRH_ALRIE                       ((uint8_t)0x02)               /*!<Alarm Interrupt Enable */
+#define  RTC_CRH_OWIE                        ((uint8_t)0x04)               /*!<OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CRL register  ********************/
+#define  RTC_CRL_SECF                        ((uint8_t)0x01)               /*!<Second Flag */
+#define  RTC_CRL_ALRF                        ((uint8_t)0x02)               /*!<Alarm Flag */
+#define  RTC_CRL_OWF                         ((uint8_t)0x04)               /*!<OverfloW Flag */
+#define  RTC_CRL_RSF                         ((uint8_t)0x08)               /*!<Registers Synchronized Flag */
+#define  RTC_CRL_CNF                         ((uint8_t)0x10)               /*!<Configuration Flag */
+#define  RTC_CRL_RTOFF                       ((uint8_t)0x20)               /*!<RTC operation OFF */
+
+/*******************  Bit definition for RTC_PRLH register  *******************/
+#define  RTC_PRLH_PRL                        ((uint16_t)0x000F)            /*!<RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PRLL_PRL                        ((uint16_t)0xFFFF)            /*!<RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /*!<RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /*!<RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /*!<RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /*!<RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRH register  *******************/
+#define  RTC_ALRH_RTC_ALR                    ((uint16_t)0xFFFF)            /*!<RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRL register  *******************/
+#define  RTC_ALRL_RTC_ALR                    ((uint16_t)0xFFFF)            /*!<RTC Alarm Low */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   USB                                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USB_TOP register  *******************/
+#define  USB_TOP_SPEED                         ((uint16_t)0x0001)
+#define  USB_TOP_CONNECT                       ((uint16_t)0x0002)
+#define  USB_TOP_RESET                         ((uint16_t)0x0008)
+#define  USB_TOP_SUSPEND                       ((uint16_t)0x0010)
+#define  USB_TOP_ACTIVE                        ((uint16_t)0x0080)
+
+#define  USB_TOP_STATE                         ((uint16_t)0x0060)
+#define  USB_TOP_STATE_0                       ((uint16_t)0x0020)
+#define  USB_TOP_STATE_1                       ((uint16_t)0x0040)
+
+/*******************  Bit definition for USB_INT_STATE register  *******************/
+#define  USB_INT_STATE_RSTF                    ((uint16_t)0x0001)
+#define  USB_INT_STATE_SUSPENDF                ((uint16_t)0x0002)
+#define  USB_INT_STATE_RESUMF                  ((uint16_t)0x0004)
+#define  USB_INT_STATE_SOFF                    ((uint16_t)0x0008)
+#define  USB_INT_STATE_EPINTF                  ((uint16_t)0x0010)
+
+/*******************  Bit definition for EP_INT_STATE register  *******************/
+#define  EP_INT_STATE_EP0F                    ((uint16_t)0x0001)
+#define  EP_INT_STATE_EP1F                    ((uint16_t)0x0002)
+#define  EP_INT_STATE_EP2F                    ((uint16_t)0x0004)
+#define  EP_INT_STATE_EP3F                    ((uint16_t)0x0008)
+#define  EP_INT_STATE_EP4F                    ((uint16_t)0x0010)
+
+/*******************  Bit definition for EP0_INT_STATE register  *******************/
+#define  EPn_INT_STATE_SETUP                  ((uint16_t)0x0001)
+#define  EPn_INT_STATE_END                    ((uint16_t)0x0002)
+#define  EPn_INT_STATE_INNACK                 ((uint16_t)0x0004)
+#define  EPn_INT_STATE_INACK                  ((uint16_t)0x0008)
+#define  EPn_INT_STATE_INSTALL                ((uint16_t)0x0010)
+#define  EPn_INT_STATE_OUTNACK                ((uint16_t)0x0020)
+#define  EPn_INT_STATE_OUTACK                 ((uint16_t)0x0040)
+#define  EPn_INT_STATE_OUTSTALL               ((uint16_t)0x0080)
+
+/*******************  Bit definition for USB_INT_EN register  *******************/
+#define  USB_INT_EN_RSTIE                     ((uint16_t)0x0001)
+#define  USB_INT_EN_SUSPENDIE                 ((uint16_t)0x0002)
+#define  USB_INT_EN_RESUMIE                   ((uint16_t)0x0004)
+#define  USB_INT_EN_SOFIE                     ((uint16_t)0x0008)
+#define  USB_INT_EN_EPINTIE                   ((uint16_t)0x0010)
+
+/*******************  Bit definition for EP_INT_EN register  *******************/
+#define  EP_INT_EN_EP0IE                      ((uint16_t)0x0001)
+#define  EP_INT_EN_EP1IE                      ((uint16_t)0x0002)
+#define  EP_INT_EN_EP2IE                      ((uint16_t)0x0004)
+#define  EP_INT_EN_EP3IE                      ((uint16_t)0x0008)
+#define  EP_INT_EN_EP4IE                      ((uint16_t)0x0010)
+
+/*******************  Bit definition for EP0_INT_EN register  *******************/
+#define  EPn_INT_EN_SETUPIE                   ((uint16_t)0x0001)
+#define  EPn_INT_EN_ENDIE                     ((uint16_t)0x0002)
+#define  EPn_INT_EN_INNACKIE                  ((uint16_t)0x0004)
+#define  EPn_INT_EN_INACKIE                   ((uint16_t)0x0008)
+#define  EPn_INT_EN_INSTALLIE                 ((uint16_t)0x0010)
+#define  EPn_INT_EN_OUTNACKIE                 ((uint16_t)0x0020)
+#define  EPn_INT_EN_OUTACKIE                  ((uint16_t)0x0040)
+#define  EPn_INT_EN_OUTSTALLIE                ((uint16_t)0x0080)
+
+///*******************  Bit definition for EP1_INT_STATE register  *******************/
+//#define  EP1_INT_STATE_END                    ((uint16_t)0x0002)
+//#define  EP1_INT_STATE_INNACK                 ((uint16_t)0x0004)
+//#define  EP1_INT_STATE_INACK                  ((uint16_t)0x0008)
+//#define  EP1_INT_STATE_INSTALL                ((uint16_t)0x0010)
+//#define  EP1_INT_STATE_OUTNACK                ((uint16_t)0x0020)
+//#define  EP1_INT_STATE_OUTACK                 ((uint16_t)0x0040)
+//#define  EP1_INT_STATE_OUTSTALL               ((uint16_t)0x0080)
+
+///*******************  Bit definition for EP2_INT_STATE register  *******************/
+//#define  EP2_INT_STATE_END                    ((uint16_t)0x0002)
+//#define  EP2_INT_STATE_INNACK                 ((uint16_t)0x0004)
+//#define  EP2_INT_STATE_INACK                  ((uint16_t)0x0008)
+//#define  EP2_INT_STATE_INSTALL                ((uint16_t)0x0010)
+//#define  EP2_INT_STATE_OUTNACK                ((uint16_t)0x0020)
+//#define  EP2_INT_STATE_OUTACK                 ((uint16_t)0x0040)
+//#define  EP2_INT_STATE_OUTSTALL               ((uint16_t)0x0080)
+
+///*******************  Bit definition for EP3_INT_STATE register  *******************/
+//#define  EP3_INT_STATE_END                    ((uint16_t)0x0002)
+//#define  EP3_INT_STATE_INNACK                 ((uint16_t)0x0004)
+//#define  EP3_INT_STATE_INACK                  ((uint16_t)0x0008)
+//#define  EP3_INT_STATE_INSTALL                ((uint16_t)0x0010)
+//#define  EP3_INT_STATE_OUTNACK                ((uint16_t)0x0020)
+//#define  EP3_INT_STATE_OUTACK                 ((uint16_t)0x0040)
+//#define  EP3_INT_STATE_OUTSTALL               ((uint16_t)0x0080)
+
+///*******************  Bit definition for EP4_INT_STATE register  *******************/
+//#define  EP4_INT_STATE_END                    ((uint16_t)0x0002)
+//#define  EP4_INT_STATE_INNACK                 ((uint16_t)0x0004)
+//#define  EP4_INT_STATE_INACK                  ((uint16_t)0x0008)
+//#define  EP4_INT_STATE_INSTALL                ((uint16_t)0x0010)
+//#define  EP4_INT_STATE_OUTNACK                ((uint16_t)0x0020)
+//#define  EP4_INT_STATE_OUTACK                 ((uint16_t)0x0040)
+//#define  EP4_INT_STATE_OUTSTALL               ((uint16_t)0x0080)
+
+///*******************  Bit definition for EP1_INT_EN register  *******************/
+//#define  EPn_INT_EN_ENDIE                     ((uint16_t)0x0002)
+//#define  EPn_INT_EN_INNACKIE                  ((uint16_t)0x0004)
+//#define  EPn_INT_EN_INACKIE                   ((uint16_t)0x0008)
+//#define  EPn_INT_EN_INSTALLIE                 ((uint16_t)0x0010)
+//#define  EPn_INT_EN_OUTNACKIE                 ((uint16_t)0x0020)
+//#define  EPn_INT_EN_OUTACKIE                  ((uint16_t)0x0040)
+//#define  EPn_INT_EN_OUTSTALLIE                ((uint16_t)0x0080)
+
+/*******************  Bit definition for USB_ADDR register  *******************/
+#define  USB_ADDR_ADDR                        ((uint16_t)0x007F)
+
+/*******************  Bit definition for EP_EN register  *******************/
+#define  EP_EN_EP0EN                        ((uint16_t)0x0001)
+#define  EP_EN_EP1EN                        ((uint16_t)0x0002)
+#define  EP_EN_EP2EN                        ((uint16_t)0x0004)
+#define  EP_EN_EP3EN                        ((uint16_t)0x0008)
+#define  EP_EN_EP4EN                        ((uint16_t)0x0010)
+
+/*******************  Bit definition for TOG_CTRL1_4 register  *******************/
+#define  TOG_CTRL1_4_DTOG1                  ((uint16_t)0x0001)
+#define  TOG_CTRL1_4_DTOG1EN                ((uint16_t)0x0002)
+#define  TOG_CTRL1_4_DTOG2                  ((uint16_t)0x0004)
+#define  TOG_CTRL1_4_DTOG2EN                ((uint16_t)0x0008)
+#define  TOG_CTRL1_4_DTOG3                  ((uint16_t)0x0010)
+#define  TOG_CTRL1_4_DTOG3EN                ((uint16_t)0x0020)
+#define  TOG_CTRL1_4_DTOG4                  ((uint16_t)0x0040)
+#define  TOG_CTRL1_4_DTOG4EN                ((uint16_t)0x0080)
+
+/*******************  Bit definition for SETUP0 register  *******************/
+#define  SETUP0                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP1 register  *******************/
+#define  SETUP1                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP2 register  *******************/
+#define  SETUP2                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP3 register  *******************/
+#define  SETUP3                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP4 register  *******************/
+#define  SETUP4                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP5 register  *******************/
+#define  SETUP5                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP6 register  *******************/
+#define  SETUP6                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for SETUP7 register  *******************/
+#define  SETUP7                             ((uint16_t)0x00FF)
+
+/*******************  Bit definition for PACKET_SIZE1 register  *******************/
+#define  PACKET_SIZE1                        ((uint16_t)0x00FF)
+
+/*******************  Bit definition for PACKET_SIZE2 register  *******************/
+#define  PACKET_SIZE2                        ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP0_AVIL register  *******************/
+#define  EP0_AVIL_EPXAVIL                   ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP1_AVIL register  *******************/
+#define  EP1_AVIL_EPXAVIL                   ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP2_AVIL register  *******************/
+#define  EP2_AVIL_EPXAVIL                   ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP3_AVIL register  *******************/
+#define  EP3_AVIL_EPXAVIL                   ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP4_AVIL register  *******************/
+#define  EP4_AVIL_EPXAVIL                   ((uint16_t)0x00FF)
+
+/*******************  Bit definition for EP0_CTRL register  *******************/
+#define  EP0_CTRL_TRANEN                    ((uint16_t)0x0080)
+
+#define  EP0_CTRL_TRANCOUNT                 ((uint16_t)0x007F)
+#define  EP0_CTRL_TRANCOUNT_0               ((uint16_t)0x0001)
+#define  EP0_CTRL_TRANCOUNT_1               ((uint16_t)0x0002)
+#define  EP0_CTRL_TRANCOUNT_2               ((uint16_t)0x0004)
+#define  EP0_CTRL_TRANCOUNT_3               ((uint16_t)0x0008)
+#define  EP0_CTRL_TRANCOUNT_4               ((uint16_t)0x0010)
+#define  EP0_CTRL_TRANCOUNT_5               ((uint16_t)0x0020)
+#define  EP0_CTRL_TRANCOUNT_6               ((uint16_t)0x0040)
+
+/*******************  Bit definition for EP1_CTRL register  *******************/
+#define  EP1_CTRL_TRANEN                    ((uint16_t)0x0080)
+
+#define  EP1_CTRL_TRANCOUNT                 ((uint16_t)0x007F)
+#define  EP1_CTRL_TRANCOUNT_0               ((uint16_t)0x0001)
+#define  EP1_CTRL_TRANCOUNT_1               ((uint16_t)0x0002)
+#define  EP1_CTRL_TRANCOUNT_2               ((uint16_t)0x0004)
+#define  EP1_CTRL_TRANCOUNT_3               ((uint16_t)0x0008)
+#define  EP1_CTRL_TRANCOUNT_4               ((uint16_t)0x0010)
+#define  EP1_CTRL_TRANCOUNT_5               ((uint16_t)0x0020)
+#define  EP1_CTRL_TRANCOUNT_6               ((uint16_t)0x0040)
+
+/*******************  Bit definition for EP2_CTRL register  *******************/
+#define  EP2_CTRL_TRANEN                    ((uint16_t)0x0080)
+
+#define  EP2_CTRL_TRANCOUNT                 ((uint16_t)0x007F)
+#define  EP2_CTRL_TRANCOUNT_0               ((uint16_t)0x0001)
+#define  EP2_CTRL_TRANCOUNT_1               ((uint16_t)0x0002)
+#define  EP2_CTRL_TRANCOUNT_2               ((uint16_t)0x0004)
+#define  EP2_CTRL_TRANCOUNT_3               ((uint16_t)0x0008)
+#define  EP2_CTRL_TRANCOUNT_4               ((uint16_t)0x0010)
+#define  EP2_CTRL_TRANCOUNT_5               ((uint16_t)0x0020)
+#define  EP2_CTRL_TRANCOUNT_6               ((uint16_t)0x0040)
+
+/*******************  Bit definition for EP3_CTRL register  *******************/
+#define  EP3_CTRL_TRANEN                    ((uint16_t)0x0080)
+
+#define  EP3_CTRL_TRANCOUNT                 ((uint16_t)0x007F)
+#define  EP3_CTRL_TRANCOUNT_0               ((uint16_t)0x0001)
+#define  EP3_CTRL_TRANCOUNT_1               ((uint16_t)0x0002)
+#define  EP3_CTRL_TRANCOUNT_2               ((uint16_t)0x0004)
+#define  EP3_CTRL_TRANCOUNT_3               ((uint16_t)0x0008)
+#define  EP3_CTRL_TRANCOUNT_4               ((uint16_t)0x0010)
+#define  EP3_CTRL_TRANCOUNT_5               ((uint16_t)0x0020)
+#define  EP3_CTRL_TRANCOUNT_6               ((uint16_t)0x0040)
+
+/*******************  Bit definition for EP4_CTRL register  *******************/
+#define  EP4_CTRL_TRANEN                    ((uint16_t)0x0080)
+
+#define  EP4_CTRL_TRANCOUNT                 ((uint16_t)0x007F)
+#define  EP4_CTRL_TRANCOUNT_0               ((uint16_t)0x0001)
+#define  EP4_CTRL_TRANCOUNT_1               ((uint16_t)0x0002)
+#define  EP4_CTRL_TRANCOUNT_2               ((uint16_t)0x0004)
+#define  EP4_CTRL_TRANCOUNT_3               ((uint16_t)0x0008)
+#define  EP4_CTRL_TRANCOUNT_4               ((uint16_t)0x0010)
+#define  EP4_CTRL_TRANCOUNT_5               ((uint16_t)0x0020)
+#define  EP4_CTRL_TRANCOUNT_6               ((uint16_t)0x0040)
+
+/*******************  Bit definition for EP_DMA register  *******************/
+#define  EP_DMA_DMA1EN                      ((uint16_t)0x0001)
+#define  EP_DMA_DMA2EN                      ((uint16_t)0x0002)
+
+/*******************  Bit definition for EP_HALT register  *******************/
+#define  EP_HALT_HALT0                      ((uint16_t)0x0001)
+#define  EP_HALT_HALT1                      ((uint16_t)0x0002)
+#define  EP_HALT_HALT2                      ((uint16_t)0x0004)
+#define  EP_HALT_HALT3                      ((uint16_t)0x0008)
+#define  EP_HALT_HALT4                      ((uint16_t)0x0010)
+
+/*******************  Bit definition for USB_POWER register  *******************/
+#define  USB_POWER_SUSPEN                   ((uint16_t)0x0001)
+#define  USB_POWER_SUSP                     ((uint16_t)0x0002)
+#define  USB_POWER_WKUP                     ((uint16_t)0x0008)
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_TXREG register  ********************/
+#define  SPI_TXREG_TXREG                     ((uint32_t)0xFFFFFFFF)
+
+/*******************  Bit definition for SPI_RXREG register  ********************/
+#define  SPI_RXREG_RXREG                     ((uint32_t)0xFFFFFFFF)
+
+/*******************  Bit definition for SPI_CSTAT register  ********************/
+#define  SPI_CSTAT_TXEPT                     ((uint8_t)0x01)
+#define  SPI_CSTAT_RXAVL                     ((uint8_t)0x02)
+#define  SPI_CSTAT_TXFULL                    ((uint8_t)0x04)
+#define  SPI_CSTAT_RXAVL_4BYTE               ((uint8_t)0x08)
+
+/*******************  Bit definition for SPI_INTSTAT register  ********************/
+#define  SPI_INTSTAT_TX_INTF                ((uint16_t)0x0001)
+#define  SPI_INTSTAT_RX_INTF                ((uint16_t)0x0002)
+#define  SPI_INTSTAT_UNDERRUN_INTF          ((uint16_t)0x0004)
+#define  SPI_INTSTAT_RXOERR_INTF            ((uint16_t)0x0008)
+#define  SPI_INTSTAT_RXMATCH_INTF           ((uint16_t)0x0010)
+#define  SPI_INTSTAT_RXFULL_INTF            ((uint16_t)0x0020)
+#define  SPI_INTSTAT_TXEPT_INTF             ((uint16_t)0x0040)
+
+/*******************  Bit definition for SPI_INTEN register  ********************/
+#define  SPI_INTEN_TX_IEN                   ((uint16_t)0x0001)
+#define  SPI_INTEN_RX_IEN                   ((uint16_t)0x0002)
+#define  SPI_INTEN_UNDERRUN_IEN             ((uint16_t)0x0004)
+#define  SPI_INTEN_RXOERR_IEN               ((uint16_t)0x0008)
+#define  SPI_INTEN_RXMATCH_IEN              ((uint16_t)0x0010)
+#define  SPI_INTEN_RXFULL_IEN               ((uint16_t)0x0020)
+#define  SPI_INTEN_TXEPT_IEN                ((uint16_t)0x0040)
+
+/*******************  Bit definition for SPI_INTCLR register  ********************/
+#define  SPI_INTCLR_TX_ICLR                 ((uint16_t)0x0001)
+#define  SPI_INTCLR_RX_ICLR                 ((uint16_t)0x0002)
+#define  SPI_INTCLR_UNDERRUN_ICLR           ((uint16_t)0x0004)
+#define  SPI_INTCLR_RXOERR_ICLR             ((uint16_t)0x0008)
+#define  SPI_INTCLR_RXMATCH_ICLR            ((uint16_t)0x0010)
+#define  SPI_INTCLR_RXFULL_ICLR             ((uint16_t)0x0020)
+#define  SPI_INTCLR_TXEPT_ICLR              ((uint16_t)0x0040)
+
+/*******************  Bit definition for SPI_GCTL register  ********************/
+#define  SPI_GCTL_SPIEN                     ((uint16_t)0x0001)
+#define  SPI_GCTL_INT_EN                    ((uint16_t)0x0002)
+#define  SPI_GCTL_MM                        ((uint16_t)0x0004)
+#define  SPI_GCTL_TXEN                      ((uint16_t)0x0008)
+#define  SPI_GCTL_RXEN                      ((uint16_t)0x0010)
+#define  SPI_GCTL_RXTLF                     ((uint16_t)0x0060)
+#define  SPI_GCTL_TXTLF                     ((uint16_t)0x0180)
+#define  SPI_GCTL_DMAEN                     ((uint16_t)0x0200)
+#define  SPI_GCTL_NSS_SEL                   ((uint16_t)0x0400)
+#define  SPI_GCTL_DATA_SEL                  ((uint16_t)0x0800)
+
+/*******************  Bit definition for SPI_CCTL register  ********************/
+#define  SPI_CCTL_CPHA                      ((uint16_t)0x0001)
+#define  SPI_CCTL_CPOL                      ((uint16_t)0x0002)
+#define  SPI_CCTL_LSBFE                     ((uint16_t)0x0004)
+#define  SPI_CCTL_SPILEN                    ((uint16_t)0x0008)
+#define  SPI_CCTL_RXEDGE                    ((uint16_t)0x0010)
+#define  SPI_CCTL_TXEDGE                    ((uint16_t)0x0020)
+
+/*******************  Bit definition for SPI_SPBRG register  ********************/
+#define  SPI_SPBRG_SPBRG                    ((uint32_t)0xFFFFFFFF)
+
+/*******************  Bit definition for SPI_RXDNR register  ********************/
+#define  SPI_RXDNR_RXDNR                    ((uint32_t)0xFFFFFFFF)
+
+/*******************  Bit definition for SPI_NSSR register  ********************/
+#define  SPI_NSSR_NSS                       ((uint8_t)0x01)
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CON register  ********************/
+#define  I2C_CON_MASTER_MODE                             ((uint16_t)0x0001)
+#define  I2C_CON_10BITADDR_SLAVE                         ((uint16_t)0x0008)
+#define  I2C_CON_10BITADDR_MASTER                        ((uint16_t)0x0010)
+#define  I2C_CON_RESTART_EN                              ((uint16_t)0x0020)
+#define  I2C_CON_SLAVE_DISABLE                           ((uint16_t)0x0040)
+#define  I2C_CON_STOP_DET_IFADDRESSED                    ((uint16_t)0x0080)
+#define  I2C_CON_EMPTY_CTRL                              ((uint16_t)0x0100)
+
+#define  I2C_CON_SPEED                                   ((uint16_t)0x0006)          
+#define  I2C_CON_SPEED_0                                 ((uint16_t)0x0002)
+#define  I2C_CON_SPEED_1                                 ((uint16_t)0x0004)
+
+/*******************  Bit definition for I2C_TAR register  ********************/
+#define  I2C_TAR_GC_OR_START                             ((uint16_t)0x0400)
+#define  I2C_TAR_SPECIAL                                 ((uint16_t)0x0800)
+
+#define  I2C_TAR_TAR                                     ((uint16_t)0x03FF)
+#define  I2C_TAR_TAR_0                                   ((uint16_t)0x0001)
+#define  I2C_TAR_TAR_1                                   ((uint16_t)0x0002)
+#define  I2C_TAR_TAR_2                                   ((uint16_t)0x0004)
+#define  I2C_TAR_TAR_3                                   ((uint16_t)0x0008)
+#define  I2C_TAR_TAR_4                                   ((uint16_t)0x0010)
+#define  I2C_TAR_TAR_5                                   ((uint16_t)0x0020)
+#define  I2C_TAR_TAR_6                                   ((uint16_t)0x0040)
+#define  I2C_TAR_TAR_7                                   ((uint16_t)0x0080)
+#define  I2C_TAR_TAR_8                                   ((uint16_t)0x0100)
+#define  I2C_TAR_TAR_9                                   ((uint16_t)0x0200)
+
+/*******************  Bit definition for I2C_SAR register  ********************/
+#define  I2C_SAR_SAR                                     ((uint16_t)0x03FF)
+
+/*******************  Bit definition for I2C_HS_MADDR register  ********************/
+#define  I2C_HS_MADDR                                    ((uint16_t)0x0007)
+
+/*******************  Bit definition for I2C_DATA_CMD register  ********************/
+#define  I2C_DATA_CMD_CMD                                ((uint16_t)0x0100)
+
+#define  I2C_DATA_CMD_DAT                                ((uint16_t)0x00FF)
+#define  I2C_DATA_CMD_DAT_0                              ((uint16_t)0x0001)
+#define  I2C_DATA_CMD_DAT_1                              ((uint16_t)0x0002)
+#define  I2C_DATA_CMD_DAT_2                              ((uint16_t)0x0004)
+#define  I2C_DATA_CMD_DAT_3                              ((uint16_t)0x0008)
+#define  I2C_DATA_CMD_DAT_4                              ((uint16_t)0x0010)
+#define  I2C_DATA_CMD_DAT_5                              ((uint16_t)0x0020)
+#define  I2C_DATA_CMD_DAT_6                              ((uint16_t)0x0040)
+#define  I2C_DATA_CMD_DAT_7                              ((uint16_t)0x0080)
+
+/*******************  Bit definition for I2C_SS_SCL_HCNT register  ********************/
+#define  I2C_SS_SCL_HCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_SS_SCL_LCNT register  ********************/
+#define  I2C_SS_SCL_LCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_FS_SCL_HCNT register  ********************/
+#define  I2C_FS_SCL_HCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_FS_SCL_LCNT register  ********************/
+#define  I2C_FS_SCL_LCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_FS_SCL_HCNT register  ********************/
+#define  I2C_HS_SCL_HCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_FS_SCL_LCNT register  ********************/
+#define  I2C_HS_SCL_LCNT                                ((uint16_t)0xFFFF)
+
+/*******************  Bit definition for I2C_INTR_STAT register  ********************/
+#define  I2C_INTR_STAT_RX_UNDER                         ((uint16_t)0x0001)
+#define  I2C_INTR_STAT_RX_OVER                          ((uint16_t)0x0002)
+#define  I2C_INTR_STAT_RX_FULL                          ((uint16_t)0x0004)
+#define  I2C_INTR_STAT_TX_OVER                          ((uint16_t)0x0008)
+#define  I2C_INTR_STAT_TX_EMPTY                         ((uint16_t)0x0010)
+#define  I2C_INTR_STAT_RX_REQ                           ((uint16_t)0x0020)
+#define  I2C_INTR_STAT_TX_ABRT                          ((uint16_t)0x0040)
+#define  I2C_INTR_STAT_RX_DONE                          ((uint16_t)0x0080)
+#define  I2C_INTR_STAT_ACTIVITY                         ((uint16_t)0x0100)
+#define  I2C_INTR_STAT_STOP_DET                         ((uint16_t)0x0200)
+#define  I2C_INTR_STAT_START_DET                        ((uint16_t)0x0400)
+#define  I2C_INTR_STAT_GEN_CALL                         ((uint16_t)0x0800)
+#define  I2C_INTR_STAT_RESTART_DET                      ((uint16_t)0x1000)
+#define  I2C_INTR_STAT_MST_ON_HOLD                      ((uint16_t)0x2000)
+
+/*******************  Bit definition for I2C_INTR_MASK register  ********************/
+#define  I2C_INTR_MASK_RX_UNDER                         ((uint16_t)0x0001)
+#define  I2C_INTR_MASK_RX_OVER                          ((uint16_t)0x0002)
+#define  I2C_INTR_MASK_RX_FULL                          ((uint16_t)0x0004)
+#define  I2C_INTR_MASK_TX_OVER                          ((uint16_t)0x0008)
+#define  I2C_INTR_MASK_TX_EMPTY                         ((uint16_t)0x0010)
+#define  I2C_INTR_MASK_RX_REQ                           ((uint16_t)0x0020)
+#define  I2C_INTR_MASK_TX_ABRT                          ((uint16_t)0x0040)
+#define  I2C_INTR_MASK_RX_DONE                          ((uint16_t)0x0080)
+#define  I2C_INTR_MASK_ACTIVITY                         ((uint16_t)0x0100)
+#define  I2C_INTR_MASK_STOP_DET                         ((uint16_t)0x0200)
+#define  I2C_INTR_MASK_START_DET                        ((uint16_t)0x0400)
+#define  I2C_INTR_MASK_GEN_CALL                         ((uint16_t)0x0800)
+#define  I2C_INTR_MASK_RESTART_DET                      ((uint16_t)0x1000)
+#define  I2C_INTR_MASK_MST_ON_HOLD                      ((uint16_t)0x2000)
+
+/*******************  Bit definition for I2C_RAW_INTR_STAT register  ********************/
+#define  I2C_RAW_INTR_MASK_RX_UNDER                         ((uint16_t)0x0001)
+#define  I2C_RAW_INTR_MASK_RX_OVER                          ((uint16_t)0x0002)
+#define  I2C_RAW_INTR_MASK_RX_FULL                          ((uint16_t)0x0004)
+#define  I2C_RAW_INTR_MASK_TX_OVER                          ((uint16_t)0x0008)
+#define  I2C_RAW_INTR_MASK_TX_EMPTY                         ((uint16_t)0x0010)
+#define  I2C_RAW_INTR_MASK_RX_REQ                           ((uint16_t)0x0020)
+#define  I2C_RAW_INTR_MASK_TX_ABRT                          ((uint16_t)0x0040)
+#define  I2C_RAW_INTR_MASK_RX_DONE                          ((uint16_t)0x0080)
+#define  I2C_RAW_INTR_MASK_ACTIVITY                         ((uint16_t)0x0100)
+#define  I2C_RAW_INTR_MASK_STOP_DET                         ((uint16_t)0x0200)
+#define  I2C_RAW_INTR_MASK_START_DET                        ((uint16_t)0x0400)
+#define  I2C_RAW_INTR_MASK_GEN_CALL                         ((uint16_t)0x0800)
+#define  I2C_RAW_INTR_MASK_RESTART_DET                      ((uint16_t)0x1000)
+#define  I2C_RAW_INTR_MASK_MST_ON_HOLD                      ((uint16_t)0x2000)
+
+/*******************  Bit definition for I2C_CLR_INTR register  ********************/
+#define  I2C_CLR_INTR                                       ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_RX_UNDER register  ********************/
+#define  I2C_CLR_RX_UNDER                                   ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_RX_OVER register  ********************/
+#define  I2C_CLR_RX_OVER                                    ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_TX_OVER register  ********************/
+#define  I2C_CLR_TX_OVER                                    ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_RD_REQ register  ********************/
+#define  I2C_CLR_RD_REQ                                     ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_TX_ABRT register  ********************/
+#define  I2C_CLR_TX_ABRT                                    ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_RX_DONE register  ********************/
+#define  I2C_CLR_RX_DONE                                    ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_ACTIVITY register  ********************/
+#define  I2C_CLR_ACTIVITY                                   ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_STOP_DET register  ********************/
+#define  I2C_CLR_STOP_DET                                   ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_START_DET register  ********************/
+#define  I2C_CLR_START_DET                                  ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_CLR_GEN_CALL register  ********************/
+#define  I2C_CLR_GEN_CALL                                   ((uint16_t)0x0001)
+
+/*******************  Bit definition for I2C_ENABLE register  ********************/
+#define  I2C_ENABLE_ENABLE                                  ((uint16_t)0x0001)
+#define  I2C_ENABLE_ABORT                                   ((uint16_t)0x0002)
+
+/*******************  Bit definition for I2C_STATUS register  ********************/
+#define  I2C_STATUS_ACTIVITY                                ((uint16_t)0x0001)
+#define  I2C_STATUS_TFNF                                    ((uint16_t)0x0002)
+#define  I2C_STATUS_TFE                                     ((uint16_t)0x0004)
+#define  I2C_STATUS_RFNE                                    ((uint16_t)0x0008)
+#define  I2C_STATUS_RFF                                     ((uint16_t)0x0010)
+#define  I2C_STATUS_MST_ACTIVITY                            ((uint16_t)0x0020)
+#define  I2C_STATUS_SLV_ACTIVITY                            ((uint16_t)0x0040)
+
+/*******************  Bit definition for I2C_TXFLR register  ********************/
+#define  I2C_TXFLR                                          ((uint16_t)0x0003)
+#define  I2C_TXFLR_0                                        ((uint16_t)0x0001)
+#define  I2C_TXFLR_1                                        ((uint16_t)0x0002)
+
+/*******************  Bit definition for I2C_RXFLR register  ********************/
+#define  I2C_RXFLR                                          ((uint16_t)0x0003)
+#define  I2C_RXFLR_0                                        ((uint16_t)0x0001)
+#define  I2C_RXFLR_1                                        ((uint16_t)0x0002)
+
+/*******************  Bit definition for I2C_SDA_HOLD register  ********************/
+#define  I2C_SDA_TX_HOLD                                    ((uint32_t)0x0000FFFF)
+#define  I2C_SDA_RX_HOLD                                    ((uint32_t)0xFFFF0000)
+
+/*******************  Bit definition for I2C_DMA_CR register  ********************/
+#define  I2C_DMA_CR_RDMAE                                   ((uint16_t)0x0001)
+#define  I2C_DMA_CR_TDMAE                                   ((uint16_t)0x0002)
+
+/*******************  Bit definition for I2C_SDA_SET_UP register  ********************/
+#define  I2C_SDA_SET_UP                                     ((uint16_t)0x00FF)
+
+/*******************  Bit definition for I2C_ACK_GENERAL_CALL register  ********************/
+#define  I2C_ACK_GENERAL_CALL                               ((uint16_t)0x0001)
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for UART_TDR register  *******************/
+#define  UART_TDR_TXREG                         ((uint16_t)0x00FF)
+
+/*******************  Bit definition for UART_RDR register  *******************/
+#define  UART_TDR_RXREG                         ((uint16_t)0x00FF)
+
+/*******************  Bit definition for UART_CSR register  *******************/
+#define  UART_CSR_TXC                           ((uint16_t)0x0001)
+#define  UART_CSR_RXAVL                         ((uint16_t)0x0002)
+#define  UART_CSR_TXFULL                        ((uint16_t)0x0004)
+#define  UART_CSR_TXBUF_EMPTY                   ((uint16_t)0x0008)
+
+/*******************  Bit definition for UART_ISR register  *******************/
+#define  UART_ISR_TX_INTF                       ((uint16_t)0x0001)
+#define  UART_ISR_RX_INTF                       ((uint16_t)0x0002)
+#define  UART_ISR_RXOERR_INTF                   ((uint16_t)0x0008)
+#define  UART_ISR_RXFERR_INTF                   ((uint16_t)0x0010)
+#define  UART_ISR_RXPERR_INTF                   ((uint16_t)0x0020)
+#define  UART_ISR_RXBRK_INFT                    ((uint16_t)0x0040)
+
+/*******************  Bit definition for UART_IER register  *******************/
+#define  UART_IER_TXIEN                         ((uint16_t)0x0001)
+#define  UART_IER_RXIEN                         ((uint16_t)0x0002)
+#define  UART_IER_TIMEOUTEN                     ((uint16_t)0x0004)
+#define  UART_IER_RXOERREN                      ((uint16_t)0x0008)
+#define  UART_IER_RXPERREN                      ((uint16_t)0x0010)
+#define  UART_IER_RXFERREN                      ((uint16_t)0x0020)
+#define  UART_IER_RXBRKEN                       ((uint16_t)0x0040)
+
+/*******************  Bit definition for UART_ICR register  *******************/
+#define  UART_ICR_TXICLR                        ((uint16_t)0x0001)
+#define  UART_ICR_RXICLR                        ((uint16_t)0x0002)
+#define  UART_ICR_TIMEOUTCLR                    ((uint16_t)0x0004)
+#define  UART_ICR_RXOERRCLR                     ((uint16_t)0x0008)
+#define  UART_ICR_RXPERRCLR                     ((uint16_t)0x0010)
+#define  UART_ICR_RXFERRCLR                     ((uint16_t)0x0020)
+#define  UART_ICR_RXBRKCLR                      ((uint16_t)0x0040)
+
+/*******************  Bit definition for UART_GCR register  *******************/
+#define  UART_GCR_UARTEN                        ((uint16_t)0x0001)
+#define  UART_GCR_DMAMODE                       ((uint16_t)0x0002)
+#define  UART_GCR_AUTOFLOWEN                    ((uint16_t)0x0004)
+#define  UART_GCR_RXEN                          ((uint16_t)0x0008)
+#define  UART_GCR_TXEN                          ((uint16_t)0x0010)
+
+/*******************  Bit definition for UART_CCR register  *******************/
+#define  UART_CCR_PEN                           ((uint16_t)0x0001)
+#define  UART_CCR_PSEL                          ((uint16_t)0x0002)
+#define  UART_CCR_SPB                           ((uint16_t)0x0004)
+#define  UART_CCR_BRK                           ((uint16_t)0x0008)
+
+#define  UART_CCR_CHAR                          ((uint16_t)0x0030)
+#define  UART_CCR_CHAR_0                        ((uint16_t)0x0010)
+#define  UART_CCR_CHAR_1                        ((uint16_t)0x0020)
+
+/*******************  Bit definition for UART_BRR register  *******************/
+#define  UART_BRR_SPBRG                         ((uint16_t)0xFFFF)
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 Debug MCU                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0xFFFFFFFF)        /*!<Device Identifier */
+
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!<Debug Sleep Mode */
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!<Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!<Debug Standby mode */
+
+#define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!<Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!<Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!<TIM1 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!<TIM2 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!<TIM3 counter stopped when core is halted */
+#define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!<TIM4 counter stopped when core is halted */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint8_t)0x07)               /*!<LATENCY[2:0] bits (Latency) */
+#define  FLASH_ACR_LATENCY_0                 ((uint8_t)0x01)               /*!<Bit 0 */
+#define  FLASH_ACR_LATENCY_1                 ((uint8_t)0x02)               /*!<Bit 0 */
+#define  FLASH_ACR_LATENCY_2                 ((uint8_t)0x04)               /*!<Bit 1 */
+
+#define  FLASH_ACR_HLFCYA                    ((uint8_t)0x08)               /*!<Flash Half Cycle Access Enable */
+#define  FLASH_ACR_PRFTBE                    ((uint8_t)0x10)               /*!<Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint8_t)0x20)               /*!<Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!<FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!<Option Byte Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint8_t)0x01)               /*!<Busy */
+#define  FLASH_SR_PGERR                      ((uint8_t)0x04)               /*!<Programming Error */
+#define  FLASH_SR_WRPRTERR                   ((uint8_t)0x10)               /*!<Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint8_t)0x20)               /*!<End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint16_t)0x0001)            /*!<Programming */
+#define  FLASH_CR_PER                        ((uint16_t)0x0002)            /*!<Page Erase */
+#define  FLASH_CR_MER                        ((uint16_t)0x0004)            /*!<Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint16_t)0x0010)            /*!<Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint16_t)0x0020)            /*!<Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint16_t)0x0040)            /*!<Start */
+#define  FLASH_CR_LOCK                       ((uint16_t)0x0080)            /*!<Lock */
+#define  FLASH_CR_OPTWRE                     ((uint16_t)0x0200)            /*!<Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint16_t)0x0400)            /*!<Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint16_t)0x1000)            /*!<End of operation interrupt enable */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!<Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint16_t)0x0001)            /*!<Option Byte Error */
+#define  FLASH_OBR_RDPRT                     ((uint16_t)0x0002)            /*!<Read protection */
+
+#define  FLASH_OBR_USER                      ((uint16_t)0x03FC)            /*!<User Option Bytes */
+#define  FLASH_OBR_WDG_SW                    ((uint16_t)0x0004)            /*!<WDG_SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint16_t)0x0008)            /*!<nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint16_t)0x0010)            /*!<nRST_STDBY */
+//#define  FLASH_OBR_Notused                   ((uint16_t)0x03E0)            /*!<Not used */           //by   chenhui
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                        ((uint32_t)0xFFFFFFFF)        /*!<Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   CAN Registers and bits                   */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CAN_CMR register  *******************/
+#define  CAN_CMR_TR                          ((uint16_t)0x0001)
+#define  CAN_CMR_AT                          ((uint16_t)0x0002)
+#define  CAN_CMR_RRB                         ((uint16_t)0x0004)
+#define  CAN_CMR_CDO                         ((uint16_t)0x0008)
+#define  CAN_CMR_GTS                         ((uint16_t)0x0010)
+
+/*******************  Bit definition for CAN_SR register  *******************/
+#define  CAN_SR_RBS                          ((uint16_t)0x0001)
+#define  CAN_SR_DOS                          ((uint16_t)0x0002)
+#define  CAN_SR_TBS                          ((uint16_t)0x0004)
+#define  CAN_SR_TCS                          ((uint16_t)0x0008)
+#define  CAN_SR_RS                           ((uint16_t)0x0010)
+#define  CAN_SR_TS                           ((uint16_t)0x0020)
+#define  CAN_SR_ES                           ((uint16_t)0x0040)
+#define  CAN_SR_BS                           ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_IR register  *******************/
+#define  CAN_IR_RI                           ((uint16_t)0x0001)
+#define  CAN_IR_TI                           ((uint16_t)0x0002)
+#define  CAN_IR_EI                           ((uint16_t)0x0004)
+#define  CAN_IR_DOI                          ((uint16_t)0x0008)
+#define  CAN_IR_WUI                          ((uint16_t)0x0010)
+#define  CAN_IR_EPI                          ((uint16_t)0x0020) /*PeliCAN*/
+#define  CAN_IR_ALI                          ((uint16_t)0x0040) /*PeliCAN*/
+#define  CAN_IR_BEI                          ((uint16_t)0x0080) /*PeliCAN*/
+
+/*******************  Bit definition for CAN_BTR0 register  *******************/
+#define  CAN_BTR0_BRP                        ((uint16_t)0x003F)
+#define  CAN_BTR0_BRP_0                      ((uint16_t)0x0001)
+#define  CAN_BTR0_BRP_1                      ((uint16_t)0x0002)
+#define  CAN_BTR0_BRP_2                      ((uint16_t)0x0004)
+#define  CAN_BTR0_BRP_3                      ((uint16_t)0x0008)
+#define  CAN_BTR0_BRP_4                      ((uint16_t)0x0010)
+#define  CAN_BTR0_BRP_5                      ((uint16_t)0x0020)
+
+#define  CAN_BTR0_SJW                        ((uint16_t)0x00C0)
+#define  CAN_BTR0_SJW_0                      ((uint16_t)0x0040)
+#define  CAN_BTR0_SJW_1                      ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_BTR1 register  *******************/
+#define  CAN_BTR1_SAM                        ((uint16_t)0x0080)
+
+#define  CAN_BTR1_TSEG1                      ((uint16_t)0x000F)
+#define  CAN_BTR1_TSEG1_0                    ((uint16_t)0x0001)
+#define  CAN_BTR1_TSEG1_1                    ((uint16_t)0x0002)
+#define  CAN_BTR1_TSEG1_2                    ((uint16_t)0x0004)
+#define  CAN_BTR1_TSEG1_3                    ((uint16_t)0x0008)
+
+#define  CAN_BTR1_TSEG2                      ((uint16_t)0x0070)
+#define  CAN_BTR1_TSEG2_0                    ((uint16_t)0x0010)
+#define  CAN_BTR1_TSEG2_1                    ((uint16_t)0x0020)
+#define  CAN_BTR1_TSEG2_2                    ((uint16_t)0x0040)
+
+/*******************  Bit definition for CAN_CDR register  *******************/
+#define  CAN_CDR_MODE                        ((uint16_t)0x0080)
+
+/*!<BasicCAN registers */
+/*******************  Bit definition for CAN_CR register  *******************/
+#define  CAN_CR_RR                           ((uint16_t)0x0001)
+#define  CAN_CR_RIE                          ((uint16_t)0x0002)
+#define  CAN_CR_TIE                          ((uint16_t)0x0004)
+#define  CAN_CR_EIE                          ((uint16_t)0x0008)
+#define  CAN_CR_OIE                          ((uint16_t)0x0010)
+
+/*******************  Bit definition for CAN_ACR register  *******************/
+#define  CAN_ACR_AC                          ((uint16_t)0x00FF)
+#define  CAN_ACR_AC_0                        ((uint16_t)0x0001)
+#define  CAN_ACR_AC_1                        ((uint16_t)0x0002)
+#define  CAN_ACR_AC_2                        ((uint16_t)0x0004)
+#define  CAN_ACR_AC_3                        ((uint16_t)0x0008)
+#define  CAN_ACR_AC_4                        ((uint16_t)0x0010)
+#define  CAN_ACR_AC_5                        ((uint16_t)0x0020)
+#define  CAN_ACR_AC_6                        ((uint16_t)0x0040)
+#define  CAN_ACR_AC_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_AMR register  *******************/
+#define  CAN_AMR_AM                          ((uint16_t)0x00FF)
+#define  CAN_AMR_AM_0                        ((uint16_t)0x0001)
+#define  CAN_AMR_AM_1                        ((uint16_t)0x0002)
+#define  CAN_AMR_AM_2                        ((uint16_t)0x0004)
+#define  CAN_AMR_AM_3                        ((uint16_t)0x0008)
+#define  CAN_AMR_AM_4                        ((uint16_t)0x0010)
+#define  CAN_AMR_AM_5                        ((uint16_t)0x0020)
+#define  CAN_AMR_AM_6                        ((uint16_t)0x0040)
+#define  CAN_AMR_AM_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_TXID1 register  *******************/
+#define  CAN_TXID1_ID                        ((uint16_t)0x00FF)
+#define  CAN_TXID1_ID_3                      ((uint16_t)0x0001)
+#define  CAN_TXID1_ID_4                      ((uint16_t)0x0002)
+#define  CAN_TXID1_ID_5                      ((uint16_t)0x0004)
+#define  CAN_TXID1_ID_6                      ((uint16_t)0x0008)
+#define  CAN_TXID1_ID_7                      ((uint16_t)0x0010)
+#define  CAN_TXID1_ID_8                      ((uint16_t)0x0020)
+#define  CAN_TXID1_ID_9                      ((uint16_t)0x0040)
+#define  CAN_TXID1_ID_10                     ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_TXID2 register  *******************/
+#define  CAN_TXID2_RTR                       ((uint16_t)0x0010)
+
+#define  CAN_TXID2_DLC                       ((uint16_t)0x000F)
+#define  CAN_TXID2_DLC_0                     ((uint16_t)0x0001)
+#define  CAN_TXID2_DLC_1                     ((uint16_t)0x0002)
+#define  CAN_TXID2_DLC_2                     ((uint16_t)0x0004)
+#define  CAN_TXID2_DLC_3                     ((uint16_t)0x0008)
+
+#define  CAN_TXID2_ID                        ((uint16_t)0x00E0)
+#define  CAN_TXID2_ID_0                      ((uint16_t)0x0020)
+#define  CAN_TXID2_ID_1                      ((uint16_t)0x0040)
+#define  CAN_TXID2_ID_2                      ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_TXDR0 register  *******************/
+#define  CAN_TXDR0                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR1 register  *******************/
+#define  CAN_TXDR1                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR2 register  *******************/
+#define  CAN_TXDR2                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR3 register  *******************/
+#define  CAN_TXDR3                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR4 register  *******************/
+#define  CAN_TXDR4                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR5 register  *******************/
+#define  CAN_TXDR5                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR6 register  *******************/
+#define  CAN_TXDR6                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_TXDR7 register  *******************/
+#define  CAN_TXDR7                           ((uint16_t)0x00FF)
+
+/*******************  Bit definition for CAN_RXID1 register  *******************/
+#define  CAN_RXID1_ID                        ((uint16_t)0x00FF)
+#define  CAN_RXID1_ID_3                      ((uint16_t)0x0001)
+#define  CAN_RXID1_ID_4                      ((uint16_t)0x0002)
+#define  CAN_RXID1_ID_5                      ((uint16_t)0x0004)
+#define  CAN_RXID1_ID_6                      ((uint16_t)0x0008)
+#define  CAN_RXID1_ID_7                      ((uint16_t)0x0010)
+#define  CAN_RXID1_ID_8                      ((uint16_t)0x0020)
+#define  CAN_RXID1_ID_9                      ((uint16_t)0x0040)
+#define  CAN_RXID1_ID_10                     ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_RXID2 register  *******************/
+#define  CAN_RXID2_RTR                       ((uint16_t)0x0010)
+
+#define  CAN_RXID2_DLC                       ((uint16_t)0x000F)
+#define  CAN_RXID2_DLC_0                     ((uint16_t)0x0001)
+#define  CAN_RXID2_DLC_1                     ((uint16_t)0x0002)
+#define  CAN_RXID2_DLC_2                     ((uint16_t)0x0004)
+#define  CAN_RXID2_DLC_3                     ((uint16_t)0x0008)
+
+#define  CAN_RXID2_ID                        ((uint16_t)0x00E0)
+#define  CAN_RXID2_ID_0                      ((uint16_t)0x0020)
+#define  CAN_RXID2_ID_1                      ((uint16_t)0x0040)
+#define  CAN_RXID2_ID_2                      ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_RXDR0 register  *******************/
+#define  CAN_RXDR0                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR1 register  *******************/
+#define  CAN_RXDR1                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR2 register  *******************/
+#define  CAN_RXDR2                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR3 register  *******************/
+#define  CAN_RXDR3                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR4 register  *******************/
+#define  CAN_RXDR4                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR5 register  *******************/
+#define  CAN_RXDR5                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR6 register  *******************/
+#define  CAN_RXDR6                           ((uint16_t)0x00FF)
+/*******************  Bit definition for CAN_RXDR7 register  *******************/
+#define  CAN_RXDR7                           ((uint16_t)0x00FF)
+
+/*!<PeliCAN registers */
+/*******************  Bit definition for CAN_MOD register  *******************/
+#define  CAN_MOD_RM							 ((uint16_t)0x0001)
+#define  CAN_MOD_LOM						 ((uint16_t)0x0002)
+#define  CAN_MOD_STM						 ((uint16_t)0x0004)
+#define  CAN_MOD_AFM						 ((uint16_t)0x0008)
+#define  CAN_MOD_SM							 ((uint16_t)0x0010)
+
+/*******************  Bit definition for CAN_IER register  *******************/
+#define  CAN_IER_RIE							 ((uint16_t)0x0001)
+#define  CAN_IER_TIE							 ((uint16_t)0x0002)
+#define  CAN_IER_EIE							 ((uint16_t)0x0004)
+#define  CAN_IER_DOIE							 ((uint16_t)0x0008)
+#define  CAN_IER_WUIE							 ((uint16_t)0x0010)
+#define  CAN_IER_EPIE							 ((uint16_t)0x0020)
+#define  CAN_IER_ALIE							 ((uint16_t)0x0040)
+#define  CAN_IER_BEIE							 ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_ALC register  *******************/
+#define  CAN_ALC_BITNO							 ((uint16_t)0x001F)
+#define  CAN_ALC_BITNO_0						 ((uint16_t)0x0001)
+#define  CAN_ALC_BITNO_1						 ((uint16_t)0x0002)
+#define  CAN_ALC_BITNO_2						 ((uint16_t)0x0004)
+#define  CAN_ALC_BITNO_3						 ((uint16_t)0x0008)
+#define  CAN_ALC_BITNO_4						 ((uint16_t)0x0010)
+
+/*******************  Bit definition for CAN_ECC register  *******************/
+#define  CAN_ECC_DIR							 ((uint16_t)0x0020)
+
+#define  CAN_ECC_SEG							 ((uint16_t)0x001F)
+#define  CAN_ECC_SEG_0							 ((uint16_t)0x0001)
+#define  CAN_ECC_SEG_1							 ((uint16_t)0x0002)
+#define  CAN_ECC_SEG_2							 ((uint16_t)0x0004)
+#define  CAN_ECC_SEG_3							 ((uint16_t)0x0008)
+#define  CAN_ECC_SEG_4							 ((uint16_t)0x0010)
+
+#define  CAN_ECC_ERRC							 ((uint16_t)0x00C0)
+#define  CAN_ECC_ERRC_0							 ((uint16_t)0x0040)
+#define  CAN_ECC_ERRC_1							 ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_EWLR register  *******************/
+#define  CAN_EWLR_EWL							 ((uint16_t)0x00FF)
+
+/*******************  Bit definition for CAN_RXERR register  *******************/
+#define  CAN_RXERR_RXERR						 ((uint16_t)0x00FF)
+
+/*******************  Bit definition for CAN_TXERR register  *******************/
+#define  CAN_TXERR_TXERR						 ((uint16_t)0x00FF)
+
+/*******************  Bit definition for CAN_FF register  *******************/
+#define  CAN_FF_RTR						         ((uint16_t)0x0040)
+#define  CAN_FF_FF						         ((uint16_t)0x0080)
+
+#define  CAN_FF_DLC						         ((uint16_t)0x000F)
+#define  CAN_FF_DLC_0						     ((uint16_t)0x0001)
+#define  CAN_FF_DLC_1						     ((uint16_t)0x0002)
+#define  CAN_FF_DLC_2						     ((uint16_t)0x0004)
+#define  CAN_FF_DLC_3						     ((uint16_t)0x0008)
+
+/*******************  Bit definition for CAN_ACR0 register  *******************/
+#define  CAN_ACR0_AC                          ((uint16_t)0x00FF)
+#define  CAN_ACR0_AC_0                        ((uint16_t)0x0001)
+#define  CAN_ACR0_AC_1                        ((uint16_t)0x0002)
+#define  CAN_ACR0_AC_2                        ((uint16_t)0x0004)
+#define  CAN_ACR0_AC_3                        ((uint16_t)0x0008)
+#define  CAN_ACR0_AC_4                        ((uint16_t)0x0010)
+#define  CAN_ACR0_AC_5                        ((uint16_t)0x0020)
+#define  CAN_ACR0_AC_6                        ((uint16_t)0x0040)
+#define  CAN_ACR0_AC_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_ACR1 register  *******************/
+#define  CAN_ACR1_AC                          ((uint16_t)0x00FF)
+#define  CAN_ACR1_AC_0                        ((uint16_t)0x0001)
+#define  CAN_ACR1_AC_1                        ((uint16_t)0x0002)
+#define  CAN_ACR1_AC_2                        ((uint16_t)0x0004)
+#define  CAN_ACR1_AC_3                        ((uint16_t)0x0008)
+#define  CAN_ACR1_AC_4                        ((uint16_t)0x0010)
+#define  CAN_ACR1_AC_5                        ((uint16_t)0x0020)
+#define  CAN_ACR1_AC_6                        ((uint16_t)0x0040)
+#define  CAN_ACR1_AC_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_ACR2 register  *******************/
+#define  CAN_ACR2_AC                          ((uint16_t)0x00FF)
+#define  CAN_ACR2_AC_0                        ((uint16_t)0x0001)
+#define  CAN_ACR2_AC_1                        ((uint16_t)0x0002)
+#define  CAN_ACR2_AC_2                        ((uint16_t)0x0004)
+#define  CAN_ACR2_AC_3                        ((uint16_t)0x0008)
+#define  CAN_ACR2_AC_4                        ((uint16_t)0x0010)
+#define  CAN_ACR2_AC_5                        ((uint16_t)0x0020)
+#define  CAN_ACR2_AC_6                        ((uint16_t)0x0040)
+#define  CAN_ACR2_AC_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_ACR3 register  *******************/
+#define  CAN_ACR3_AC                          ((uint16_t)0x00FF)
+#define  CAN_ACR3_AC_0                        ((uint16_t)0x0001)
+#define  CAN_ACR3_AC_1                        ((uint16_t)0x0002)
+#define  CAN_ACR3_AC_2                        ((uint16_t)0x0004)
+#define  CAN_ACR3_AC_3                        ((uint16_t)0x0008)
+#define  CAN_ACR3_AC_4                        ((uint16_t)0x0010)
+#define  CAN_ACR3_AC_5                        ((uint16_t)0x0020)
+#define  CAN_ACR3_AC_6                        ((uint16_t)0x0040)
+#define  CAN_ACR3_AC_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_AMR0 register  *******************/
+#define  CAN_AMR0_AM                          ((uint16_t)0x00FF)
+#define  CAN_AMR0_AM_0                        ((uint16_t)0x0001)
+#define  CAN_AMR0_AM_1                        ((uint16_t)0x0002)
+#define  CAN_AMR0_AM_2                        ((uint16_t)0x0004)
+#define  CAN_AMR0_AM_3                        ((uint16_t)0x0008)
+#define  CAN_AMR0_AM_4                        ((uint16_t)0x0010)
+#define  CAN_AMR0_AM_5                        ((uint16_t)0x0020)
+#define  CAN_AMR0_AM_6                        ((uint16_t)0x0040)
+#define  CAN_AMR0_AM_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_AMR1 register  *******************/
+#define  CAN_AMR1_AM                          ((uint16_t)0x00FF)
+#define  CAN_AMR1_AM_0                        ((uint16_t)0x0001)
+#define  CAN_AMR1_AM_1                        ((uint16_t)0x0002)
+#define  CAN_AMR1_AM_2                        ((uint16_t)0x0004)
+#define  CAN_AMR1_AM_3                        ((uint16_t)0x0008)
+#define  CAN_AMR1_AM_4                        ((uint16_t)0x0010)
+#define  CAN_AMR1_AM_5                        ((uint16_t)0x0020)
+#define  CAN_AMR1_AM_6                        ((uint16_t)0x0040)
+#define  CAN_AMR1_AM_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_AMR2 register  *******************/
+#define  CAN_AMR2_AM                          ((uint16_t)0x00FF)
+#define  CAN_AMR2_AM_0                        ((uint16_t)0x0001)
+#define  CAN_AMR2_AM_1                        ((uint16_t)0x0002)
+#define  CAN_AMR2_AM_2                        ((uint16_t)0x0004)
+#define  CAN_AMR2_AM_3                        ((uint16_t)0x0008)
+#define  CAN_AMR2_AM_4                        ((uint16_t)0x0010)
+#define  CAN_AMR2_AM_5                        ((uint16_t)0x0020)
+#define  CAN_AMR2_AM_6                        ((uint16_t)0x0040)
+#define  CAN_AMR2_AM_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_AMR3 register  *******************/
+#define  CAN_AMR3_AM                          ((uint16_t)0x00FF)
+#define  CAN_AMR3_AM_0                        ((uint16_t)0x0001)
+#define  CAN_AMR3_AM_1                        ((uint16_t)0x0002)
+#define  CAN_AMR3_AM_2                        ((uint16_t)0x0004)
+#define  CAN_AMR3_AM_3                        ((uint16_t)0x0008)
+#define  CAN_AMR3_AM_4                        ((uint16_t)0x0010)
+#define  CAN_AMR3_AM_5                        ((uint16_t)0x0020)
+#define  CAN_AMR3_AM_6                        ((uint16_t)0x0040)
+#define  CAN_AMR3_AM_7                        ((uint16_t)0x0080)
+
+/*******************  Bit definition for CAN_RMC register  *******************/
+#define  CAN_RMC_RMC                          ((uint16_t)0x001F)
+
+/*******************  Bit definition for CAN_RBSA register  *******************/
+#define  CAN_RBSA_RBSA                        ((uint16_t)0x003F)
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+#ifdef USE_STDPERIPH_DRIVER
+#include "HAL_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+* @{
+*/
+
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
+
+
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+* @brief  The assert_param macro is used for function's parameters check.
+* @param expr: If expr is false, it calls assert_failed function
+*   which reports the name of the source file and the source
+*   line number of the call that failed.
+*   If expr is true, it returns no value.
+* @retval : None
+*/
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+/**
+* @}
+*/
+
+#endif /* __MM32F103_H */
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/MM32F103/Include/SYSTEM_MM32F103.h

@@ -0,0 +1,41 @@
+/**
+******************************************************************************
+* @file    system_MM32F103.h
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System head File.
+******************************************************************************
+* @copy
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+*/
+#ifndef __SYSTEM_MM32F103_H__
+#define __SYSTEM_MM32F103_H__
+
+
+extern uint32_t SystemCoreClock;
+void SystemInit (void);
+
+#endif /* __SYSTEM_MM32F103_H__ */
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/
+

bsp/mm32f103x/Libraries/MM32F103/Source/IAR_StartAsm/startup_MM32F103.s

@@ -0,0 +1,333 @@
+;******************** (C) COPYRIGHT 2019 MindMotion ********************
+;* File Name          : startup_MM32F103.s
+;* Author             : AE Team
+;* Version            : V1.1.0
+;* Date               : 28/08/2019
+;* Description        : MM32F103 Medium-density devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address
+;*                      - Configure the system clock
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_IRQHandler         ; Tamper
+        DCD     RTC_IRQHandler            ; RTC
+        DCD     FLASH_IRQHandler          ; Flash
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_2_IRQHandler         ; ADC1 & ADC2
+        DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+        DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+        DCD     CAN1_RX1_IRQHandler       ; CAN1 RX1
+        DCD     CAN1_SCE_IRQHandler       ; CAN1 SCE
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     TIM1_BRK_IRQHandler       ; TIM1 Break
+        DCD     TIM1_UP_IRQHandler        ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler   ; TIM1 Trigger and Commutation
+        DCD     TIM1_CC_IRQHandler        ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     UART1_IRQHandler          ; UART1
+        DCD     UART2_IRQHandler          ; UART2
+        DCD     UART3_IRQHandler          ; UART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTCAlarm_IRQHandler       ; RTC Alarm through EXTI Line
+        DCD     USBWakeUp_IRQHandler      ; USB Wakeup from suspend
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        PUBWEAK TAMPER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TAMPER_IRQHandler
+        B TAMPER_IRQHandler
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        PUBWEAK ADC1_2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_2_IRQHandler
+        B ADC1_2_IRQHandler
+        PUBWEAK USB_HP_CAN1_TX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_HP_CAN1_TX_IRQHandler
+        B USB_HP_CAN1_TX_IRQHandler
+        PUBWEAK USB_LP_CAN1_RX0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_LP_CAN1_RX0_IRQHandler
+        B USB_LP_CAN1_RX0_IRQHandler
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_RX1_IRQHandler
+        B CAN1_RX1_IRQHandler
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_SCE_IRQHandler
+        B CAN1_SCE_IRQHandler
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+        PUBWEAK RTCAlarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTCAlarm_IRQHandler
+        B RTCAlarm_IRQHandler
+        PUBWEAK USBWakeUp_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USBWakeUp_IRQHandler
+        B USBWakeUp_IRQHandler
+
+        END
+;******************** (C) COPYRIGHT 2019 MindMotion ********************

bsp/mm32f103x/Libraries/MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s

@@ -0,0 +1,299 @@
+;******************** (C) COPYRIGHT 2019 MindMotion ********************
+;* File Name          : startup_MM32F103.s
+;* Author             : AE Team
+;* Version            : V1.1.0
+;* Date               : 28/08/2019
+;* Description        : MM32F103 Medium-density devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address
+;*                      - Configure the system clock
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler            ; Window Watchdog
+                DCD     PVD_IRQHandler             ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler          ; Tamper
+                DCD     RTC_IRQHandler             ; RTC
+                DCD     FLASH_IRQHandler           ; Flash
+                DCD     RCC_IRQHandler             ; RCC
+                DCD     EXTI0_IRQHandler           ; EXTI Line 0
+                DCD     EXTI1_IRQHandler           ; EXTI Line 1
+                DCD     EXTI2_IRQHandler           ; EXTI Line 2
+                DCD     EXTI3_IRQHandler           ; EXTI Line 3
+                DCD     EXTI4_IRQHandler           ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler   ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler   ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler   ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler   ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler   ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler   ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler   ; DMA1 Channel 7
+                DCD     ADC1_2_IRQHandler          ; ADC1_2
+                DCD     USB_HP_CAN1_TX_IRQHandler  ; USB High Priority or CAN1 TX
+                DCD     USB_LP_CAN1_RX0_IRQHandler ; USB Low  Priority or CAN1 RX0
+                DCD     CAN1_RX1_IRQHandler        ; CAN1 RX1
+                DCD     CAN1_SCE_IRQHandler        ; CAN1 SCE
+                DCD     EXTI9_5_IRQHandler         ; EXTI Line 9..5
+                DCD     TIM1_BRK_IRQHandler        ; TIM1 Break
+                DCD     TIM1_UP_IRQHandler         ; TIM1 Update
+                DCD     TIM1_TRG_COM_IRQHandler    ; TIM1 Trigger and Commutation
+                DCD     TIM1_CC_IRQHandler         ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler            ; TIM2
+                DCD     TIM3_IRQHandler            ; TIM3
+                DCD     TIM4_IRQHandler            ; TIM4
+                DCD     I2C1_EV_IRQHandler         ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler         ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler         ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler         ; I2C2 Error
+                DCD     SPI1_IRQHandler            ; SPI1
+                DCD     SPI2_IRQHandler            ; SPI2
+                DCD     UART1_IRQHandler           ; UART1
+                DCD     UART2_IRQHandler           ; UART2
+                DCD     UART3_IRQHandler           ; UART3
+                DCD     EXTI15_10_IRQHandler       ; EXTI Line 15..10
+                DCD     RTCAlarm_IRQHandler        ; RTC Alarm through EXTI Line 17
+                DCD     USBWakeUp_IRQHandler       ; USB Wakeup from suspend
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_IRQHandler          [WEAK]
+                EXPORT  RTC_IRQHandler             [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_2_IRQHandler          [WEAK]
+                EXPORT  USB_HP_CAN1_TX_IRQHandler  [WEAK]
+                EXPORT  USB_LP_CAN1_RX0_IRQHandler [WEAK]
+                EXPORT  CAN1_RX1_IRQHandler        [WEAK]
+                EXPORT  CAN1_SCE_IRQHandler        [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler        [WEAK]
+                EXPORT  TIM1_UP_IRQHandler         [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler    [WEAK]
+                EXPORT  TIM1_CC_IRQHandler         [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  UART1_IRQHandler           [WEAK]
+                EXPORT  UART2_IRQHandler           [WEAK]
+                EXPORT  UART3_IRQHandler           [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTCAlarm_IRQHandler        [WEAK]
+                EXPORT  USBWakeUp_IRQHandler       [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_IRQHandler
+RTC_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+USB_HP_CAN1_TX_IRQHandler
+USB_LP_CAN1_RX0_IRQHandler
+CAN1_RX1_IRQHandler
+CAN1_SCE_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+EXTI15_10_IRQHandler
+RTCAlarm_IRQHandler
+USBWakeUp_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB           
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************** (C) COPYRIGHT 2019 MindMotion ********************

bsp/mm32f103x/Libraries/MM32F103/Source/system_MM32F103.c

@@ -0,0 +1,965 @@
+/**
+******************************************************************************
+* @file    system_MM32F103.c
+* @author  AE Team
+* @version V1.1.0
+* @date    28/08/2019
+* @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+*
+* 1.  This file provides two functions and one global variable to be called from
+*     user application:
+*      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+*                      factors, AHB/APBx prescalers and Flash settings).
+*                      This function is called at startup just after reset and
+*                      before branch to main program. This call is made inside
+*                      the "startup_MM32F103.s" file.
+*
+*      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+*                                  by the user application to setup the SysTick
+*                                  timer or configure other parameters.
+*
+*      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+*                                 be called whenever the core clock is changed
+*                                 during program execution.
+*
+* 2. After each device reset the HSI (8 MHz) is used as system clock source.
+*    Then SystemInit() function is casslled, in "startup_MM32F103.s" file, to
+*    configure the system clock before to branch to main program.
+*
+* 3. If the system clock source selected by user fails to startup, the SystemInit()
+*    function will do nothing and HSI still used as system clock source. User can
+*    add some code to deal with this issue inside the SetSysClock() function.
+*
+* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
+*    the product used), refer to "HSE_VALUE" define in "MM32F103.h" file.
+*    When HSE is used as system clock source, directly or through PLL, and you
+*    are using different crystal you have to adapt the HSE value to your own
+*    configuration.
+*
+******************************************************************************
+*
+* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+* TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
+* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+*
+* <h2><center>&copy; COPYRIGHT 2019 MindMotion</center></h2>
+******************************************************************************
+*/
+
+/** @addtogroup CMSIS
+* @{
+*/
+#include "HAL_device.h"
+
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
+frequency (after reset the HSI is used as SYSCLK source)
+
+IMPORTANT NOTE:
+==============
+1. After each device reset the HSI is used as System clock source.
+
+2. Please make sure that the selected System clock doesn't exceed your device's
+maximum frequency.
+
+3. If none of the define below is enabled, the HSI is used as System clock
+source.
+
+4. The System clock configuration functions provided within this file assume that:
+- For Low, Medium and High density Value line devices an external 8MHz
+crystal is used to drive the System clock.
+- For Low, Medium and High density devices an external 8MHz crystal is
+used to drive the System clock.
+- For Connectivity line devices an external 25MHz crystal is used to drive
+the System clock.
+If you are using different crystal you have to adapt those functions accordingly.
+*/
+
+//#define SYSCLK_FREQ_HSE    HSE_VALUE
+//#define SYSCLK_FREQ_24MHz  24000000
+//#define SYSCLK_FREQ_36MHz  36000000
+//#define SYSCLK_FREQ_48MHz  48000000
+//#define SYSCLK_FREQ_56MHz  56000000
+//#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+
+//#define SYSCLK_HSI_48MHz  48000000
+//#define SYSCLK_HSI_72MHz  72000000
+#define SYSCLK_HSI_96MHz  96000000
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+Internal SRAM. */
+//#define VECT_TAB_SRAM
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+This value must be a multiple of 0x200. */
+
+/**
+* @}
+*/
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#ifdef SYSCLK_FREQ_HSE
+uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_36MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_96MHz
+uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_HSI_48MHz
+uint32_t SystemCoreClock         = SYSCLK_HSI_48MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_HSI_72MHz
+uint32_t SystemCoreClock         = SYSCLK_HSI_72MHz;        /*!< System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_HSI_96MHz
+uint32_t SystemCoreClock         = SYSCLK_HSI_96MHz;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+uint32_t SystemCoreClock         = HSI_VALUE_PLL_OFF;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+/**
+* @}
+*/
+
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_36MHz
+static void SetSysClockTo36(void);
+#elif defined SYSCLK_FREQ_48MHz
+static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+static void SetSysClockTo72(void);
+#elif defined SYSCLK_FREQ_96MHz
+static void SetSysClockTo96(void);
+
+#elif defined SYSCLK_HSI_48MHz
+static void SetSysClockTo48_HSI(void);
+#elif defined SYSCLK_HSI_72MHz
+static void SetSysClockTo72_HSI(void);
+#elif defined SYSCLK_HSI_96MHz
+static void SetSysClockTo96_HSI(void);
+#endif
+
+#ifdef DATA_IN_ExtSRAM
+static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+* @}
+*/
+
+/**
+* @brief  Setup the microcontroller system
+*         Initialize the Embedded Flash Interface, the PLL and update the
+*         SystemCoreClock variable.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+void SystemInit (void)
+{
+    /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+    /* Set HSION bit */
+    RCC->CR |= (uint32_t)0x00000001;
+
+    /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+    RCC->CFGR &= (uint32_t)0xF8FF000C;
+
+    /* Reset HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+    RCC->CFGR &= (uint32_t)0xFF80FFFF;
+    RCC->CR &= (uint32_t)0x000FFFFF;
+
+    /* Disable all interrupts and clear pending bits  */
+    RCC->CIR = 0x009F0000;
+
+    /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+    /* Configure the Flash Latency cycles and enable prefetch buffer */
+    SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+* @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+* @param  None
+* @retval None
+*/
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+    SetSysClockTo24();
+#elif defined SYSCLK_FREQ_36MHz
+    SetSysClockTo36();
+#elif defined SYSCLK_FREQ_48MHz
+    SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+    SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+    SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+    SetSysClockTo96();
+
+#elif defined SYSCLK_HSI_48MHz
+    SetSysClockTo48_HSI();
+#elif defined SYSCLK_HSI_72MHz
+    SetSysClockTo72_HSI();
+#elif defined SYSCLK_HSI_96MHz
+    SetSysClockTo96_HSI();
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+    source (default after reset) */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+/**
+* @brief  Selects HSE as System clock source and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockToHSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+        /* Select HSE as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+#elif defined SYSCLK_FREQ_24MHz
+/**
+* @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo24(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x01;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+        /*  PLL configuration:  = (HSE ) * (2+1) = 24 MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
+        RCC->CR |= 0x08000000;//pll=3/1
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+#elif defined SYSCLK_FREQ_36MHz
+/**
+* @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo36(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x01;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+        /*  PLL configuration:  = (HSE ) * (8+1)/(1+1) = 36 MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
+        RCC->CR |= 0x20100000;//pll = 9/2
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+#elif defined SYSCLK_FREQ_48MHz
+/**
+* @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo48(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x01;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+        /*  PLL configuration:  = (HSE ) * (5+1) = 48MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t ) RCC_CFGR_PLLSRC ;
+        RCC->CR |= 0x14000000;//pll = 6/1
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+/**
+* @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo56(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x02;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+        /*  PLL configuration:  = (HSE ) * (6+1) = 56 MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
+        RCC->CR |= 0x18000000;//pll = 7/1
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+/**
+* @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo72(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    u16 i = 0;
+    int nTime = 2;
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 750;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x03;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+        /*  PLL configuration:  = (HSE ) * (8+1) = 72 MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
+        //    RCC->CR |= 0x20000000;//pll = 9/1
+        RCC->CR |= (1 << 20) | (17 << 26); //pll = 9/1
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+
+#elif defined SYSCLK_FREQ_96MHz
+/**
+* @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2
+*          and PCLK1 prescalers.
+* @note   This function should be used only after reset.
+* @param  None
+* @retval None
+*/
+static void SetSysClockTo96(void)
+{
+    int i = 100000;
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+    int nTime = 2;
+    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+    /* Enable HSE */
+    RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CR & RCC_CR_HSERDY;
+        StartUpCounter++;
+    }
+    while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    /*delay more than 2ms*/
+    while(nTime--)
+    {
+        i = 1500;
+        while(i--);
+    }
+
+    if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+    i = 10000; while(i--);
+    if (HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACR |= FLASH_ACR_PRFTBE;
+        /* Flash 0 wait state ,bit0~2*/
+        FLASH->ACR &= ~0x07;
+        FLASH->ACR |= 0x03;
+        /* HCLK = SYSCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+        /* PCLK2 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+        /* PCLK1 = HCLK */
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+        /*  PLL configuration:  = (HSE ) * (11+1) = 96 MHz */
+        RCC->CFGR &= (uint32_t)0xFFFCFFFF;
+        RCC->CR &= (uint32_t)0x000FFFFF;
+
+        RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
+        RCC->CR |= 0x2C000000;//pll = 12/1
+        //RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+        //RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CR |= RCC_CR_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CR & RCC_CR_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+        RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+        /* Wait till PLL is used as system clock source */
+        while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+          configuration. User can add here some code to deal with this error */
+    }
+}
+
+
+
+#elif defined SYSCLK_HSI_48MHz
+void SetSysClockTo48_HSI()
+{
+    unsigned char temp = 0;
+
+    RCC->CR |= RCC_CR_HSION;
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
+
+    RCC->CFGR &= ~RCC_CFGR_PLLSRC;	 //PLLSRC ON
+
+    RCC->CR &= ~(RCC_CR_PLLON);		//清PLL//	RCC->CR &=~(7<<20);		//清PLL
+
+    RCC->CR &= ~(0x1f << 26);
+    RCC->CR |= (4 - 1) << 26; //设置PLL值 2~16
+
+    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;	 //FLASH 2个延时周期
+
+    RCC->CR |= RCC_CR_PLLON; //PLLON
+    while(!(RCC->CR & RCC_CR_PLLRDY)); //等待PLL锁定
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_PLL; //PLL作为系统时钟
+    while(temp != 0x02)   //等待PLL作为系统时钟设置成功
+    {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+#elif defined SYSCLK_HSI_72MHz
+void SetSysClockTo72_HSI()
+{
+    unsigned char temp = 0;
+    RCC->CR |= RCC_CR_HSION;
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
+
+    RCC->CFGR &= ~RCC_CFGR_PLLSRC;	 //PLLSRC ON
+
+    RCC->CR &= ~(RCC_CR_PLLON);		//清PLL//	RCC->CR &=~(7<<20);		//清PLL
+
+    RCC->CR &= ~(0x1f << 26);
+    RCC->CR |= (6 - 1) << 26; //设置PLL值 2~16
+
+    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_PRFTBE;	 //FLASH 2个延时周期
+
+    RCC->CR |= RCC_CR_PLLON; //PLLON
+    while(!(RCC->CR & RCC_CR_PLLRDY)); //等待PLL锁定
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_PLL; //PLL作为系统时钟
+    while(temp != 0x02)   //等待PLL作为系统时钟设置成功
+    {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+#elif defined SYSCLK_HSI_96MHz
+void SetSysClockTo96_HSI()
+{
+    unsigned char temp = 0;
+    RCC->CR |= RCC_CR_HSION;
+    while(!(RCC->CR & RCC_CR_HSIRDY));
+    RCC->CFGR = RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
+
+    RCC->CFGR &= ~RCC_CFGR_PLLSRC;	 //PLLSRC ON
+
+    RCC->CR &= ~(RCC_CR_PLLON);		//清PLL//	RCC->CR &=~(7<<20);		//清PLL
+
+    RCC->CR &= ~(0x1f << 26);
+    RCC->CR |= (8 - 1) << 26; //设置PLL值 2~16
+
+    FLASH->ACR = FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0 | FLASH_ACR_PRFTBE;	 //FLASH 2个延时周期
+
+    RCC->CR |= RCC_CR_PLLON; //PLLON
+    while(!(RCC->CR & RCC_CR_PLLRDY)); //等待PLL锁定
+    RCC->CFGR &= ~RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_PLL; //PLL作为系统时钟
+    while(temp != 0x02)   //等待PLL作为系统时钟设置成功
+    {
+        temp = RCC->CFGR >> 2;
+        temp &= 0x03;
+    }
+}
+#endif
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+
+/**
+* @}
+*/
+/*-------------------------(C) COPYRIGHT 2019 MindMotion ----------------------*/

bsp/mm32f103x/Libraries/SConscript

@@ -0,0 +1,16 @@
+from building import *
+import rtconfig
+cwd     = GetCurrentDir()
+src	= ['MM32F103/Source/system_MM32F103.c']
+CPPPATH = [cwd + '/CMSIS/KEIL_CORE', cwd + '/MM32F103/Include',  cwd + '/MM32F103/Source', cwd + '/MM32F103/HAL_lib/inc']
+
+src += Glob('MM32F103/HAL_lib/src/*.c')
+CPPDEFINES = ['USE_STDPERIPH_DRIVER']
+
+if rtconfig.CROSS_TOOL == 'keil':
+    src += ['MM32F103/Source/KEIL_StartAsm/startup_MM32F103.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += ['MM32F103/Source/IAR_StartAsm/startup_MM32F103.s']
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/mm32f103x/README.md

@@ -0,0 +1,112 @@
+# MM32F103xx 芯片BSP 说明
+
+标签： MM32、Cortex-M3、MM32F103、国产MCU
+
+---
+
+## 1. 简介
+
+本文档使用 MM32 MiniBoard 开发板提供BSP(板级支持包) 支持。通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+MM32 MiniBoard 是为了用户快速上手、了解学习MM32系列MCU的一块入门级开发板，可满足基础测试及高端开发需求。
+
+开发板外观如下图所示：
+
+MM32 MiniBoard
+
+![MM32 MiniBoard Rev.D2](figures/MM32%20MiniBoard%20Rev.D2_1.jpg)
+
+MM32 MiniBoard 开发板板载资源如下：
+
+- MCU：MM32F103RB  ARM 32-bit Cortex-M3，主频 96MHz，128KB FLASH ，20KB SRAM
+- 常用外设
+  - LED：4个4色LED，可用于测试GPIO功能
+  - 按键：1个复位按键、 1个WakeUp按键、两个普通按键
+  - SPI Flash W25P80，容量8M bit，速度50MHz
+  - I2C接口EEPROM芯片，AT24C02，容量256字节
+  - 1个旋转式电位计（变阻器），用于ADC测试
+  - 能耗测试开关：待机模式和运行模式
+- 常用接口：Micro-USB接口，RS-232接口，UART接口
+- 调试接口：SWD，支持J-Link、U-LINK2、MM32-LINK调试器
+
+更多信息可以访问：[灵动微电子官方网站][https://www.mindmotion.com.cn]
+
+### 1.2  MCU 简介
+
+MM32F103RB 是上海灵动微电子股份有限公司的一款面向电机驱动、工业应用、消费电子、白色家电等领域的低功耗芯片。包括如下硬件特性：
+
+| 硬件 | 描述 |
+| -- | -- |
+|芯片型号| MM32F103RB |
+|CPU| ARM Cortex-M3 |
+|主频| 96MHz |
+|片内SRAM| 20KB |
+|片内Flash|  128KB |
+
+## 2. 编译说明
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 Jlink 仿真器下载程序，在通过 Jlink 连接开发板到 PC 的基础上，点击下载按钮即可下载程序到开发板
+
+推荐熟悉 RT_Thread 的用户使用[env工具](https://www.rt-thread.org/page/download.html)，可以在console下进入到 `bsp/mm32f103` 目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中 rtthread.bin 可以烧写到设备中运行。
+
+## 3. 烧写及执行
+
+### 3.1 硬件连接
+
+使用MM32-LINK或Jlink等调试工具连接开发板到PC，通过调试调试工具供电或使用Micro-USB供电。若使用Jlink等调试工具，还需要将UART1_TX(PA9)、UART1_RX(PA10)、GND接到串口工具上。
+
+使用MM32-LINK连接开发板如下图所示：
+
+MM32-LINK+MiniBoard
+
+![MM32-LINK+MiniBoard Rev.D2](figures/MM32%20MiniBoard%20Rev.D2_2.jpg)
+
+*你也可以使用 J-Link 或者 DAP-Link 实现下载调试。
+
+### 3.2 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会看到板子上的1个LED闪烁。串口打印RT-Thread的启动logo信息：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Dec 11 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh />
+```
+
+## 4. 驱动支持情况及计划
+
+| 驱动       | 支持情况 | 备注                         |
+| ---------- | :------: | :--------------------------: |
+| UART       | 支持     | UART1/2                   |
+| GPIO       | 支持     | / |
+
+## 5. 联系人信息
+
+维护人：
+
+-[StackRyan](https://github.com/StackRyan) email: yuanjyjyj@outlook.com
+
+## 6. 参考
+
+- [MM32F103xx 系列数据手册](https://www.mindmotion.com.cn/userfiles/images/MM32F103XiLieWenDang/DS_MM32F103xx_n_V1.09_SC.pdf)
+
+- [MM32F103xx 系列用户手册](https://www.mindmotion.com.cn/userfiles/images/MM32F103XiLieWenDang/UM_MM32F103xx_n_V1.69_SC.pdf)
+
+- [MiniBoardStartKit资料包](https://www.mindmotion.com.cn/download.aspx?cid=2545)
+
+- [keil pack安装包](https://www.mindmotion.com.cn/download.aspx?cid=2546)
+
+- [MM32 支持工具包](https://www.mindmotion.com.cn/download.aspx?cid=2547)
+

bsp/mm32f103x/SConscript

@@ -0,0 +1,11 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+objs = []
+list = os.listdir(cwd)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+Return('objs')

bsp/mm32f103x/SConstruct

@@ -0,0 +1,40 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mm32f103x/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd, str(Dir('#'))]
+src	= Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mm32f103x/drivers/Kconfig

@@ -0,0 +1,23 @@
+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        menu "GPIO Drivers"
+            config BSP_USING_GPIO
+                bool "Enable GPIO"
+                select RT_USING_PIN
+                default n
+        endmenu 
+        menu "UART Drivers"
+            config BSP_USING_UART1
+                bool "Enable UART1 PA9/10(T/R)"
+                select RT_USING_SERIAL
+                default n
+        
+            config BSP_USING_UART2
+                bool "Enable UART2 PA2/3(T/R)"
+                select RT_USING_SERIAL
+                default y
+        endmenu 
+    endmenu
+        
+endmenu

bsp/mm32f103x/drivers/SConscript

@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+board.c
+""")
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2'):
+    src += ['drv_uart.c']
+
+# add gpio driver code
+if  GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mm32f103x/drivers/board.c

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2017-2019, MindMotion AE Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-04     stackRyan    first version
+ */
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+#include <drv_uart.h>
+extern uint32_t SystemCoreClock;
+extern void SystemInit(void);
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+static void bsp_clock_config(void)
+{
+    SystemInit();
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    SysTick->CTRL |= 0x00000004UL;
+}
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void rt_hw_board_init()
+{
+    bsp_clock_config();
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+    volatile uint16_t i=0;
+    rt_hw_uart_init();
+    i = UINT16_MAX;
+    while(i--);     //wait for a while after uart initiated.
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}

bsp/mm32f103x/drivers/board.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017-2019, MindMotion AE Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-13     henryhuang   first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+#include <rtthread.h>
+#include <hal_device.h>
+
+#define SRAM_SIZE 0x5000
+
+#define SRAM_END (SRAM_BASE + SRAM_SIZE)
+#ifdef __CC_ARM
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section = "HEAP"
+    #define HEAP_BEGIN (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN ((void *)&__bss_end)
+#endif
+#define HEAP_END SRAM_END
+#define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN)
+extern void rt_hw_board_init(void);
+#endif

bsp/mm32f103x/drivers/drv_gpio.c

@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-04     stackRyan    first version
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+#include <rthw.h>
+
+#define MM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index}
+#define MM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
+/* MM32 GPIO driver */
+struct pin_index
+{
+    int index;
+    uint32_t rcc;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+    uint8_t port_source;
+    uint8_t pin_source;
+};
+static const struct pin_index mm32_pin_map[] =
+{
+    MM32_PIN_DEFAULT,
+    MM32_PIN(1, APB2, A, 0),
+    MM32_PIN(2, APB2, A, 1),
+    MM32_PIN(3, APB2, A, 2),
+    MM32_PIN(4, APB2, A, 3),
+    MM32_PIN(5, APB2, A, 4),
+    MM32_PIN(6, APB2, A, 5),
+    MM32_PIN(7, APB2, A, 6),
+    MM32_PIN(8, APB2, A, 7),
+    MM32_PIN(9, APB2, A, 8),
+    MM32_PIN(10, APB2, A, 9),
+    MM32_PIN(11, APB2, A, 10),
+    MM32_PIN(12, APB2, A, 11),
+    MM32_PIN(13, APB2, A, 12),
+    MM32_PIN(14, APB2, A, 13),
+    MM32_PIN(15, APB2, A, 14),
+    MM32_PIN(16, APB2, A, 15),
+    MM32_PIN(17, APB2, B, 0),
+    MM32_PIN(18, APB2, B, 1),
+    MM32_PIN(19, APB2, B, 2),
+    MM32_PIN(20, APB2, B, 3),
+    MM32_PIN(21, APB2, B, 4),
+    MM32_PIN(22, APB2, B, 5),
+    MM32_PIN(23, APB2, B, 6),
+    MM32_PIN(24, APB2, B, 7),
+    MM32_PIN(25, APB2, B, 8),
+    MM32_PIN(26, APB2, B, 9),
+    MM32_PIN(27, APB2, B, 10),
+    MM32_PIN(28, APB2, B, 11),
+    MM32_PIN(29, APB2, B, 12),
+    MM32_PIN(30, APB2, B, 13),
+    MM32_PIN(31, APB2, B, 14),
+    MM32_PIN(32, APB2, B, 15),
+    MM32_PIN(33, APB2, C, 0),
+    MM32_PIN(34, APB2, C, 1),
+    MM32_PIN(35, APB2, C, 2),
+    MM32_PIN(36, APB2, C, 3),
+    MM32_PIN(37, APB2, C, 4),
+    MM32_PIN(38, APB2, C, 5),
+    MM32_PIN(39, APB2, C, 6),
+    MM32_PIN(40, APB2, C, 7),
+    MM32_PIN(41, APB2, C, 8),
+    MM32_PIN(42, APB2, C, 9),
+    MM32_PIN(43, APB2, C, 10),
+    MM32_PIN(44, APB2, C, 11),
+    MM32_PIN(45, APB2, C, 12),
+    MM32_PIN(46, APB2, C, 13),
+    MM32_PIN(47, APB2, C, 14),
+    MM32_PIN(48, APB2, C, 15),
+    MM32_PIN(49, APB2, D, 0),
+    MM32_PIN(50, APB2, D, 1),
+    MM32_PIN(51, APB2, D, 2),
+    MM32_PIN(52, APB2, D, 3),
+    MM32_PIN(53, APB2, D, 4),
+    MM32_PIN(54, APB2, D, 5),
+    MM32_PIN(55, APB2, D, 6),
+    MM32_PIN(56, APB2, D, 7),
+    MM32_PIN(57, APB2, D, 8),
+    MM32_PIN(58, APB2, D, 9),
+    MM32_PIN(59, APB2, D, 10),
+    MM32_PIN(60, APB2, D, 11),
+    MM32_PIN(61, APB2, D, 12),
+    MM32_PIN(62, APB2, D, 13),
+    MM32_PIN(63, APB2, D, 14),
+    MM32_PIN(64, APB2, D, 15),
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t            pinbit;
+    rt_uint32_t            irqbit;
+    enum IRQn              irqno;
+};
+const struct pin_irq_map mm32_pin_irq_map[] =
+{
+    {GPIO_Pin_0,  EXTI_Line0,  EXTI0_IRQn    },
+    {GPIO_Pin_1,  EXTI_Line1,  EXTI1_IRQn    },
+    {GPIO_Pin_2,  EXTI_Line2,  EXTI2_IRQn    },
+    {GPIO_Pin_3,  EXTI_Line3,  EXTI3_IRQn    },
+    {GPIO_Pin_4,  EXTI_Line4,  EXTI4_IRQn    },
+    {GPIO_Pin_5,  EXTI_Line5,  EXTI9_5_IRQn  },
+    {GPIO_Pin_6,  EXTI_Line6,  EXTI9_5_IRQn  },
+    {GPIO_Pin_7,  EXTI_Line7,  EXTI9_5_IRQn  },
+    {GPIO_Pin_8,  EXTI_Line8,  EXTI9_5_IRQn  },
+    {GPIO_Pin_9,  EXTI_Line9,  EXTI9_5_IRQn  },
+    {GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn},
+    {GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn},
+    {GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn},
+    {GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn},
+    {GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn},
+    {GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn},
+};
+struct rt_pin_irq_hdr mm32_pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(mm32_pin_map))
+    {
+        index = &mm32_pin_map[pin];
+        if (index->gpio == 0)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    if (value == PIN_LOW)
+    {
+        GPIO_ResetBits(index->gpio, index->pin);
+    }
+    else
+    {
+        GPIO_SetBits(index->gpio, index->pin);
+    }
+}
+
+int mm32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return PIN_LOW;
+    }
+    if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
+    {
+        value = PIN_LOW;
+    }
+    else
+    {
+        value = PIN_HIGH;
+    }
+    return value;
+}
+
+void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef  GPIO_InitStructure;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    /* GPIO Periph clock enable */
+    RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStructure.GPIO_Pin     = index->pin;
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_PP;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_Out_OD;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IN_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPU;
+    }
+    else
+    {
+        /* input setting:default. */
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPD;
+    }
+    GPIO_Init( index->gpio, &GPIO_InitStructure);
+}
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &mm32_pin_irq_map[mapindex];
+};
+rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                             rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return -RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
+    {
+        return -RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (mm32_pin_irq_hdr_tab[irqindex].pin == pin   &&
+            mm32_pin_irq_hdr_tab[irqindex].hdr == hdr   &&
+            mm32_pin_irq_hdr_tab[irqindex].mode == mode &&
+            mm32_pin_irq_hdr_tab[irqindex].args == args
+       )
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (mm32_pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return -RT_EBUSY;
+    }
+    mm32_pin_irq_hdr_tab[irqindex].pin = pin;
+    mm32_pin_irq_hdr_tab[irqindex].hdr = hdr;
+    mm32_pin_irq_hdr_tab[irqindex].mode = mode;
+    mm32_pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    mm32_pin_irq_hdr_tab[irqindex].pin = -1;
+    mm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    mm32_pin_irq_hdr_tab[irqindex].mode = 0;
+    mm32_pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                             rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    NVIC_InitTypeDef  NVIC_InitStructure;
+    EXTI_InitTypeDef EXTI_InitStructure;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return -RT_ENOSYS;
+    }
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(index->pin);
+        if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map))
+        {
+            return -RT_ENOSYS;
+        }
+        level = rt_hw_interrupt_disable();
+        if (mm32_pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return -RT_ENOSYS;
+        }
+        irqmap = &mm32_pin_irq_map[irqindex];
+        /* GPIO Periph clock enable */
+        RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStructure.GPIO_Pin     = index->pin;
+        GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_IPU;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(index->gpio, &GPIO_InitStructure);
+
+        NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno;
+        NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
+        NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
+        NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+        NVIC_Init(&NVIC_InitStructure);
+
+        GPIO_EXTILineConfig(index->port_source, index->pin_source);
+        EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
+        EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+        switch (mm32_pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+            break;
+        }
+        EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+        EXTI_Init(&EXTI_InitStructure);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return -RT_ENOSYS;
+        }
+        EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
+        EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+        EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+        EXTI_InitStructure.EXTI_LineCmd = DISABLE;
+        EXTI_Init(&EXTI_InitStructure);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _mm32_pin_ops =
+{
+    mm32_pin_mode,
+    mm32_pin_write,
+    mm32_pin_read,
+    mm32_pin_attach_irq,
+    mm32_pin_detach_irq,
+    mm32_pin_irq_enable,
+    RT_NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+
+    result = rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    EXTI_ClearITPendingBit(mm32_pin_irq_map[irqno].irqbit);
+    if (mm32_pin_irq_hdr_tab[irqno].hdr)
+    {
+        mm32_pin_irq_hdr_tab[irqno].hdr(mm32_pin_irq_hdr_tab[irqno].args);
+    }
+}
+void EXTI0_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    pin_irq_hdr(0);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    pin_irq_hdr(1);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    pin_irq_hdr(2);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    pin_irq_hdr(3);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    pin_irq_hdr(4);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI9_5_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (EXTI_GetITStatus(EXTI_Line5) != RESET)
+    {
+        pin_irq_hdr(5);
+    }
+    if (EXTI_GetITStatus(EXTI_Line6) != RESET)
+    {
+        pin_irq_hdr(6);
+    }
+    if (EXTI_GetITStatus(EXTI_Line7) != RESET)
+    {
+        pin_irq_hdr(7);
+    }
+    if (EXTI_GetITStatus(EXTI_Line8) != RESET)
+    {
+        pin_irq_hdr(8);
+    }
+    if (EXTI_GetITStatus(EXTI_Line9) != RESET)
+    {
+        pin_irq_hdr(9);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+void EXTI15_10_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (EXTI_GetITStatus(EXTI_Line10) != RESET)
+    {
+        pin_irq_hdr(10);
+    }
+    if (EXTI_GetITStatus(EXTI_Line11) != RESET)
+    {
+        pin_irq_hdr(11);
+    }
+    if (EXTI_GetITStatus(EXTI_Line12) != RESET)
+    {
+        pin_irq_hdr(12);
+    }
+    if (EXTI_GetITStatus(EXTI_Line13) != RESET)
+    {
+        pin_irq_hdr(13);
+    }
+    if (EXTI_GetITStatus(EXTI_Line14) != RESET)
+    {
+        pin_irq_hdr(14);
+    }
+    if (EXTI_GetITStatus(EXTI_Line15) != RESET)
+    {
+        pin_irq_hdr(15);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}

bsp/mm32f103x/drivers/drv_gpio.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-02     henryhuang   the first version
+ */
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/mm32f103x/drivers/drv_uart.c

@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-04     stackRyan    first version
+ */
+#include <HAL_device.h>
+#include <rtdevice.h>
+#include "drv_uart.h"
+
+/* UART1 */
+#define UART1_GPIO_TX           GPIO_Pin_9
+#define UART1_GPIO_TX_SOURCE    GPIO_PinSource9
+#define UART1_GPIO_RX           GPIO_Pin_10
+#define UART1_GPIO_RX_SOURCE    GPIO_PinSource10
+#define UART1_GPIO_AF           GPIO_AF_1
+#define UART1_GPIO              GPIOA
+
+/* UART2 */
+#define UART2_GPIO_TX           GPIO_Pin_2
+#define UART2_GPIO_TX_SOURCE    GPIO_PinSource2
+#define UART2_GPIO_RX           GPIO_Pin_3
+#define UART2_GPIO_RX_SOURCE    GPIO_PinSource3
+#define UART2_GPIO_AF           GPIO_AF_1
+#define UART2_GPIO              GPIOA
+
+/* uart driver */
+struct mm32_uart
+{
+    UART_TypeDef *uart;
+    IRQn_Type irq;
+};
+
+static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct mm32_uart *uart;
+    UART_InitTypeDef UART_InitStructure;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct mm32_uart *)serial->parent.user_data;
+    UART_InitStructure.UART_BaudRate = cfg->baud_rate;
+    if (cfg->data_bits == DATA_BITS_8)
+        UART_InitStructure.UART_WordLength = UART_WordLength_8b;
+    if (cfg->stop_bits == STOP_BITS_1)
+        UART_InitStructure.UART_StopBits = UART_StopBits_1;
+    else if (cfg->stop_bits == STOP_BITS_2)
+        UART_InitStructure.UART_StopBits = UART_StopBits_2;
+    UART_InitStructure.UART_Parity = UART_Parity_No;
+    UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
+    UART_InitStructure.UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
+    UART_Init(uart->uart, &UART_InitStructure);
+    /* Enable UART */
+    UART_Cmd(uart->uart, ENABLE);
+    return RT_EOK;
+}
+
+static rt_err_t mm32_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct mm32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        UART_ITConfig(uart->uart, UART_IT_RXIEN, DISABLE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        UART_ITConfig(uart->uart, UART_IT_RXIEN, ENABLE);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int mm32_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct mm32_uart *)serial->parent.user_data;
+    while ((uart->uart->CSR & UART_IT_TXIEN) == 0);
+    uart->uart->TDR = (c & (uint16_t)0x00FF);
+    return 1;
+}
+
+static int mm32_uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct mm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct mm32_uart *)serial->parent.user_data;
+    ch = -1;
+    if (uart->uart->CSR & UART_FLAG_RXAVL)
+    {
+        ch = uart->uart->RDR & 0xff;
+    }
+    return ch;
+}
+
+static const struct rt_uart_ops mm32_uart_ops =
+{
+    mm32_uart_configure,
+    mm32_uart_control,
+    mm32_uart_putc,
+    mm32_uart_getc,
+};
+
+#if defined(BSP_USING_UART1)
+/* UART1 device driver structure */
+static struct mm32_uart uart1;
+struct rt_serial_device serial1;
+void UART1_IRQHandler(void)
+{
+    struct mm32_uart *uart;
+    uart = &uart1;
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET)
+    {
+        UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN);
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET)
+    {
+        /* clear interrupt */
+        UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+/* UART2 device driver structure */
+static struct mm32_uart uart2;
+struct rt_serial_device serial2;
+void UART2_IRQHandler(void)
+{
+    struct mm32_uart *uart;
+    uart = &uart2;
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (UART_GetITStatus(uart->uart, UART_IT_RXIEN) != RESET)
+    {
+        UART_ClearITPendingBit(uart->uart, UART_IT_RXIEN);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+    }
+    if (UART_GetITStatus(uart->uart, UART_IT_TXIEN) != RESET)
+    {
+        /* clear interrupt */
+        UART_ClearITPendingBit(uart->uart, UART_IT_TXIEN);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART1
+static void UART1PINconfigStepA(void)
+{
+    /* Enable UART clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_UART1 | RCC_APB2Periph_GPIOA, ENABLE);
+}
+
+static void UART1PINconfigStepB(void)
+{
+
+    GPIO_InitTypeDef GPIO_InitStructure;
+    /* Configure USART Rx/tx PIN */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+}
+#endif
+
+#ifdef BSP_USING_UART2
+static void UART2PINconfigStepA(void)
+{
+    /* Enable UART clock */
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+}
+
+static void UART2PINconfigStepB(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+    /* Configure USART Rx/tx PIN */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+}
+#endif
+
+int rt_hw_uart_init(void)
+{
+    struct mm32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#ifdef BSP_USING_UART1
+    UART1PINconfigStepA();
+    uart = &uart1;
+    uart->uart = UART1;
+    uart->irq = UART1_IRQn;
+    config.baud_rate = BAUD_RATE_115200;
+    serial1.ops    = &mm32_uart_ops;
+    serial1.config = config;
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    UART1PINconfigStepB();
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+    UART2PINconfigStepA();
+    uart = &uart2;
+    uart->uart = UART2;
+    uart->irq = UART2_IRQn;
+    config.baud_rate = BAUD_RATE_115200;
+    serial2.ops    = &mm32_uart_ops;
+    serial2.config = config;
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    UART2PINconfigStepB();
+#endif /* BSP_USING_UART2 */
+    return 0;
+}
+//INIT_BOARD_EXPORT(rt_hw_uart_init);
+//attention: uart init hardware problems occure on mm32f103
+//recommand manually initialize uart in rt_hw_board_init()
+//see in rt_hw_board_init() learn more on rt_hw_uart_init() detials.

bsp/mm32f103x/drivers/drv_uart.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2017-2019, MindMotion AE Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-13     henryhuang   first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/mm32f103x/drivers/linker_scripts/link.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_IROM_end__   = 0x0001FFFF;
+define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_IRAM_end__   = 0x20004FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__     = 0x0800;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__       = 0x0800;
+/**** End of ICF editor section. ###ICF###*/
+define memory mem with size = 4G;
+define region IROM_region   =   mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__];
+define region IRAM_region   =   mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with alignment = 8, size = __ICFEDIT_size_heap__       { };
+
+do not initialize  { section .noinit };
+initialize by copy { readwrite };
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+  // Required in a multi-threaded application
+  initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in IROM_region  { readonly };
+place in IRAM_region  { readwrite, block CSTACK, block PROC_STACK, block HEAP };

bsp/mm32f103x/drivers/linker_scripts/link.lds

@@ -0,0 +1,137 @@
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x08000000, LENGTH = 128k /* 128KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH =  20k /* 8K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/mm32f103x/drivers/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00005000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/mm32f103x/project.ewd

@@ -0,0 +1,2966 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rt-thread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\MindMotion\MM32F103xB.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.20.1.14181</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>JLINK_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>8.40.1.21529</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$\config\flashloader\MindMotion\FlashMM32F10xxB.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>9</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>7</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state>72</state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>6</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>8.20.1.14181</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>ARMSIM_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>6</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>

bsp/mm32f103x/project.ewp

@@ -0,0 +1,2334 @@
+<project>
+  <fileVersion>3</fileVersion>
+  <configuration>
+    <name>rt-thread</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>build\iar\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>build\iar\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>build\iar\List</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter, without multibyte support.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>6.30.6.53380</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>8.40.1.21529</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MM32F103xB	MindMotion MM32F103xB</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>27</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CoreVariant</name>
+          <version>27</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GFPUDeviceSlave</name>
+          <state>MM32F103xB	MindMotion MM32F103xB</state>
+        </option>
+        <option>
+          <name>FPU2</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NrRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NEON</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave2</name>
+          <version>27</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGCMSISPackSelectDevice</name>
+        </option>
+        <option>
+          <name>OgLibHeap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGLibAdditionalLocale</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGPrintfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfVariant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGScanfMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenLocaleTags</name>
+          <state />
+        </option>
+        <option>
+          <name>GenLocaleDisplayOnly</name>
+          <state />
+        </option>
+        <option>
+          <name>DSPExtension</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TrustZone</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>TrustZoneModes</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>35</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          <state />
+          <state>__RTTHREAD__</state>
+          <state>USE_STDPERIPH_DRIVER</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state />
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state />
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
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+          <name>IlinkAdditionalLibs</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state />
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state />
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>1</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogCallGraph</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile_AltDefault</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkEncInput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkEncOutputBom</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkHeapSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLocaleSelect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkTrustzoneImportLibraryOut</name>
+          <state>###Unitialized###</state>
+        </option>
+        <option>
+          <name>OILinkExtraOption</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment2</name>
+          <state />
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign2</name>
+          <state />
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state />
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data />
+    </settings>
+  </configuration>
+  <group>
+    <name>Applications</name>
+    <file>
+      <name>$PROJ_DIR$\applications\main.c</name>
+    </file>
+  </group>
+  <group>
+    <name>CPU</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\backtrace.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\showmem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\common\div0.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c</name>
+    </file>
+  </group>
+  <group>
+    <name>DeviceDrivers</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\misc\pin.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\serial\serial.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\dataqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\waitqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\workqueue.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\pipe.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\drivers\src\completion.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Drivers</name>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\drv_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\drivers\board.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Finsh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\msh.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\memheap.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\timer.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\components.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\thread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\object.c</name>
+    </file>
+  </group>
+  <group>
+    <name>libc</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\libc\compilers\common\time.c</name>
+    </file>
+  </group>
+  <group>
+    <name>Libraries</name>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\Source\system_MM32F103.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_flash.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_spi.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_wwdg.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\Source\IAR_StartAsm\startup_MM32F103.s</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_gpio.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_adc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_tim.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_exti.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rcc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_rtc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_pwr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_misc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_iwdg.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_bkp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_can.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_dma.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_uart.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_i2c.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Libraries\MM32F103\HAL_lib\src\HAL_crc.c</name>
+    </file>
+  </group>
+  <group>
+    <name>utestcases</name>
+  </group>
+</project>

bsp/mm32f103x/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/mm32f103x/rtconfig.h

@@ -0,0 +1,186 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 1024
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 1024
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_LIBC_USING_TIME
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+
+/* Hardware Drivers Config */
+
+/* On-chip Peripheral Drivers */
+
+/* GPIO Drivers */
+
+#define BSP_USING_GPIO
+
+/* UART Drivers */
+
+#define BSP_USING_UART1
+#define SOC_MM32L373
+
+#endif

bsp/mm32f103x/rtconfig.py

@@ -0,0 +1,135 @@
+# BSP Note: For TI EK-TM4C1294XL Tiva C Series Connected LancuhPad	(REV D)
+
+import os
+import sys
+# toolchains options
+CROSS_TOOL = 'gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+# device options
+ARCH = 'arm'
+CPU = 'cortex-m3'
+
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if CROSS_TOOL == 'gcc':
+    PLATFORM = 'gcc'
+    EXEC_PATH = '/Users/zhangyihong/.env/gcc-arm-none-eabi-5_4-2016q3/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM = 'armcc'
+    EXEC_PATH = 'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM = 'iar'
+    EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections -Wall'
+    CFLAGS = DEVICE + ' -std=c99'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu ' + CPU 
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "drivers/linker_scripts/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/ARMCC/LIB'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/arm/armcc/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm' # + ' -D' + PART_TYPE
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+
+    CFLAGS += ' --endian=little' 
+    CFLAGS += ' --cpu=Cortex-M3' 
+    CFLAGS += ' -e' 
+
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' --silent'
+        
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu ' + CPU
+
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'    
+    #LFLAGS += ' --silent'
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = ''

bsp/mm32f103x/template.ewp

@@ -0,0 +1,2106 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>rt-thread</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>build\iar\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>build\iar\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>build\iar\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Automatic choice of formatter, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>6.30.6.53380</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.40.1.21529</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>MM32F103xB	MindMotion MM32F103xB</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>27</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>27</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>MM32F103xB	MindMotion MM32F103xB</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>27</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>35</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state>Pa050</state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>../../../rtthread.bin</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>23</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>rtthread.out</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>$PROJ_DIR$\drivers\linker_scripts\link.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state>__iar_program_start</state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>31</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>ExePath</name>
+                    <state>Release\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Release\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Release\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>6.30.6.53380</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>8.11.3.13977</state>
+                </option>
+                <option>
+                    <name>GeneralEnableMisra</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVerbose</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>Default	None</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>GeneralMisraVer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GeneralMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>27</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>27</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>Default	None</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>27</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>35</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>11111110</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CompilerMisraOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules98</name>
+                    <version>0</version>
+                    <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+                </option>
+                <option>
+                    <name>CompilerMisraRules04</name>
+                    <version>0</version>
+                    <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>10</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+            </data>
+        </settings>
+        <settings>
+            <name>BICOMP</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>23</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>XLinkMisraHandler</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogModule</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogSection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogVeneer</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state>lnk0t.icf</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsWarn</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoFill</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>FillerByte</name>
+                    <state>0xFF</state>
+                </option>
+                <option>
+                    <name>FillerStart</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>FillerEnd</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>CrcSize</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcAlign</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcPoly</name>
+                    <state>0x11021</state>
+                </option>
+                <option>
+                    <name>CrcCompl</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcBitOrder</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
+                    <state>0x0</state>
+                </option>
+                <option>
+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackControlFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>BILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data />
+        </settings>
+    </configuration>
+</project>

bsp/mm32f103x/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/mm32f103x/template.uvopt

@@ -0,0 +1,184 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>25000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <Books>
+        <Book>
+          <Number>0</Number>
+          <Title>Datasheet</Title>
+          <Path>DATASHTS\ST\STM32F4xx\DM00053488.pdf</Path>
+        </Book>
+        <Book>
+          <Number>1</Number>
+          <Title>Reference Manual</Title>
+          <Path>DATASHTS\ST\STM32F4xx\DM00031020.pdf</Path>
+        </Book>
+        <Book>
+          <Number>2</Number>
+          <Title>Technical Reference Manual</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF</Path>
+        </Book>
+        <Book>
+          <Number>3</Number>
+          <Title>Generic User Guide</Title>
+          <Path>datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF</Path>
+        </Book>
+      </Books>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <tPdscDbg>0</tPdscDbg>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>6</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U20090928 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-O207 -S0 -C0 -FO7  -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/mm32f103x/template.uvoptx

@@ -0,0 +1,182 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>4</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>Segger\JL2CM3.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U69614099 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128.FLM -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128 -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>MM32LINKCM3</Key>
+          <Name>-U6175B4CC7 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0MM32L3xx_128.FLM -FS08000000 -FL020000 -FP0($$Device:MM32L373PF$Flash\MM32L3xx_128.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/mm32f103x/template.uvprojx

@@ -0,0 +1,406 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MM32F103RBT</Device>
+          <Vendor>MindMotion</Vendor>
+          <PackID>MindMotion.MM32F103x8xB_DFP.1.4.7</PackID>
+          <PackURL>http://www.mindmotion.com.cn/Download/MDK_KEIL/</PackURL>
+          <Cpu>IRAM(0x20000000,0x5000) IROM(0x08000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MM32F103_128 -FS08000000 -FL020000 -FP0($$Device:MM32F103RBT$Flash\MM32F103_128.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:MM32F103RBT$Device\MM32F103\Include\HAL_device.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:MM32F103RBT$SVD\MM32F103.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x5000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>USE_STDPERIPH_DRIVER</Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\drivers\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayDesc></LayDesc>
+        <LayUrl></LayUrl>
+        <LayKeys></LayKeys>
+        <LayCat></LayCat>
+        <LayLic></LayLic>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>