[bsp][stm32][f796-disco]Add stm32f769-st-disco bsp

Signed-off-by: Willian Chan <chentingwei@rt-thread.com>

bsp/stm32/README.md

@@ -31,6 +31,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f767-atk-apollo](stm32f767-atk-apollo) | 正点原子 F767 阿波罗开发板 |
 | [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 |
 | [stm32f767-st-nucleo](stm32f767-st-nucleo) | ST 官方 STM32F767-nucleo 开发板 |
+| [stm32f769-st-disco](stm32f769-st-disco) | ST 官方 STM32f769-discovery 开发板 |
 | **G0 系列** |  |
 | [stm32g071-st-nucleo](stm32g071-st-nucleo) | ST 官方 STM32G071-nucleo 开发板 |
 | **H7 系列** |  |

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/.config

@@ -0,0 +1,408 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40002
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_LIBC_USING_TIME=y
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+CONFIG_PKG_USING_NRF24L01=y
+CONFIG_PKG_NRF24L01_PATH="/packages/peripherals/nrf24l01"
+# CONFIG_PKG_USING_NRF24L01_V100 is not set
+CONFIG_PKG_USING_NRF24L01_LATEST_VERSION=y
+CONFIG_PKG_NRF24L01_VER="latest"
+# CONFIG_PKG_USING_NRF24L01_SAMPLE is not set
+# CONFIG_NRF24_USING_INFO_REPORT is not set
+# CONFIG_NRF24_USING_SHELL_CMD is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_LCD_DRIVERS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32F1=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32F103ZE=y
+
+#
+# Onboard Peripheral Drivers
+#
+# CONFIG_BSP_USING_SDIO_SDCARD is not set
+# CONFIG_BSP_USING_SPI_SDCARD is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_EEPROM is not set
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+CONFIG_BSP_USING_SPI=y
+# CONFIG_BSP_USING_SPI1 is not set
+CONFIG_BSP_USING_SPI2=y
+# CONFIG_BSP_SPI2_TX_USING_DMA is not set
+# CONFIG_BSP_SPI2_RX_USING_DMA is not set
+# CONFIG_BSP_USING_SPI3 is not set
+# CONFIG_BSP_USING_I2C2 is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_UDID is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_NRF24L01=y

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/.project

@@ -0,0 +1,69 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>stm32f103-dofly-M3S</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.rt-thread.studio.rttnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>rt-thread</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/bsp</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/components</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/include</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/libcpu</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/src</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/bsp/stm32</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>rt-thread/bsp/stm32/libraries</name>
+			<type>2</type>
+			<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-631187056492398907" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/Kconfig

@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "board/Kconfig"
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/README.md

@@ -0,0 +1,117 @@
+# STM32F103 德飞莱-尼莫 M3S 开发板 BSP 说明
+
+## 简介
+
+本文档是石河子大学陈庭伟同学为 STM32F103 德飞莱-尼莫 M3S 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+STM32F103 德飞莱-尼莫 M3S 是徳飞莱推出的一款基于 ARM Cortex-M3 内核的开发板，最高主频为 72Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F103 的芯片性能。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32F103ZET6，主频 72MHz，512KB FLASH ，64KB RAM
+- 外部 RAM：型号24C02，2KB
+- 外部 FLASH：型号W25Q64，8MB
+- 常用外设
+  - LED：2个，LED2（红色，PE5），LED3（红色，PB5）
+  - 按键：4个，S1（PE4），S2（PE3），S3（PE2），S4（兼具唤醒功能，PA0）
+- 常用接口：USB 转串口、SD 卡接口、RS232 接口、LCD 接口、NRF24L01接口等
+- 调试接口，标准 JTAG/SWD
+
+开发板更多详细信息请参考徳飞莱的 [STM32F103-尼莫M3S 开发板介绍](https://item.taobao.com/item.htm?spm=a1z10.1-c.w4004-1022655459.10.44ae4d22Wa8UIo&id=44835368405)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注** |
+| :-----: | :-----: | :-----: |
+| SDCARD | 支持 |  |
+| SPI FLASH | 支持 | W25Q64，8MB |
+| EEPRAM | 支持 | 24c02，2KB |
+| **片上外设** | **支持情况** | **备注** |
+| GPIO  | 支持 |  |
+| USART | 支持 | USART1 |
+| SDIO | 支持 |  |
+| SPI | 支持 | SPI1/2/3 |
+| I2C | 支持 | 软件I2C |
+| FLASH | 支持 | 已适配 [FAL](https://github.com/RT-Thread-packages/fal) |
+| **扩展模块** | **支持情况** | **备注** |
+| NRF24L01 | 支持 | 根据实际板子接线情况修改 NRF24L01 软件包中的 `NRF24L01_CE_PIN` 和 `NRF24_IRQ_PIN` 的宏定义，以及 SPI 设备名 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 st-link 仿真器下载程序，在通过 st-link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.1 build Apr  9 2019
+ 2006 - 2019 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+- 这款开发板使用终端工具 SecureCRT 来打开串口会出现系统不能启动的问题，推荐使用 XCOM V2.0。
+
+## 联系人信息
+
+维护人:
+
+-  [WillianChan](https://github.com/willianchanlovegithub)

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/SConstruct

@@ -0,0 +1,63 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+# set RTT_ROOT
+if not os.getenv("RTT_ROOT"): 
+    RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32F1xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/applications/SConscript

@@ -0,0 +1,18 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Split('''
+main.c
+''')
+
+if GetDepend(['BSP_USING_NRF24L01']):
+    src += Glob('ports/nrf24l01_init.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/applications/main.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-04-09     WillianChan  add stm32f103-dofly-M3S BSP
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED0 pin: PE5 */
+#define LED0_PIN    GET_PIN(E, 5)
+
+int main(void)
+{
+    int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/applications/nrf24l01_init.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-06-29     WillianChan   first version
+ */
+
+#include <rtthread.h>
+
+#ifdef PKG_USING_NRF24L01
+
+#include "drv_spi.h"
+static int rt_hw_nrf24l01_init(void)
+{
+    rt_hw_spi_device_attach("spi2", "spi20", GPIOG, GPIO_PIN_7);
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_nrf24l01_init);
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,184 @@
+#MicroXplorer Configuration settings - do not modify
+File.Version=6
+KeepUserPlacement=false
+Mcu.Family=STM32F1
+Mcu.IP0=NVIC
+Mcu.IP1=RCC
+Mcu.IP2=SDIO
+Mcu.IP3=SPI1
+Mcu.IP4=SPI2
+Mcu.IP5=SPI3
+Mcu.IP6=SYS
+Mcu.IP7=USART1
+Mcu.IPNb=8
+Mcu.Name=STM32F103Z(C-D-E)Tx
+Mcu.Package=LQFP144
+Mcu.Pin0=PC14-OSC32_IN
+Mcu.Pin1=PC15-OSC32_OUT
+Mcu.Pin10=PC8
+Mcu.Pin11=PC9
+Mcu.Pin12=PA9
+Mcu.Pin13=PA10
+Mcu.Pin14=PA13
+Mcu.Pin15=PA14
+Mcu.Pin16=PC10
+Mcu.Pin17=PC11
+Mcu.Pin18=PC12
+Mcu.Pin19=PD2
+Mcu.Pin2=OSC_IN
+Mcu.Pin20=PB3
+Mcu.Pin21=PB4
+Mcu.Pin22=PB5
+Mcu.Pin23=VP_SYS_VS_Systick
+Mcu.Pin3=OSC_OUT
+Mcu.Pin4=PA5
+Mcu.Pin5=PA6
+Mcu.Pin6=PA7
+Mcu.Pin7=PB13
+Mcu.Pin8=PB14
+Mcu.Pin9=PB15
+Mcu.PinsNb=24
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F103ZETx
+MxCube.Version=5.1.0
+MxDb.Version=DB.5.0.10
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+OSC_IN.Mode=HSE-External-Oscillator
+OSC_IN.Signal=RCC_OSC_IN
+OSC_OUT.Mode=HSE-External-Oscillator
+OSC_OUT.Signal=RCC_OSC_OUT
+PA10.Mode=Asynchronous
+PA10.Signal=USART1_RX
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA6.Mode=Full_Duplex_Master
+PA6.Signal=SPI1_MISO
+PA7.Mode=Full_Duplex_Master
+PA7.Signal=SPI1_MOSI
+PA9.Mode=Asynchronous
+PA9.Signal=USART1_TX
+PB13.Mode=Full_Duplex_Master
+PB13.Signal=SPI2_SCK
+PB14.Mode=Full_Duplex_Master
+PB14.Signal=SPI2_MISO
+PB15.Mode=Full_Duplex_Master
+PB15.Signal=SPI2_MOSI
+PB3.Mode=Full_Duplex_Master
+PB3.Signal=SPI3_SCK
+PB4.Mode=Full_Duplex_Master
+PB4.Signal=SPI3_MISO
+PB5.Mode=Full_Duplex_Master
+PB5.Signal=SPI3_MOSI
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDIO_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDIO_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDIO_CK
+PC14-OSC32_IN.Mode=LSE-External-Oscillator
+PC14-OSC32_IN.Signal=RCC_OSC32_IN
+PC15-OSC32_OUT.Mode=LSE-External-Oscillator
+PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDIO_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDIO_D1
+PCC.Checker=false
+PCC.Line=STM32F103
+PCC.MCU=STM32F103Z(C-D-E)Tx
+PCC.PartNumber=STM32F103ZETx
+PCC.Seq0=0
+PCC.Series=STM32F1
+PCC.Temperature=25
+PCC.Vdd=3.3
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDIO_CMD
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F103ZETx
+ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SDIO_SD_Init-SDIO-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_SPI3_Init-SPI3-false-HAL-true
+RCC.ADCFreqValue=36000000
+RCC.AHBFreq_Value=72000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV2
+RCC.APB1Freq_Value=36000000
+RCC.APB1TimFreq_Value=72000000
+RCC.APB2Freq_Value=72000000
+RCC.APB2TimFreq_Value=72000000
+RCC.FCLKCortexFreq_Value=72000000
+RCC.FSMCFreq_Value=72000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=72000000
+RCC.I2S2Freq_Value=72000000
+RCC.I2S3Freq_Value=72000000
+RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FSMCFreq_Value,FamilyName,HCLKFreq_Value,I2S2Freq_Value,I2S3Freq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,SDIOFreq_Value,SDIOHCLKDiv2FreqValue,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.MCOFreq_Value=72000000
+RCC.PLLCLKFreq_Value=72000000
+RCC.PLLMCOFreq_Value=36000000
+RCC.PLLMUL=RCC_PLL_MUL9
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.SDIOFreq_Value=72000000
+RCC.SDIOHCLKDiv2FreqValue=36000000
+RCC.SYSCLKFreq_VALUE=72000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TimSysFreq_Value=72000000
+RCC.USBFreq_Value=72000000
+RCC.VCOOutput2Freq_Value=8000000
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
+SPI1.CalculateBaudRate=18.0 MBits/s
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualType=VM_MASTER
+SPI2.CalculateBaudRate=18.0 MBits/s
+SPI2.Direction=SPI_DIRECTION_2LINES
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
+SPI2.Mode=SPI_MODE_MASTER
+SPI2.VirtualType=VM_MASTER
+SPI3.CalculateBaudRate=18.0 MBits/s
+SPI3.Direction=SPI_DIRECTION_2LINES
+SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
+SPI3.Mode=SPI_MODE_MASTER
+SPI3.VirtualType=VM_MASTER
+USART1.IPParameters=VirtualMode
+USART1.VirtualMode=VM_ASYNC
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/main.h

@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h

@@ -0,0 +1,370 @@
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_hal_conf.h
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_CONF_H
+#define __STM32F1xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+  
+#define HAL_MODULE_ENABLED  
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_CAN_MODULE_ENABLED   */
+/*#define HAL_CEC_MODULE_ENABLED   */
+/*#define HAL_CORTEX_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_DMA_MODULE_ENABLED   */
+/*#define HAL_ETH_MODULE_ENABLED   */
+/*#define HAL_FLASH_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_PCCARD_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_HCD_MODULE_ENABLED   */
+/*#define HAL_PWR_MODULE_ENABLED   */
+/*#define HAL_RCC_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
+/*#define HAL_MMC_MODULE_ENABLED   */
+/*#define HAL_SDRAM_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+/*#define HAL_EXTI_MODULE_ENABLED   */
+
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz
+                                                The real value may vary depending on the variations
+                                                in voltage and temperature. */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)0)    /*!< tick interrupt priority (lowest by default)  */            
+#define  USE_RTOS                     0
+#define  PREFETCH_ENABLE              1
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2
+#define MAC_ADDR1   0
+#define MAC_ADDR2   0
+#define MAC_ADDR3   0
+#define MAC_ADDR4   0
+#define MAC_ADDR5   0
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)8)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/ 
+#define DP83848_PHY_ADDRESS           0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32f1xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f1xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+   
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f1xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f1xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */  
+   
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f1xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f1xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f1xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f1xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f1xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f1xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f1xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f1xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f1xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f1xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */ 
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */  
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f1xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f1xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */     
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f1xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f1xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f1xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f1xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f1xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f1xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f1xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */   
+   
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Inc/stm32f1xx_it.h

@@ -0,0 +1,69 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_IT_H
+#define __STM32F1xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Src/main.c

@@ -0,0 +1,391 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+SD_HandleTypeDef hsd;
+
+SPI_HandleTypeDef hspi1;
+SPI_HandleTypeDef hspi2;
+SPI_HandleTypeDef hspi3;
+
+UART_HandleTypeDef huart1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART1_UART_Init(void);
+static void MX_SDIO_SD_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_SPI2_Init(void);
+static void MX_SPI3_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART1_UART_Init();
+  MX_SDIO_SD_Init();
+  MX_SPI1_Init();
+  MX_SPI2_Init();
+  MX_SPI3_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief SDIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDIO_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDIO_Init 0 */
+
+  /* USER CODE END SDIO_Init 0 */
+
+  /* USER CODE BEGIN SDIO_Init 1 */
+
+  /* USER CODE END SDIO_Init 1 */
+  hsd.Instance = SDIO;
+  hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+  hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+  hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
+  hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd.Init.ClockDiv = 0;
+  if (HAL_SD_Init(&hsd) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SDIO_Init 2 */
+
+  /* USER CODE END SDIO_Init 2 */
+
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 10;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+  * @brief SPI2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI2_Init(void)
+{
+
+  /* USER CODE BEGIN SPI2_Init 0 */
+
+  /* USER CODE END SPI2_Init 0 */
+
+  /* USER CODE BEGIN SPI2_Init 1 */
+
+  /* USER CODE END SPI2_Init 1 */
+  /* SPI2 parameter configuration*/
+  hspi2.Instance = SPI2;
+  hspi2.Init.Mode = SPI_MODE_MASTER;
+  hspi2.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi2.Init.NSS = SPI_NSS_SOFT;
+  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi2.Init.CRCPolynomial = 10;
+  if (HAL_SPI_Init(&hspi2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI2_Init 2 */
+
+  /* USER CODE END SPI2_Init 2 */
+
+}
+
+/**
+  * @brief SPI3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI3_Init(void)
+{
+
+  /* USER CODE BEGIN SPI3_Init 0 */
+
+  /* USER CODE END SPI3_Init 0 */
+
+  /* USER CODE BEGIN SPI3_Init 1 */
+
+  /* USER CODE END SPI3_Init 1 */
+  /* SPI3 parameter configuration*/
+  hspi3.Instance = SPI3;
+  hspi3.Init.Mode = SPI_MODE_MASTER;
+  hspi3.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi3.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi3.Init.NSS = SPI_NSS_SOFT;
+  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi3.Init.CRCPolynomial = 10;
+  if (HAL_SPI_Init(&hspi3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI3_Init 2 */
+
+  /* USER CODE END SPI3_Init 2 */
+
+}
+
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c

@@ -0,0 +1,401 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32f1xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_AFIO_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled 
+  */
+  __HAL_AFIO_REMAP_SWJ_NOJTAG();
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hsd->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspInit 0 */
+
+  /* USER CODE END SDIO_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDIO_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDIO GPIO Configuration    
+    PC8     ------> SDIO_D0
+    PC9     ------> SDIO_D1
+    PC10     ------> SDIO_D2
+    PC11     ------> SDIO_D3
+    PC12     ------> SDIO_CK
+    PD2     ------> SDIO_CMD 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SDIO_MspInit 1 */
+
+  /* USER CODE END SDIO_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspDeInit 0 */
+
+  /* USER CODE END SDIO_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDIO_CLK_DISABLE();
+  
+    /**SDIO GPIO Configuration    
+    PC8     ------> SDIO_D0
+    PC9     ------> SDIO_D1
+    PC10     ------> SDIO_D2
+    PC11     ------> SDIO_D3
+    PC12     ------> SDIO_CK
+    PD2     ------> SDIO_CMD 
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+  /* USER CODE BEGIN SDIO_MspDeInit 1 */
+
+  /* USER CODE END SDIO_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+  else if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspInit 0 */
+
+  /* USER CODE END SPI2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI2 GPIO Configuration    
+    PB13     ------> SPI2_SCK
+    PB14     ------> SPI2_MISO
+    PB15     ------> SPI2_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI2_MspInit 1 */
+
+  /* USER CODE END SPI2_MspInit 1 */
+  }
+  else if(hspi->Instance==SPI3)
+  {
+  /* USER CODE BEGIN SPI3_MspInit 0 */
+
+  /* USER CODE END SPI3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI3_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI3 GPIO Configuration    
+    PB3     ------> SPI3_SCK
+    PB4     ------> SPI3_MISO
+    PB5     ------> SPI3_MOSI 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI3_MspInit 1 */
+
+  /* USER CODE END SPI3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+  
+    /**SPI1 GPIO Configuration    
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PA7     ------> SPI1_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+  else if(hspi->Instance==SPI2)
+  {
+  /* USER CODE BEGIN SPI2_MspDeInit 0 */
+
+  /* USER CODE END SPI2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI2_CLK_DISABLE();
+  
+    /**SPI2 GPIO Configuration    
+    PB13     ------> SPI2_SCK
+    PB14     ------> SPI2_MISO
+    PB15     ------> SPI2_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+  /* USER CODE BEGIN SPI2_MspDeInit 1 */
+
+  /* USER CODE END SPI2_MspDeInit 1 */
+  }
+  else if(hspi->Instance==SPI3)
+  {
+  /* USER CODE BEGIN SPI3_MspDeInit 0 */
+
+  /* USER CODE END SPI3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI3_CLK_DISABLE();
+  
+    /**SPI3 GPIO Configuration    
+    PB3     ------> SPI3_SCK
+    PB4     ------> SPI3_MISO
+    PB5     ------> SPI3_MOSI 
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);
+
+  /* USER CODE BEGIN SPI3_MspDeInit 1 */
+
+  /* USER CODE END SPI3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspInit 0 */
+
+  /* USER CODE END USART1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART1 GPIO Configuration    
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART1_MspInit 1 */
+
+  /* USER CODE END USART1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+  /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+  /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+  
+    /**USART1 GPIO Configuration    
+    PA9     ------> USART1_TX
+    PA10     ------> USART1_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+  /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+  /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Src/stm32f1xx_it.c

@@ -0,0 +1,203 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f1xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f1xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M3 Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Prefetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F1xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f1xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/CubeMX_Config/Src/system_stm32f1xx.c

@@ -0,0 +1,448 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f1xx.c
+  * @author  MCD Application Team
+  * @version V4.2.0
+  * @date    31-March-2017
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  * 
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      factors, AHB/APBx prescalers and Flash settings). 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f1xx_xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
+  *    the product used), refer to "HSE_VALUE". 
+  *    When HSE is used as system clock source, directly or through PLL, and you
+  *    are using different crystal you have to adapt the HSE value to your own
+  *    configuration.
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f1xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F1xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f1xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Defines
+  * @{
+  */
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.
+                                                This value can be provided and adapted by the user application. */
+#endif /* HSI_VALUE */
+
+/*!< Uncomment the following line if you need to use external SRAM  */ 
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */ 
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field. 
+                                  This value must be a multiple of 0x200. */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Variables
+  * @{
+  */
+
+/*******************************************************************************
+*  Clock Definitions
+*******************************************************************************/
+#if defined(STM32F100xB) ||defined(STM32F100xE)
+  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
+#else /*!< HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
+#endif
+
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F1xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemCoreClock variable.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= 0x00000001U;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#if !defined(STM32F105xC) && !defined(STM32F107xC)
+  RCC->CFGR &= 0xF8FF0000U;
+#else
+  RCC->CFGR &= 0xF0FF0000U;
+#endif /* STM32F105xC */   
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= 0xFEF6FFFFU;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= 0xFF80FFFFU;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEBFFFFFFU;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;
+#elif defined(STM32F100xB) || defined(STM32F100xE)
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000U;      
+#else
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000U;
+#endif /* STM32F105xC */
+    
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+  #ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl(); 
+  #endif /* DATA_IN_ExtSRAM */
+#endif 
+
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif 
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
+  *             8 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
+  *              8 MHz or 25 MHz, depending on the product used), user has to ensure
+  *              that HSE_VALUE is same as the real frequency of the crystal used.
+  *              Otherwise, this function may have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
+
+#if defined(STM32F105xC) || defined(STM32F107xC)
+  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
+#endif /* STM32F105xC */
+
+#if defined(STM32F100xB) || defined(STM32F100xE)
+  uint32_t prediv1factor = 0U;
+#endif /* STM32F100xB or STM32F100xE */
+    
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00U:  /* HSI used as system clock */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08U:  /* PLL used as system clock */
+
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+      
+#if !defined(STM32F105xC) && !defined(STM32F107xC)      
+      pllmull = ( pllmull >> 18U) + 2U;
+      
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {
+ #if defined(STM32F100xB) || defined(STM32F100xE)
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+       /* HSE oscillator clock selected as PREDIV1 clock entry */
+       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
+ #else
+        /* HSE selected as PLL clock entry */
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
+        {/* HSE oscillator clock divided by 2 */
+          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+ #endif
+      }
+#else
+      pllmull = pllmull >> 18U;
+      
+      if (pllmull != 0x0DU)
+      {
+         pllmull += 2U;
+      }
+      else
+      { /* PLL multiplication factor = PLL input clock * 6.5 */
+        pllmull = 13U / 2U; 
+      }
+            
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
+      }
+      else
+      {/* PREDIV1 selected as PLL clock entry */
+        
+        /* Get PREDIV1 clock source and division factor */
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
+        
+        if (prediv1source == 0U)
+        { 
+          /* HSE oscillator clock selected as PREDIV1 clock entry */
+          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
+        }
+        else
+        {/* PLL2 clock selected as PREDIV1 clock entry */
+          
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; 
+          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
+        }
+      }
+#endif /* STM32F105xC */ 
+      break;
+
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  
+  /* Compute HCLK clock frequency ----------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;  
+}
+
+#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller. 
+  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
+  *         This function configures the external SRAM mounted on STM3210E-EVAL
+  *         board (STM32 High density devices). This SRAM will be used as program
+  *         data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */ 
+void SystemInit_ExtMemCtl(void) 
+{
+  __IO uint32_t tmpreg;
+  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
+    required, then adjust the Register Addresses */
+
+  /* Enable FSMC clock */
+  RCC->AHBENR = 0x00000114U;
+
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
+  
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
+  RCC->APB2ENR = 0x000001E0U;
+  
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
+
+  (void)(tmpreg);
+  
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
+/*----------------  SRAM Address lines configuration -------------------------*/
+/*----------------  NOE and NWE configuration --------------------------------*/  
+/*----------------  NE3 configuration ----------------------------------------*/
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/
+  
+  GPIOD->CRL = 0x44BB44BBU;  
+  GPIOD->CRH = 0xBBBBBBBBU;
+
+  GPIOE->CRL = 0xB44444BBU;  
+  GPIOE->CRH = 0xBBBBBBBBU;
+
+  GPIOF->CRL = 0x44BBBBBBU;  
+  GPIOF->CRH = 0xBBBB4444U;
+
+  GPIOG->CRL = 0x44BBBBBBU;  
+  GPIOG->CRH = 0x444B4B44U;
+   
+/*----------------  FSMC Configuration ---------------------------------------*/  
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
+  
+  FSMC_Bank1->BTCR[4U] = 0x00001091U;
+  FSMC_Bank1->BTCR[5U] = 0x00110212U;
+}
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/Kconfig

@@ -0,0 +1,152 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32F103ZE
+    bool
+    select SOC_SERIES_STM32F1
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_SDIO_SDCARD
+        bool "Enable SDCARD (sdio)"
+        select BSP_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        select RT_USING_PIN
+        default n
+        
+    config BSP_USING_SPI_SDCARD
+        bool "Enable SDCARD (spi2)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI2
+        select RT_USING_SPI_MSD
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        default n
+        
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (W25Q64 spi2)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI2
+        select RT_USING_SFUD
+        select RT_SFUD_USING_SFDP
+        default n
+        
+    config BSP_USING_EEPROM
+        bool "Enable I2C EEPROM (i2c2)"
+        select BSP_USING_I2C2
+        default n
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+
+        endif
+        
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                depends on BSP_USING_SPI1
+                default n
+                
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                depends on BSP_USING_SPI1
+                select BSP_SPI1_TX_USING_DMA
+                default n
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n  
+                
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                depends on BSP_USING_SPI2
+                default n
+                
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                depends on BSP_USING_SPI2
+                select BSP_SPI2_TX_USING_DMA
+                default n
+                
+            config BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n        
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                depends on BSP_USING_SPI3
+                default n
+                
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                depends on BSP_USING_SPI3
+                select BSP_SPI3_TX_USING_DMA
+                default n  
+        endif
+        
+    menuconfig BSP_USING_I2C2
+        bool "Enable I2C2 BUS (software simulation)"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C2
+            comment "Notice: PB10 --> 26; PB11 --> 27" 
+            config BSP_I2C2_SCL_PIN
+                int "i2c2 scl pin number"
+                range 0 175
+                default 26
+            config BSP_I2C2_SDA_PIN
+                int "i2c2 sda pin number"
+                range 0 175
+                default 27
+        endif
+        
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+        
+    config BSP_USING_SDIO
+        bool "Enable SDIO"
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        default n
+    source "libraries/HAL_Drivers/Kconfig"
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+    config BSP_USING_NRF24L01
+        bool "Enable NRF24L01"
+        select BSP_USING_SPI
+        select BSP_USING_SPI2
+        select PKG_USING_NRF24L01
+        default n
+
+endmenu
+
+endmenu

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/SConscript

@@ -0,0 +1,45 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+CubeMX_Config/Src/stm32f1xx_hal_msp.c
+''')
+
+if GetDepend(['BSP_USING_SDIO_SDCARD']):
+    src += Glob('ports/drv_sdcard.c')
+    
+if GetDepend(['BSP_USING_SPI_SDCARD']):
+    src += Glob('ports/drv_sdcard.c')
+    
+if GetDepend(['BSP_USING_SPI_FLASH']):
+    src += Glob('ports/spi_flash_init.c')
+
+path =  [cwd]
+path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/gcc/startup_stm32f103xe.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/arm/startup_stm32f103xe.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/STM32F1xx_HAL/CMSIS/Device/ST/STM32F1xx/Source/Templates/iar/startup_stm32f103xe.s']
+
+# STM32F100xB || STM32F100xE || STM32F101x6
+# STM32F101xB || STM32F101xE || STM32F101xG
+# STM32F102x6 || STM32F102xB || STM32F103x6
+# STM32F103xB || STM32F103xE || STM32F103xG
+# STM32F105xC || STM32F107xC)
+# You can select chips from the list above
+CPPDEFINES = ['STM32F103xE']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/board.c

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-04-09     WillianChan  add stm32f103-dofly-M3S BSP
+ */
+ 
+#include "board.h"
+
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/board.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-5      SummerGift   first version
+ * 2019-04-09     WillianChan  add stm32f103-dofly-M3S BSP
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32f1xx.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (512 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
+#define STM32_SRAM_SIZE      64
+#define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END        STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/linker_scripts/link.icf

@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/linker_scripts/link.lds

@@ -0,0 +1,156 @@
+/*
+ * linker script for STM32F10x with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  64k /* 64K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00010000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/ports/drv_sdcard.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2018-12-13     balanceTWK    add sdcard port file
+ * 2019-08-23     WillianChan   add spi sdcard port code
+ */
+
+#include <rtthread.h>
+
+#if defined BSP_USING_SDIO_SDCARD || defined BSP_USING_SPI_SDCARD
+#include <dfs_elm.h>
+#include <dfs_fs.h>
+#include <dfs_posix.h>
+#include "drv_gpio.h"
+
+#define DBG_TAG "app.card"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+void sd_mount(void *parameter)
+{
+    while (1)
+    {
+        rt_thread_mdelay(500);
+        if(rt_device_find("sd0") != RT_NULL)
+        {
+            if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
+            {
+                LOG_I("sd card mount to '/'");
+                break;
+            }
+            else
+            {
+                LOG_W("sd card mount to '/' failed!");
+            }
+        }
+    }
+}
+
+int stm32_sdcard_mount(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                           1024, RT_THREAD_PRIORITY_MAX - 2, 20);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("create sd_mount thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(stm32_sdcard_mount);
+#endif /* BSP_USING_SDIO_SDCARD || BSP_USING_SPI_SDCARD */
+
+#ifdef BSP_USING_SPI_SDCARD
+#include "drv_spi.h"
+#include "spi_msd.h"
+static int rt_hw_spi2_tfcard(void)
+{
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    rt_hw_spi_device_attach("spi2", "spi20", GPIOD, GPIO_PIN_2);
+    return msd_init("sd0", "spi20");
+}
+INIT_DEVICE_EXPORT(rt_hw_spi2_tfcard);
+#endif /* BSP_USING_SPI_SDCARD */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/ports/fal_cfg.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev stm32_onchip_flash;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &stm32_onchip_flash,                                             \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                      \
+{                                                                                           \
+    {FAL_PART_MAGIC_WROD,        "app",   "onchip_flash",       0,          496 * 1024, 0}, \
+    {FAL_PART_MAGIC_WROD,        "param", "onchip_flash",       496* 1024 , 16 * 1024, 0},  \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/board/ports/spi_flash_init.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-27     SummerGift   add spi flash port file
+ */
+
+#include <rtthread.h>
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+#include "drv_spi.h"
+
+#if defined(BSP_USING_SPI_FLASH)
+static int rt_hw_spi_flash_init(void)
+{
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    rt_hw_spi_device_attach("spi2", "spi20", GPIOB, GPIO_PIN_12);
+
+    if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi20"))
+    {
+        return -RT_ERROR;
+    };
+
+    return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
+#endif
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/Kconfig

@@ -0,0 +1,23 @@
+
+config BSP_USING_CRC
+    bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRC
+    # "Crypto device frame dose not support above 8-bits granularity"
+    # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7)
+    default n 
+
+config BSP_USING_RNG
+    bool "Enable RNG (Random Number Generator)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_RNG
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
+                SOC_SERIES_STM32H7)
+    default n
+    
+config BSP_USING_UDID
+    bool "Enable UDID (Unique Device Identifier)"
+    select RT_USING_HWCRYPTO
+    default n
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,98 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
+    src += ['drv_pm.c']
+    src += ['drv_lptim.c']
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+
+if GetDepend('BSP_USING_LCD_MIPI'):
+    src += ['drv_lcd_mipi.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
+    src += ['drv_flash/drv_flash_f0.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
+    src += ['drv_flash/drv_flash_f1.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
+    src += ['drv_flash/drv_flash_f2.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
+    src += ['drv_flash/drv_flash_f4.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
+    src += ['drv_flash/drv_flash_f7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
+    src += ['drv_flash/drv_flash_l4.c']
+	
+if GetDepend('RT_USING_HWCRYPTO'):
+    src += ['drv_crypto.c']
+	
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['BSP_USING_USBD_FS']):
+    src += ['drv_usbd_fs.c']
+
+src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    path += [cwd + '/drv_flash']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/adc_config.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel2-3 DMA2 channel1-2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
+#define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+
+#if  defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+/* DMA1 channel2-3 DMA2 channel1-2 */
+
+/* DMA1 channel4-7 DMA2 channel3-5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#endif
+/* DMA1 channel4-7 DMA2 channel3-5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/spi_config.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM14,         \
+       .tim_irqn                = TIM14_IRQn,    \
+       .name                    = "timer14",     \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM16,         \
+       .tim_irqn                = TIM16_IRQn,    \
+       .name                    = "timer16",     \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM17,         \
+       .tim_irqn                = TIM17_IRQn,    \
+       .name                    = "timer17",     \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f0/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+    
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/adc_config.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC1,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC2,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC3,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/dma_config.h

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-02     SummerGift   first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler         DMA1_Channel2_IRQHandler
+#define UART3_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE           DMA1_Channel2
+#define UART3_TX_DMA_IRQ                DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE           DMA1_Channel7
+#define UART2_TX_DMA_IRQ                DMA1_Channel7_IRQn
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
+#define SPI3_RX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_RX_DMA_INSTANCE            DMA2_Channel1
+#define SPI3_RX_DMA_IRQ                 DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
+#define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART4_RX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_RX_DMA_INSTANCE           DMA2_Channel3
+#define UART4_RX_DMA_IRQ                DMA2_Channel3_IRQn
+#endif
+/* DMA2 channel4 */
+/* DMA2 channel5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler         DMA2_Channel4_5_IRQHandler
+#define UART4_TX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_TX_DMA_INSTANCE           DMA2_Channel5
+#define UART4_TX_DMA_IRQ                DMA2_Channel4_5_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/sdio_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f1xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel4,                \
+        .dma_tx.dma_irq = DMA2_Channel4_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/spi_config.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/tim_config.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/uart_config.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     BalanceTWK   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f1/usbd_fs_config.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-07-29     Chinese66    change from f4 to f1
+ */
+#ifndef __USBD_FS_CONFIG_H__
+#define __USBD_FS_CONFIG_H__
+
+#define USBD_FS_IRQ_HANDLER  USB_LP_CAN1_RX0_IRQHandler
+#define USBD_INSTANCE        USB
+#define BSP_USB_CONNECT_PIN  -1
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/dma_config.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART6_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART6_RX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+/* DMA2 stream3 */
+
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)	
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+
+/* DMA2 stream7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f2xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/spi_config.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/tim_config.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef BSP_USING_TIM7
+#ifndef TIM7_CONFIG
+#define TIM7_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM7,         \
+       .tim_irqn                = TIM7_IRQn,    \
+       .name                    = "timer7",     \
+    }
+#endif /* TIM7_CONFIG */
+#endif /* BSP_USING_TIM7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f2/uart_config.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE            DMA1_Stream3
+#define UART3_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_TX_DMA_IRQ                 DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_TX_DMA_INSTANCE            DMA1_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_TX_DMA_IRQ                 DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream6
+#define UART2_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_TX_DMA_IRQ                 DMA1_Stream6_IRQn
+#endif
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_TX_DMA_INSTANCE            DMA1_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler          DMA2_Stream1_IRQHandler
+#define UART6_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE            DMA2_Stream1
+#define UART6_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                 DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_DMA_TX_IRQHandler         DMA2_Stream6_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_TX_DMA_INSTANCE           DMA2_Stream6
+#define UART6_TX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_TX_DMA_IRQ                DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Stream7_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Stream7
+#define UART1_TX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_TX_DMA_IRQ                DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/spi_config.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-03     zylx         modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/uart_config.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f4/usbd_fs_config.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ */
+#ifndef __USBD_FS_CONFIG_H__
+#define __USBD_FS_CONFIG_H__
+
+#define USBD_FS_IRQ_HANDLER OTG_FS_IRQHandler
+#define USBD_INSTANCE       USB_OTG_FS
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/dma_config.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/f7/uart_config.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/adc_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/dma_config.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA1_Channel1_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE             DMA1_Channel1
+#define SPI1_RX_DMA_REQUEST              DMA_REQUEST_SPI1_RX
+#define SPI1_RX_DMA_IRQ                  DMA1_Channel1_IRQn
+#ifdef BSP_UART1_RX_USING_DMA
+#undef BSP_UART1_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel1
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#define UART1_RX_DMA_IRQ                DMA1_Channel1_IRQn
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel1_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel1
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel1_IRQn
+#endif
+
+/* DMA1 channle2-3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#ifdef BSP_UART2_RX_USING_DMA
+#undef BSP_UART2_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel2_3_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel2
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                DMA1_Channel2_3_IRQn
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#endif
+
+#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHBENR_DMA1EN
+#define LPUART1_RX_DMA_INSTANCE         DMA1_Channel5
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#define LPUART1_RX_DMA_IRQ              DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/pwm_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/spi_config.h

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .request = SPI1_TX_DMA_REQUEST,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .request = SPI1_RX_DMA_REQUEST,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .request = SPI2_TX_DMA_REQUEST,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .request = SPI2_RX_DMA_REQUEST,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/tim_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/g0/uart_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#define LPUART1_IRQHandler      USART3_4_LPUART1_IRQHandler
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request =  LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request =  UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request =  UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#else
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request =  UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#else
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = USART4,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* UART4_CONFIG */
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request =  UART4_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/dma_config.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32h7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/h7/uart_config.h

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l0/dma_config.h

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Channel4_5_6_7_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART1_RX_DMA_IRQ                 DMA1_Channel4_5_6_7_IRQn
+#endif
+/* DMA1 channel5 */
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Channel4_5_6_7_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel6
+#define UART2_RX_DMA_IRQ                 DMA1_Channel4_5_6_7_IRQn
+#endif
+/* DMA1 channel6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l0/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+    
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/adc_config.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,              \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 1,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/dma_config.h

@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
+#define QSPI_DMA_INSTANCE               DMA1_Channel5
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
+#define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_TX_DMA_INSTANCE           DMA2_Channel1
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_RX_DMA_INSTANCE           DMA2_Channel2
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
+#endif
+
+/* DMA2 channel5 */
+
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE               DMA2_Channel7
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
+#define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
+#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA2_Channel7_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHB1ENR_DMA2EN
+#define LPUART1_RX_DMA_INSTANCE         DMA2_Channel7
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_4
+#define LPUART1_RX_DMA_IRQ              DMA2_Channel7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+    
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Request = QSPI_DMA_REQUEST,                      \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32l4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.request = DMA_REQUEST_7,                 \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel5,                \
+        .dma_tx.request = DMA_REQUEST_7,                 \
+        .dma_tx.dma_irq = DMA2_Channel5_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/spi_config.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI2,                                \
+        .bus_name = "spi2",                              \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#define SPI3_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI3,                                \
+        .bus_name = "spi3",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Channel1,                \
+        .dma_rx.request = DMA_REQUEST_3,                 \
+        .dma_rx.dma_irq = DMA2_Channel1_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel2,                \
+        .dma_tx.request = DMA_REQUEST_3,                 \
+        .dma_tx.dma_irq = DMA2_Channel2_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-12     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/uart_config.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */  
+   
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

bsp/stm32/stm32f103-dofly-M3S/dist/stm32f103-dofly-M3S/libraries/HAL_Drivers/config/l4/usbd_fs_config.h

@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ */
+#ifndef __USBD_FS_CONFIG_H__
+#define __USBD_FS_CONFIG_H__
+
+#define USBD_FS_IRQ_HANDLER OTG_FS_IRQHandler
+#define USBD_INSTANCE       USB_OTG_FS
+#endif